1 /* 2 * Extended Trap data component interface file. 3 * 4 * Copyright (C) 1999-2019, Broadcom. 5 * 6 * Unless you and Broadcom execute a separate written software license 7 * agreement governing use of this software, this software is licensed to you 8 * under the terms of the GNU General Public License version 2 (the "GPL"), 9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 10 * following added to such license: 11 * 12 * As a special exception, the copyright holders of this software give you 13 * permission to link this software with independent modules, and to copy and 14 * distribute the resulting executable under terms of your choice, provided that 15 * you also meet, for each linked independent module, the terms and conditions 16 * of the license of that module. An independent module is a module which is 17 * not derived from this software. The special exception does not apply to any 18 * modifications of the software. 19 * 20 * Notwithstanding the above, under no circumstances may you combine this 21 * software in any way with any other Broadcom software provided under a license 22 * other than the GPL, without Broadcom's express prior written consent. 23 * 24 * 25 * <<Broadcom-WL-IPTag/Open:>> 26 * 27 * $Id: etd.h 813064 2019-04-03 11:29:38Z $ 28 */ 29 30 #ifndef _ETD_H_ 31 #define _ETD_H_ 32 33 #if defined(ETD) && !defined(WLETD) 34 #include <hnd_trap.h> 35 #endif // endif 36 #include <bcmutils.h> 37 /* Tags for structures being used by etd info iovar. 38 * Related structures are defined in wlioctl.h. 39 */ 40 #define ETD_TAG_JOIN_CLASSIFICATION_INFO \ 41 10 /* general information about join request */ 42 #define ETD_TAG_JOIN_TARGET_CLASSIFICATION_INFO \ 43 11 /* per target (AP) join information */ 44 #define ETD_TAG_ASSOC_STATE \ 45 12 /* current state of the Device association state machine */ 46 #define ETD_TAG_CHANNEL \ 47 13 /* current channel on which the association was performed */ 48 #define ETD_TAG_TOTAL_NUM_OF_JOIN_ATTEMPTS \ 49 14 /* number of join attempts (bss_retries) */ 50 51 #define PSMDBG_REG_READ_CNT_FOR_PSMWDTRAP_V1 3 52 #define PSMDBG_REG_READ_CNT_FOR_PSMWDTRAP_V2 6 53 54 #ifndef _LANGUAGE_ASSEMBLY 55 56 #define HND_EXTENDED_TRAP_VERSION 1 57 #define HND_EXTENDED_TRAP_BUFLEN 512 58 59 typedef struct hnd_ext_trap_hdr { 60 uint8 version; /* Extended trap version info */ 61 uint8 reserved; /* currently unused */ 62 uint16 len; /* Length of data excluding this header */ 63 uint8 data[]; /* TLV data */ 64 } hnd_ext_trap_hdr_t; 65 66 typedef enum { 67 TAG_TRAP_NONE = 0, /* None trap type */ 68 TAG_TRAP_SIGNATURE = 1, /* Processor register dumps */ 69 TAG_TRAP_STACK = 2, /* Processor stack dump (possible code locations) */ 70 TAG_TRAP_MEMORY = 3, /* Memory subsystem dump */ 71 TAG_TRAP_DEEPSLEEP = 4, /* Deep sleep health check failures */ 72 TAG_TRAP_PSM_WD = 5, /* PSM watchdog information */ 73 TAG_TRAP_PHY = 6, /* Phy related issues */ 74 TAG_TRAP_BUS = 7, /* Bus level issues */ 75 TAG_TRAP_MAC_SUSP = 8, /* Mac level suspend issues */ 76 TAG_TRAP_BACKPLANE = 9, /* Backplane related errors */ 77 /* Values 10 through 14 are in use by etd_data info iovar */ 78 TAG_TRAP_PCIE_Q = 15, /* PCIE Queue state during memory trap */ 79 TAG_TRAP_WLC_STATE = 16, /* WLAN state during memory trap */ 80 TAG_TRAP_MAC_WAKE = 17, /* Mac level wake issues */ 81 TAG_TRAP_PHYTXERR_THRESH = 18, /* Phy Tx Err */ 82 TAG_TRAP_HC_DATA = 19, /* Data collected by HC module */ 83 TAG_TRAP_LOG_DATA = 20, 84 TAG_TRAP_CODE = 21, /* The trap type */ 85 TAG_TRAP_HMAP = 22, /* HMAP violation Address and Info */ 86 TAG_TRAP_PCIE_ERR_ATTN = 23, /* PCIE error attn log */ 87 TAG_TRAP_AXI_ERROR = 24, /* AXI Error */ 88 TAG_TRAP_AXI_HOST_INFO = 25, /* AXI Host log */ 89 TAG_TRAP_AXI_SR_ERROR = 26, /* AXI SR error log */ 90 TAG_TRAP_LAST /* This must be the last entry */ 91 } hnd_ext_tag_trap_t; 92 93 typedef struct hnd_ext_trap_bp_err { 94 uint32 error; 95 uint32 coreid; 96 uint32 baseaddr; 97 uint32 ioctrl; 98 uint32 iostatus; 99 uint32 resetctrl; 100 uint32 resetstatus; 101 uint32 resetreadid; 102 uint32 resetwriteid; 103 uint32 errlogctrl; 104 uint32 errlogdone; 105 uint32 errlogstatus; 106 uint32 errlogaddrlo; 107 uint32 errlogaddrhi; 108 uint32 errlogid; 109 uint32 errloguser; 110 uint32 errlogflags; 111 uint32 itipoobaout; 112 uint32 itipoobbout; 113 uint32 itipoobcout; 114 uint32 itipoobdout; 115 } hnd_ext_trap_bp_err_t; 116 117 #define HND_EXT_TRAP_AXISR_INFO_VER_1 1 118 typedef struct hnd_ext_trap_axi_sr_err_v1 { 119 uint8 version; 120 uint8 pad[3]; 121 uint32 error; 122 uint32 coreid; 123 uint32 baseaddr; 124 uint32 ioctrl; 125 uint32 iostatus; 126 uint32 resetctrl; 127 uint32 resetstatus; 128 uint32 resetreadid; 129 uint32 resetwriteid; 130 uint32 errlogctrl; 131 uint32 errlogdone; 132 uint32 errlogstatus; 133 uint32 errlogaddrlo; 134 uint32 errlogaddrhi; 135 uint32 errlogid; 136 uint32 errloguser; 137 uint32 errlogflags; 138 uint32 itipoobaout; 139 uint32 itipoobbout; 140 uint32 itipoobcout; 141 uint32 itipoobdout; 142 143 /* axi_sr_issue_debug */ 144 uint32 sr_pwr_control; 145 uint32 sr_corereset_wrapper_main; 146 uint32 sr_corereset_wrapper_aux; 147 uint32 sr_main_gci_status_0; 148 uint32 sr_aux_gci_status_0; 149 uint32 sr_dig_gci_status_0; 150 } hnd_ext_trap_axi_sr_err_v1_t; 151 152 #define HND_EXT_TRAP_PSMWD_INFO_VER 1 153 typedef struct hnd_ext_trap_psmwd_v1 { 154 uint16 xtag; 155 uint16 version; /* version of the information following this */ 156 uint32 i32_maccontrol; 157 uint32 i32_maccommand; 158 uint32 i32_macintstatus; 159 uint32 i32_phydebug; 160 uint32 i32_clk_ctl_st; 161 uint32 i32_psmdebug[PSMDBG_REG_READ_CNT_FOR_PSMWDTRAP_V1]; 162 uint16 i16_0x1a8; /* gated clock en */ 163 uint16 i16_0x406; /* Rcv Fifo Ctrl */ 164 uint16 i16_0x408; /* Rx ctrl 1 */ 165 uint16 i16_0x41a; /* Rxe Status 1 */ 166 uint16 i16_0x41c; /* Rxe Status 2 */ 167 uint16 i16_0x424; /* rcv wrd count 0 */ 168 uint16 i16_0x426; /* rcv wrd count 1 */ 169 uint16 i16_0x456; /* RCV_LFIFO_STS */ 170 uint16 i16_0x480; /* PSM_SLP_TMR */ 171 uint16 i16_0x490; /* PSM BRC */ 172 uint16 i16_0x500; /* TXE CTRL */ 173 uint16 i16_0x50e; /* TXE Status */ 174 uint16 i16_0x55e; /* TXE_xmtdmabusy */ 175 uint16 i16_0x566; /* TXE_XMTfifosuspflush */ 176 uint16 i16_0x690; /* IFS Stat */ 177 uint16 i16_0x692; /* IFS_MEDBUSY_CTR */ 178 uint16 i16_0x694; /* IFS_TX_DUR */ 179 uint16 i16_0x6a0; /* SLow_CTL */ 180 uint16 i16_0x838; /* TXE_AQM fifo Ready */ 181 uint16 i16_0x8c0; /* Dagg ctrl */ 182 uint16 shm_prewds_cnt; 183 uint16 shm_txtplufl_cnt; 184 uint16 shm_txphyerr_cnt; 185 uint16 pad; 186 } hnd_ext_trap_psmwd_v1_t; 187 188 typedef struct hnd_ext_trap_psmwd { 189 uint16 xtag; 190 uint16 version; /* version of the information following this */ 191 uint32 i32_maccontrol; 192 uint32 i32_maccommand; 193 uint32 i32_macintstatus; 194 uint32 i32_phydebug; 195 uint32 i32_clk_ctl_st; 196 uint32 i32_psmdebug[PSMDBG_REG_READ_CNT_FOR_PSMWDTRAP_V2]; 197 uint16 i16_0x4b8; /* psm_brwk_0 */ 198 uint16 i16_0x4ba; /* psm_brwk_1 */ 199 uint16 i16_0x4bc; /* psm_brwk_2 */ 200 uint16 i16_0x4be; /* psm_brwk_2 */ 201 uint16 i16_0x1a8; /* gated clock en */ 202 uint16 i16_0x406; /* Rcv Fifo Ctrl */ 203 uint16 i16_0x408; /* Rx ctrl 1 */ 204 uint16 i16_0x41a; /* Rxe Status 1 */ 205 uint16 i16_0x41c; /* Rxe Status 2 */ 206 uint16 i16_0x424; /* rcv wrd count 0 */ 207 uint16 i16_0x426; /* rcv wrd count 1 */ 208 uint16 i16_0x456; /* RCV_LFIFO_STS */ 209 uint16 i16_0x480; /* PSM_SLP_TMR */ 210 uint16 i16_0x500; /* TXE CTRL */ 211 uint16 i16_0x50e; /* TXE Status */ 212 uint16 i16_0x55e; /* TXE_xmtdmabusy */ 213 uint16 i16_0x566; /* TXE_XMTfifosuspflush */ 214 uint16 i16_0x690; /* IFS Stat */ 215 uint16 i16_0x692; /* IFS_MEDBUSY_CTR */ 216 uint16 i16_0x694; /* IFS_TX_DUR */ 217 uint16 i16_0x6a0; /* SLow_CTL */ 218 uint16 i16_0x490; /* psm_brc */ 219 uint16 i16_0x4da; /* psm_brc_1 */ 220 uint16 i16_0x838; /* TXE_AQM fifo Ready */ 221 uint16 i16_0x8c0; /* Dagg ctrl */ 222 uint16 shm_prewds_cnt; 223 uint16 shm_txtplufl_cnt; 224 uint16 shm_txphyerr_cnt; 225 } hnd_ext_trap_psmwd_t; 226 227 #define HEAP_HISTOGRAM_DUMP_LEN 6 228 #define HEAP_MAX_SZ_BLKS_LEN 2 229 230 /* Ignore chunks for which there are fewer than this many instances, 231 * irrespective of size */ 232 #define HEAP_HISTOGRAM_INSTANCE_MIN 4 233 234 /* 235 * Use the last two length values for chunks larger than this, or when we run 236 * out of histogram entries (because we have too many different sized chunks) to 237 * store "other" 238 */ 239 #define HEAP_HISTOGRAM_SPECIAL 0xfffeu 240 241 #define HEAP_HISTOGRAM_GRTR256K 0xffffu 242 243 typedef struct hnd_ext_trap_heap_err { 244 uint32 arena_total; 245 uint32 heap_free; 246 uint32 heap_inuse; 247 uint32 mf_count; 248 uint32 stack_lwm; 249 uint16 heap_histogm[HEAP_HISTOGRAM_DUMP_LEN * 2]; /* size/number */ 250 uint16 max_sz_free_blk[HEAP_MAX_SZ_BLKS_LEN]; 251 } hnd_ext_trap_heap_err_t; 252 253 #define MEM_TRAP_NUM_WLC_TX_QUEUES 6 254 #define HND_EXT_TRAP_WLC_MEM_ERR_VER_V2 2 255 256 typedef struct hnd_ext_trap_wlc_mem_err { 257 uint8 instance; 258 uint8 associated; 259 uint8 soft_ap_client_cnt; 260 uint8 peer_cnt; 261 uint16 txqueue_len[MEM_TRAP_NUM_WLC_TX_QUEUES]; 262 } hnd_ext_trap_wlc_mem_err_t; 263 264 typedef struct hnd_ext_trap_wlc_mem_err_v2 { 265 uint16 version; 266 uint16 pad; 267 uint8 instance; 268 uint8 stas_associated; 269 uint8 aps_associated; 270 uint8 soft_ap_client_cnt; 271 uint16 txqueue_len[MEM_TRAP_NUM_WLC_TX_QUEUES]; 272 } hnd_ext_trap_wlc_mem_err_v2_t; 273 274 #define HND_EXT_TRAP_WLC_MEM_ERR_VER_V3 3 275 276 typedef struct hnd_ext_trap_wlc_mem_err_v3 { 277 uint8 version; 278 uint8 instance; 279 uint8 stas_associated; 280 uint8 aps_associated; 281 uint8 soft_ap_client_cnt; 282 uint8 peer_cnt; 283 uint16 txqueue_len[MEM_TRAP_NUM_WLC_TX_QUEUES]; 284 } hnd_ext_trap_wlc_mem_err_v3_t; 285 286 typedef struct hnd_ext_trap_pcie_mem_err { 287 uint16 d2h_queue_len; 288 uint16 d2h_req_queue_len; 289 } hnd_ext_trap_pcie_mem_err_t; 290 291 #define MAX_DMAFIFO_ENTRIES_V1 1 292 #define MAX_DMAFIFO_DESC_ENTRIES_V1 2 293 #define HND_EXT_TRAP_AXIERROR_SIGNATURE 0xbabebabe 294 #define HND_EXT_TRAP_AXIERROR_VERSION_1 1 295 296 /* Structure to collect debug info of descriptor entry for dma channel on 297 * encountering AXI Error */ 298 /* Below three structures are dependant, any change will bump version of all the 299 * three */ 300 301 typedef struct hnd_ext_trap_desc_entry_v1 { 302 uint32 ctrl1; /* descriptor entry at din < misc control bits > */ 303 uint32 ctrl2; /* descriptor entry at din <buffer count and address 304 extension> */ 305 uint32 addrlo; /* descriptor entry at din <address of data buffer, bits 306 31:0> */ 307 uint32 addrhi; /* descriptor entry at din <address of data buffer, bits 308 63:32> */ 309 } dma_dentry_v1_t; 310 311 /* Structure to collect debug info about a dma channel on encountering AXI Error 312 */ 313 typedef struct hnd_ext_trap_dma_fifo_v1 { 314 uint8 valid; /* no of valid desc entries filled, non zero = fifo entry valid 315 */ 316 uint8 direction; /* TX=1, RX=2, currently only using TX */ 317 uint16 index; /* Index of the DMA channel in system */ 318 uint32 dpa; /* Expected Address of Descriptor table from software state */ 319 uint32 desc_lo; /* Low Address of Descriptor table programmed in DMA 320 register */ 321 uint32 desc_hi; /* High Address of Descriptor table programmed in DMA 322 register */ 323 uint16 din; /* rxin / txin */ 324 uint16 dout; /* rxout / txout */ 325 dma_dentry_v1_t 326 dentry[MAX_DMAFIFO_DESC_ENTRIES_V1]; /* Descriptor Entires */ 327 } dma_fifo_v1_t; 328 329 typedef struct hnd_ext_trap_axi_error_v1 { 330 uint8 version; /* version = 1 */ 331 uint8 dma_fifo_valid_count; /* Number of valid dma_fifo entries */ 332 uint16 length; /* length of whole structure */ 333 uint32 signature; /* indicate that its filled with AXI Error data */ 334 uint32 axi_errorlog_status; /* errlog_status from slave wrapper */ 335 uint32 axi_errorlog_core; /* errlog_core from slave wrapper */ 336 uint32 axi_errorlog_lo; /* errlog_lo from slave wrapper */ 337 uint32 axi_errorlog_hi; /* errlog_hi from slave wrapper */ 338 uint32 axi_errorlog_id; /* errlog_id from slave wrapper */ 339 dma_fifo_v1_t dma_fifo[MAX_DMAFIFO_ENTRIES_V1]; 340 } hnd_ext_trap_axi_error_v1_t; 341 342 #define HND_EXT_TRAP_MACSUSP_INFO_VER 1 343 typedef struct hnd_ext_trap_macsusp { 344 uint16 xtag; 345 uint8 version; /* version of the information following this */ 346 uint8 trap_reason; 347 uint32 i32_maccontrol; 348 uint32 i32_maccommand; 349 uint32 i32_macintstatus; 350 uint32 i32_phydebug[4]; 351 uint32 i32_psmdebug[8]; 352 uint16 i16_0x41a; /* Rxe Status 1 */ 353 uint16 i16_0x41c; /* Rxe Status 2 */ 354 uint16 i16_0x490; /* PSM BRC */ 355 uint16 i16_0x50e; /* TXE Status */ 356 uint16 i16_0x55e; /* TXE_xmtdmabusy */ 357 uint16 i16_0x566; /* TXE_XMTfifosuspflush */ 358 uint16 i16_0x690; /* IFS Stat */ 359 uint16 i16_0x692; /* IFS_MEDBUSY_CTR */ 360 uint16 i16_0x694; /* IFS_TX_DUR */ 361 uint16 i16_0x7c0; /* WEP CTL */ 362 uint16 i16_0x838; /* TXE_AQM fifo Ready */ 363 uint16 i16_0x880; /* MHP_status */ 364 uint16 shm_prewds_cnt; 365 uint16 shm_ucode_dbgst; 366 } hnd_ext_trap_macsusp_t; 367 368 #define HND_EXT_TRAP_MACENAB_INFO_VER 1 369 typedef struct hnd_ext_trap_macenab { 370 uint16 xtag; 371 uint8 version; /* version of the information following this */ 372 uint8 trap_reason; 373 uint32 i32_maccontrol; 374 uint32 i32_maccommand; 375 uint32 i32_macintstatus; 376 uint32 i32_psmdebug[8]; 377 uint32 i32_clk_ctl_st; 378 uint32 i32_powerctl; 379 uint16 i16_0x1a8; /* gated clock en */ 380 uint16 i16_0x480; /* PSM_SLP_TMR */ 381 uint16 i16_0x490; /* PSM BRC */ 382 uint16 i16_0x600; /* TSF CTL */ 383 uint16 i16_0x690; /* IFS Stat */ 384 uint16 i16_0x692; /* IFS_MEDBUSY_CTR */ 385 uint16 i16_0x6a0; /* SLow_CTL */ 386 uint16 i16_0x6a6; /* SLow_FRAC */ 387 uint16 i16_0x6a8; /* fast power up delay */ 388 uint16 i16_0x6aa; /* SLow_PER */ 389 uint16 shm_ucode_dbgst; 390 uint16 PAD; 391 } hnd_ext_trap_macenab_t; 392 393 #define HND_EXT_TRAP_PHY_INFO_VER_1 (1) 394 typedef struct hnd_ext_trap_phydbg { 395 uint16 err; 396 uint16 RxFeStatus; 397 uint16 TxFIFOStatus0; 398 uint16 TxFIFOStatus1; 399 uint16 RfseqMode; 400 uint16 RfseqStatus0; 401 uint16 RfseqStatus1; 402 uint16 RfseqStatus_Ocl; 403 uint16 RfseqStatus_Ocl1; 404 uint16 OCLControl1; 405 uint16 TxError; 406 uint16 bphyTxError; 407 uint16 TxCCKError; 408 uint16 TxCtrlWrd0; 409 uint16 TxCtrlWrd1; 410 uint16 TxCtrlWrd2; 411 uint16 TxLsig0; 412 uint16 TxLsig1; 413 uint16 TxVhtSigA10; 414 uint16 TxVhtSigA11; 415 uint16 TxVhtSigA20; 416 uint16 TxVhtSigA21; 417 uint16 txPktLength; 418 uint16 txPsdulengthCtr; 419 uint16 gpioClkControl; 420 uint16 gpioSel; 421 uint16 pktprocdebug; 422 uint16 PAD; 423 uint32 gpioOut[3]; 424 } hnd_ext_trap_phydbg_t; 425 426 /* unique IDs for separate cores in SI */ 427 #define REGDUMP_MASK_MAC0 BCM_BIT(1) 428 #define REGDUMP_MASK_ARM BCM_BIT(2) 429 #define REGDUMP_MASK_PCIE BCM_BIT(3) 430 #define REGDUMP_MASK_MAC1 BCM_BIT(4) 431 #define REGDUMP_MASK_PMU BCM_BIT(5) 432 433 typedef struct { 434 uint16 reg_offset; 435 uint16 core_mask; 436 } reg_dump_config_t; 437 438 #define HND_EXT_TRAP_PHY_INFO_VER 2 439 typedef struct hnd_ext_trap_phydbg_v2 { 440 uint8 version; 441 uint8 len; 442 uint16 err; 443 uint16 RxFeStatus; 444 uint16 TxFIFOStatus0; 445 uint16 TxFIFOStatus1; 446 uint16 RfseqMode; 447 uint16 RfseqStatus0; 448 uint16 RfseqStatus1; 449 uint16 RfseqStatus_Ocl; 450 uint16 RfseqStatus_Ocl1; 451 uint16 OCLControl1; 452 uint16 TxError; 453 uint16 bphyTxError; 454 uint16 TxCCKError; 455 uint16 TxCtrlWrd0; 456 uint16 TxCtrlWrd1; 457 uint16 TxCtrlWrd2; 458 uint16 TxLsig0; 459 uint16 TxLsig1; 460 uint16 TxVhtSigA10; 461 uint16 TxVhtSigA11; 462 uint16 TxVhtSigA20; 463 uint16 TxVhtSigA21; 464 uint16 txPktLength; 465 uint16 txPsdulengthCtr; 466 uint16 gpioClkControl; 467 uint16 gpioSel; 468 uint16 pktprocdebug; 469 uint32 gpioOut[3]; 470 uint32 additional_regs[1]; 471 } hnd_ext_trap_phydbg_v2_t; 472 473 #define HND_EXT_TRAP_PHY_INFO_VER_3 (3) 474 typedef struct hnd_ext_trap_phydbg_v3 { 475 uint8 version; 476 uint8 len; 477 uint16 err; 478 uint16 RxFeStatus; 479 uint16 TxFIFOStatus0; 480 uint16 TxFIFOStatus1; 481 uint16 RfseqMode; 482 uint16 RfseqStatus0; 483 uint16 RfseqStatus1; 484 uint16 RfseqStatus_Ocl; 485 uint16 RfseqStatus_Ocl1; 486 uint16 OCLControl1; 487 uint16 TxError; 488 uint16 bphyTxError; 489 uint16 TxCCKError; 490 uint16 TxCtrlWrd0; 491 uint16 TxCtrlWrd1; 492 uint16 TxCtrlWrd2; 493 uint16 TxLsig0; 494 uint16 TxLsig1; 495 uint16 TxVhtSigA10; 496 uint16 TxVhtSigA11; 497 uint16 TxVhtSigA20; 498 uint16 TxVhtSigA21; 499 uint16 txPktLength; 500 uint16 txPsdulengthCtr; 501 uint16 gpioClkControl; 502 uint16 gpioSel; 503 uint16 pktprocdebug; 504 uint32 gpioOut[3]; 505 uint16 HESigURateFlagStatus; 506 uint16 HESigUsRateFlagStatus; 507 uint32 additional_regs[1]; 508 } hnd_ext_trap_phydbg_v3_t; 509 510 /* Phy TxErr Dump Structure */ 511 #define HND_EXT_TRAP_PHYTXERR_INFO_VER 1 512 #define HND_EXT_TRAP_PHYTXERR_INFO_VER_V2 2 513 typedef struct hnd_ext_trap_macphytxerr { 514 uint8 version; /* version of the information following this */ 515 uint8 trap_reason; 516 uint16 i16_0x63E; /* tsf_tmr_rx_ts */ 517 uint16 i16_0x640; /* tsf_tmr_tx_ts */ 518 uint16 i16_0x642; /* tsf_tmr_rx_end_ts */ 519 uint16 i16_0x846; /* TDC_FrmLen0 */ 520 uint16 i16_0x848; /* TDC_FrmLen1 */ 521 uint16 i16_0x84a; /* TDC_Txtime */ 522 uint16 i16_0xa5a; /* TXE_BytCntInTxFrmLo */ 523 uint16 i16_0xa5c; /* TXE_BytCntInTxFrmHi */ 524 uint16 i16_0x856; /* TDC_VhtPsduLen0 */ 525 uint16 i16_0x858; /* TDC_VhtPsduLen1 */ 526 uint16 i16_0x490; /* psm_brc */ 527 uint16 i16_0x4d8; /* psm_brc_1 */ 528 uint16 shm_txerr_reason; 529 uint16 shm_pctl0; 530 uint16 shm_pctl1; 531 uint16 shm_pctl2; 532 uint16 shm_lsig0; 533 uint16 shm_lsig1; 534 uint16 shm_plcp0; 535 uint16 shm_plcp1; 536 uint16 shm_plcp2; 537 uint16 shm_vht_sigb0; 538 uint16 shm_vht_sigb1; 539 uint16 shm_tx_tst; 540 uint16 shm_txerr_tm; 541 uint16 shm_curchannel; 542 uint16 shm_crx_rxtsf_pos; 543 uint16 shm_lasttx_tsf; 544 uint16 shm_s_rxtsftmrval; 545 uint16 i16_0x29; /* Phy indirect address */ 546 uint16 i16_0x2a; /* Phy indirect address */ 547 } hnd_ext_trap_macphytxerr_t; 548 549 typedef struct hnd_ext_trap_macphytxerr_v2 { 550 uint8 version; /* version of the information following this */ 551 uint8 trap_reason; 552 uint16 i16_0x63E; /* tsf_tmr_rx_ts */ 553 uint16 i16_0x640; /* tsf_tmr_tx_ts */ 554 uint16 i16_0x642; /* tsf_tmr_rx_end_ts */ 555 uint16 i16_0x846; /* TDC_FrmLen0 */ 556 uint16 i16_0x848; /* TDC_FrmLen1 */ 557 uint16 i16_0x84a; /* TDC_Txtime */ 558 uint16 i16_0xa5a; /* TXE_BytCntInTxFrmLo */ 559 uint16 i16_0xa5c; /* TXE_BytCntInTxFrmHi */ 560 uint16 i16_0x856; /* TDC_VhtPsduLen0 */ 561 uint16 i16_0x858; /* TDC_VhtPsduLen1 */ 562 uint16 i16_0x490; /* psm_brc */ 563 uint16 i16_0x4d8; /* psm_brc_1 */ 564 uint16 shm_txerr_reason; 565 uint16 shm_pctl0; 566 uint16 shm_pctl1; 567 uint16 shm_pctl2; 568 uint16 shm_lsig0; 569 uint16 shm_lsig1; 570 uint16 shm_plcp0; 571 uint16 shm_plcp1; 572 uint16 shm_plcp2; 573 uint16 shm_vht_sigb0; 574 uint16 shm_vht_sigb1; 575 uint16 shm_tx_tst; 576 uint16 shm_txerr_tm; 577 uint16 shm_curchannel; 578 uint16 shm_crx_rxtsf_pos; 579 uint16 shm_lasttx_tsf; 580 uint16 shm_s_rxtsftmrval; 581 uint16 i16_0x29; /* Phy indirect address */ 582 uint16 i16_0x2a; /* Phy indirect address */ 583 uint8 phyerr_bmac_cnt; /* number of times bmac raised phy tx err */ 584 uint8 phyerr_bmac_rsn; /* bmac reason for phy tx error */ 585 uint16 pad; 586 uint32 recv_fifo_status[3] 587 [2]; /* Rcv Status0 & Rcv Status1 for 3 Rx fifos */ 588 } hnd_ext_trap_macphytxerr_v2_t; 589 590 #define HND_EXT_TRAP_PCIE_ERR_ATTN_VER_1 (1u) 591 #define MAX_AER_HDR_LOG_REGS (4u) 592 typedef struct hnd_ext_trap_pcie_err_attn_v1 { 593 uint8 version; 594 uint8 pad[3]; 595 uint32 err_hdr_logreg1; 596 uint32 err_hdr_logreg2; 597 uint32 err_hdr_logreg3; 598 uint32 err_hdr_logreg4; 599 uint32 err_code_logreg; 600 uint32 err_type; 601 uint32 err_code_state; 602 uint32 last_err_attn_ts; 603 uint32 cfg_tlp_hdr[MAX_AER_HDR_LOG_REGS]; 604 } hnd_ext_trap_pcie_err_attn_v1_t; 605 606 #define MAX_EVENTLOG_BUFFERS 48 607 typedef struct eventlog_trapdata_info { 608 uint32 num_elements; 609 uint32 seq_num; 610 uint32 log_arr_addr; 611 } eventlog_trapdata_info_t; 612 613 typedef struct eventlog_trap_buf_info { 614 uint32 len; 615 uint32 buf_addr; 616 } eventlog_trap_buf_info_t; 617 618 #if defined(ETD) && !defined(WLETD) 619 #define ETD_SW_FLAG_MEM 0x00000001 620 621 int etd_init(osl_t *osh); 622 int etd_register_trap_ext_callback(void *cb, void *arg); 623 int(etd_register_trap_ext_callback_late)(void *cb, void *arg); 624 uint32 *etd_get_trap_ext_data(void); 625 uint32 etd_get_trap_ext_swflags(void); 626 void etd_set_trap_ext_swflag(uint32 flag); 627 void etd_notify_trap_ext_callback(trap_t *tr); 628 reg_dump_config_t *etd_get_reg_dump_config_tbl(void); 629 uint etd_get_reg_dump_config_len(void); 630 631 extern bool _etd_enab; 632 633 #define ETD_ENAB(pub) (_etd_enab) 634 635 #else 636 #define ETD_ENAB(pub) (0) 637 #endif /* WLETD */ 638 639 #endif /* !LANGUAGE_ASSEMBLY */ 640 641 #endif /* _ETD_H_ */ 642