1 /*
2 * Misc utility routines for accessing the SOC Interconnects
3 * of Broadcom HNBU chips.
4 *
5 * Copyright (C) 1999-2019, Broadcom.
6 *
7 * Unless you and Broadcom execute a separate written software license
8 * agreement governing use of this software, this software is licensed to you
9 * under the terms of the GNU General Public License version 2 (the "GPL"),
10 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
11 * following added to such license:
12 *
13 * As a special exception, the copyright holders of this software give you
14 * permission to link this software with independent modules, and to copy and
15 * distribute the resulting executable under terms of your choice, provided that
16 * you also meet, for each linked independent module, the terms and conditions
17 * of the license of that module. An independent module is a module which is
18 * not derived from this software. The special exception does not apply to any
19 * modifications of the software.
20 *
21 * Notwithstanding the above, under no circumstances may you combine this
22 * software in any way with any other Broadcom software provided under a license
23 * other than the GPL, without Broadcom's express prior written consent.
24 *
25 *
26 * <<Broadcom-WL-IPTag/Open:>>
27 *
28 * $Id: siutils.h 798061 2019-01-04 23:27:15Z $
29 */
30
31 #ifndef _siutils_h_
32 #define _siutils_h_
33
34 #ifdef SR_DEBUG
35 #include "wlioctl.h"
36 #endif /* SR_DEBUG */
37
38 #define WARM_BOOT 0xA0B0C0D0
39
40 #ifdef BCM_BACKPLANE_TIMEOUT
41
42 #define SI_MAX_ERRLOG_SIZE 4
43 typedef struct si_axi_error {
44 uint32 error;
45 uint32 coreid;
46 uint32 errlog_lo;
47 uint32 errlog_hi;
48 uint32 errlog_id;
49 uint32 errlog_flags;
50 uint32 errlog_status;
51 } si_axi_error_t;
52
53 typedef struct si_axi_error_info {
54 uint32 count;
55 si_axi_error_t axi_error[SI_MAX_ERRLOG_SIZE];
56 } si_axi_error_info_t;
57 #endif /* BCM_BACKPLANE_TIMEOUT */
58
59 /**
60 * Data structure to export all chip specific common variables
61 * public (read-only) portion of siutils handle returned by
62 * si_attach()/si_kattach()
63 */
64 struct si_pub {
65 uint socitype; /**< SOCI_SB, SOCI_AI */
66
67 uint bustype; /**< SI_BUS, PCI_BUS */
68 uint buscoretype; /**< PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
69 uint buscorerev; /**< buscore rev */
70 uint buscoreidx; /**< buscore index */
71 int ccrev; /**< chip common core rev */
72 uint32 cccaps; /**< chip common capabilities */
73 uint32 cccaps_ext; /**< chip common capabilities extension */
74 int pmurev; /**< pmu core rev */
75 uint32 pmucaps; /**< pmu capabilities */
76 uint boardtype; /**< board type */
77 uint boardrev; /* board rev */
78 uint boardvendor; /**< board vendor */
79 uint boardflags; /**< board flags */
80 uint boardflags2; /**< board flags2 */
81 uint boardflags4; /**< board flags4 */
82 uint chip; /**< chip number */
83 uint chiprev; /**< chip revision */
84 uint chippkg; /**< chip package option */
85 uint32 chipst; /**< chip status */
86 bool issim; /**< chip is in simulation or emulation */
87 uint socirev; /**< SOC interconnect rev */
88 bool pci_pr32414;
89 int gcirev; /**< gci core rev */
90 int lpflags; /**< low power flags */
91 uint32
92 enum_base; /**< backplane address where the chipcommon core resides */
93
94 #ifdef BCM_BACKPLANE_TIMEOUT
95 si_axi_error_info_t *err_info;
96 #endif /* BCM_BACKPLANE_TIMEOUT */
97
98 bool _multibp_enable;
99 };
100
101 /* for HIGH_ONLY driver, the si_t must be writable to allow states sync from
102 * BMAC to HIGH driver for monolithic driver, it is readonly to prevent accident
103 * change
104 */
105 typedef struct si_pub si_t;
106
107 /*
108 * Many of the routines below take an 'sih' handle as their first arg.
109 * Allocate this by calling si_attach(). Free it by calling si_detach().
110 * At any one time, the sih is logically focused on one particular si core
111 * (the "current core").
112 * Use si_setcore() or si_setcoreidx() to change the association to another
113 * core.
114 */
115 #define SI_OSH NULL /**< Use for si_kattach when no osh is available */
116
117 #define BADIDX (SI_MAXCORES + 1)
118
119 /* clkctl xtal what flags */
120 #define XTAL 0x1 /**< primary crystal oscillator (2050) */
121 #define PLL 0x2 /**< main chip pll */
122
123 /* clkctl clk mode */
124 #define CLK_FAST 0 /**< force fast (pll) clock */
125 #define CLK_DYNAMIC 2 /**< enable dynamic clock control */
126
127 /* GPIO usage priorities */
128 #define GPIO_DRV_PRIORITY 0 /**< Driver */
129 #define GPIO_APP_PRIORITY 1 /**< Application */
130 #define GPIO_HI_PRIORITY 2 /**< Highest priority. Ignore GPIO reservation */
131
132 /* GPIO pull up/down */
133 #define GPIO_PULLUP 0
134 #define GPIO_PULLDN 1
135
136 /* GPIO event regtype */
137 #define GPIO_REGEVT 0 /**< GPIO register event */
138 #define GPIO_REGEVT_INTMSK 1 /**< GPIO register event int mask */
139 #define GPIO_REGEVT_INTPOL 2 /**< GPIO register event int polarity */
140
141 /* device path */
142 #define SI_DEVPATH_BUFSZ 16 /**< min buffer size in bytes */
143
144 /* SI routine enumeration: to be used by update function with multiple hooks */
145 #define SI_DOATTACH 1
146 #define SI_PCIDOWN 2 /**< wireless interface is down */
147 #define SI_PCIUP 3 /**< wireless interface is up */
148
149 #ifdef SR_DEBUG
150 #define PMU_RES 31
151 #endif /* SR_DEBUG */
152
153 /* "access" param defines for si_seci_access() below */
154 #define SECI_ACCESS_STATUSMASK_SET 0
155 #define SECI_ACCESS_INTRS 1
156 #define SECI_ACCESS_UART_CTS 2
157 #define SECI_ACCESS_UART_RTS 3
158 #define SECI_ACCESS_UART_RXEMPTY 4
159 #define SECI_ACCESS_UART_GETC 5
160 #define SECI_ACCESS_UART_TXFULL 6
161 #define SECI_ACCESS_UART_PUTC 7
162 #define SECI_ACCESS_STATUSMASK_GET 8
163
164 #define ISSIM_ENAB(sih) FALSE
165
166 #define INVALID_ADDR (~0)
167
168 /* PMU clock/power control */
169 #if defined(BCMPMUCTL)
170 #define PMUCTL_ENAB(sih) (BCMPMUCTL)
171 #else
172 #define PMUCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PMU)
173 #endif // endif
174
175 #if defined(BCMAOBENAB)
176 #define AOB_ENAB(sih) (BCMAOBENAB)
177 #else
178 #define AOB_ENAB(sih) \
179 ((sih)->ccrev >= 35 ? ((sih)->cccaps_ext & CC_CAP_EXT_AOB_PRESENT) : 0)
180 #endif /* BCMAOBENAB */
181
182 /* chipcommon clock/power control (exclusive with PMU's) */
183 #if defined(BCMPMUCTL) && BCMPMUCTL
184 #define CCCTL_ENAB(sih) (0)
185 #define CCPLL_ENAB(sih) (0)
186 #else
187 #define CCCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PWR_CTL)
188 #define CCPLL_ENAB(sih) ((sih)->cccaps & CC_CAP_PLL_MASK)
189 #endif // endif
190
191 typedef void (*gci_gpio_handler_t)(uint32 stat, void *arg);
192
193 /* External BT Coex enable mask */
194 #define CC_BTCOEX_EN_MASK 0x01
195 /* External PA enable mask */
196 #define GPIO_CTRL_EPA_EN_MASK 0x40
197 /* WL/BT control enable mask */
198 #define GPIO_CTRL_5_6_EN_MASK 0x60
199 #define GPIO_CTRL_7_6_EN_MASK 0xC0
200 #define GPIO_OUT_7_EN_MASK 0x80
201
202 /* CR4 specific defines used by the host driver */
203 #define SI_CR4_CAP (0x04)
204 #define SI_CR4_BANKIDX (0x40)
205 #define SI_CR4_BANKINFO (0x44)
206 #define SI_CR4_BANKPDA (0x4C)
207
208 #define ARMCR4_TCBBNB_MASK 0xf0
209 #define ARMCR4_TCBBNB_SHIFT 4
210 #define ARMCR4_TCBANB_MASK 0xf
211 #define ARMCR4_TCBANB_SHIFT 0
212
213 #define SICF_CPUHALT (0x0020)
214 #define ARMCR4_BSZ_MASK 0x7f
215 #define ARMCR4_BUNITSZ_MASK 0x200
216 #define ARMCR4_BSZ_8K 8192
217 #define ARMCR4_BSZ_1K 1024
218 #define SI_BPIND_1BYTE 0x1
219 #define SI_BPIND_2BYTE 0x3
220 #define SI_BPIND_4BYTE 0xF
221
222 #define GET_GCI_OFFSET(sih, gci_reg) \
223 (AOB_ENAB(sih) ? OFFSETOF(gciregs_t, gci_reg) \
224 : OFFSETOF(chipcregs_t, gci_reg))
225
226 #define GET_GCI_CORE(sih) \
227 (AOB_ENAB(sih) ? si_findcoreidx(sih, GCI_CORE_ID, 0) : SI_CC_IDX)
228
229 #include <osl_decl.h>
230 /* === exported functions === */
231 extern si_t *si_attach(uint pcidev, osl_t *osh, volatile void *regs,
232 uint bustype, void *sdh, char **vars, uint *varsz);
233 extern si_t *si_kattach(osl_t *osh);
234 extern void si_detach(si_t *sih);
235 extern volatile void *si_d11_switch_addrbase(si_t *sih, uint coreunit);
236 extern uint si_corelist(si_t *sih, uint coreid[]);
237 extern uint si_coreid(si_t *sih);
238 extern uint si_flag(si_t *sih);
239 extern uint si_flag_alt(si_t *sih);
240 extern uint si_intflag(si_t *sih);
241 extern uint si_coreidx(si_t *sih);
242 extern uint si_coreunit(si_t *sih);
243 extern uint si_corevendor(si_t *sih);
244 extern uint si_corerev(si_t *sih);
245 extern uint si_corerev_minor(si_t *sih);
246 extern void *si_osh(si_t *sih);
247 extern void si_setosh(si_t *sih, osl_t *osh);
248 extern int si_backplane_access(si_t *sih, uint addr, uint size, uint *val,
249 bool read);
250 extern uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask,
251 uint val);
252 extern uint si_corereg_writeonly(si_t *sih, uint coreidx, uint regoff,
253 uint mask, uint val);
254 extern uint si_pmu_corereg(si_t *sih, uint32 idx, uint regoff, uint mask,
255 uint val);
256 extern volatile uint32 *si_corereg_addr(si_t *sih, uint coreidx, uint regoff);
257 extern volatile void *si_coreregs(si_t *sih);
258 extern uint si_wrapperreg(si_t *sih, uint32 offset, uint32 mask, uint32 val);
259 extern uint si_core_wrapperreg(si_t *sih, uint32 coreidx, uint32 offset,
260 uint32 mask, uint32 val);
261 extern void *si_wrapperregs(si_t *sih);
262 extern uint32 si_core_cflags(si_t *sih, uint32 mask, uint32 val);
263 extern void si_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
264 extern uint32 si_core_sflags(si_t *sih, uint32 mask, uint32 val);
265 extern void si_commit(si_t *sih);
266 extern bool si_iscoreup(si_t *sih);
267 extern uint si_numcoreunits(si_t *sih, uint coreid);
268 extern uint si_numd11coreunits(si_t *sih);
269 extern uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit);
270 extern volatile void *si_setcoreidx(si_t *sih, uint coreidx);
271 extern volatile void *si_setcore(si_t *sih, uint coreid, uint coreunit);
272 extern uint32 si_oobr_baseaddr(si_t *sih, bool second);
273 extern volatile void *si_switch_core(si_t *sih, uint coreid, uint *origidx,
274 uint *intr_val);
275 extern void si_restore_core(si_t *sih, uint coreid, uint intr_val);
276 extern int si_numaddrspaces(si_t *sih);
277 extern uint32 si_addrspace(si_t *sih, uint spidx, uint baidx);
278 extern uint32 si_addrspacesize(si_t *sih, uint spidx, uint baidx);
279 extern void si_coreaddrspaceX(si_t *sih, uint asidx, uint32 *addr,
280 uint32 *size);
281 extern int si_corebist(si_t *sih);
282 extern void si_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
283 extern void si_core_disable(si_t *sih, uint32 bits);
284 extern uint32 si_clock_rate(uint32 pll_type, uint32 n, uint32 m);
285 extern uint si_chip_hostif(si_t *sih);
286 extern uint32 si_clock(si_t *sih);
287 extern uint32 si_alp_clock(si_t *sih); /* returns [Hz] units */
288 extern uint32 si_ilp_clock(si_t *sih); /* returns [Hz] units */
289 extern void si_pci_setup(si_t *sih, uint coremask);
290 extern void si_pcmcia_init(si_t *sih);
291 extern void si_setint(si_t *sih, int siflag);
292 extern bool si_backplane64(si_t *sih);
293 extern void si_register_intr_callback(si_t *sih, void *intrsoff_fn,
294 void *intrsrestore_fn,
295 void *intrsenabled_fn, void *intr_arg);
296 extern void si_deregister_intr_callback(si_t *sih);
297 extern void si_clkctl_init(si_t *sih);
298 extern uint16 si_clkctl_fast_pwrup_delay(si_t *sih);
299 extern bool si_clkctl_cc(si_t *sih, uint mode);
300 extern int si_clkctl_xtal(si_t *sih, uint what, bool on);
301 extern uint32 si_gpiotimerval(si_t *sih, uint32 mask, uint32 val);
302 extern void si_btcgpiowar(si_t *sih);
303 extern bool si_deviceremoved(si_t *sih);
304 extern void si_set_device_removed(si_t *sih, bool status);
305 extern uint32 si_sysmem_size(si_t *sih);
306 extern uint32 si_socram_size(si_t *sih);
307 extern uint32 si_socdevram_size(si_t *sih);
308 extern uint32 si_socram_srmem_size(si_t *sih);
309 extern void si_socram_set_bankpda(si_t *sih, uint32 bankidx, uint32 bankpda);
310 extern void si_socdevram(si_t *sih, bool set, uint8 *ennable, uint8 *protect,
311 uint8 *remap);
312 extern bool si_socdevram_pkg(si_t *sih);
313 extern bool si_socdevram_remap_isenb(si_t *sih);
314 extern uint32 si_socdevram_remap_size(si_t *sih);
315
316 extern void si_watchdog(si_t *sih, uint ticks);
317 extern void si_watchdog_ms(si_t *sih, uint32 ms);
318 extern uint32 si_watchdog_msticks(void);
319 extern volatile void *si_gpiosetcore(si_t *sih);
320 extern uint32 si_gpiocontrol(si_t *sih, uint32 mask, uint32 val,
321 uint8 priority);
322 extern uint32 si_gpioouten(si_t *sih, uint32 mask, uint32 val, uint8 priority);
323 extern uint32 si_gpioout(si_t *sih, uint32 mask, uint32 val, uint8 priority);
324 extern uint32 si_gpioin(si_t *sih);
325 extern uint32 si_gpiointpolarity(si_t *sih, uint32 mask, uint32 val,
326 uint8 priority);
327 extern uint32 si_gpiointmask(si_t *sih, uint32 mask, uint32 val,
328 uint8 priority);
329 extern uint32 si_gpioeventintmask(si_t *sih, uint32 mask, uint32 val,
330 uint8 priority);
331 extern uint32 si_gpioled(si_t *sih, uint32 mask, uint32 val);
332 extern uint32 si_gpioreserve(si_t *sih, uint32 gpio_num, uint8 priority);
333 extern uint32 si_gpiorelease(si_t *sih, uint32 gpio_num, uint8 priority);
334 extern uint32 si_gpiopull(si_t *sih, bool updown, uint32 mask, uint32 val);
335 extern uint32 si_gpioevent(si_t *sih, uint regtype, uint32 mask, uint32 val);
336 extern uint32 si_gpio_int_enable(si_t *sih, bool enable);
337 extern void si_gci_uart_init(si_t *sih, osl_t *osh, uint8 seci_mode);
338 extern void si_gci_enable_gpio(si_t *sih, uint8 gpio, uint32 mask,
339 uint32 value);
340 extern uint8 si_gci_host_wake_gpio_init(si_t *sih);
341 extern uint8 si_gci_time_sync_gpio_init(si_t *sih);
342 extern void si_gci_host_wake_gpio_enable(si_t *sih, uint8 gpio, bool state);
343 extern void si_gci_time_sync_gpio_enable(si_t *sih, uint8 gpio, bool state);
344
345 extern void si_invalidate_second_bar0win(si_t *sih);
346
347 extern void si_gci_shif_config_wake_pin(si_t *sih, uint8 gpio_n,
348 uint8 wake_events, bool gci_gpio);
349 extern void si_shif_int_enable(si_t *sih, uint8 gpio_n, uint8 wake_events,
350 bool enable);
351
352 /* GCI interrupt handlers */
353 extern void si_gci_handler_process(si_t *sih);
354
355 extern void si_enable_gpio_wake(si_t *sih, uint8 *wake_mask, uint8 *cur_status,
356 uint8 gci_gpio, uint32 pmu_cc2_mask,
357 uint32 pmu_cc2_value);
358
359 /* GCI GPIO event handlers */
360 extern void *si_gci_gpioint_handler_register(si_t *sih, uint8 gpio, uint8 sts,
361 gci_gpio_handler_t cb, void *arg);
362 extern void si_gci_gpioint_handler_unregister(si_t *sih, void *gci_i);
363
364 extern uint8 si_gci_gpio_status(si_t *sih, uint8 gci_gpio, uint8 mask,
365 uint8 value);
366 extern void si_gci_config_wake_pin(si_t *sih, uint8 gpio_n, uint8 wake_events,
367 bool gci_gpio);
368 extern void si_gci_free_wake_pin(si_t *sih, uint8 gpio_n);
369
370 /* Wake-on-wireless-LAN (WOWL) */
371 extern bool si_pci_pmecap(si_t *sih);
372 extern bool si_pci_fastpmecap(struct osl_info *osh);
373 extern bool si_pci_pmestat(si_t *sih);
374 extern void si_pci_pmeclr(si_t *sih);
375 extern void si_pci_pmeen(si_t *sih);
376 extern void si_pci_pmestatclr(si_t *sih);
377 extern uint si_pcie_readreg(void *sih, uint addrtype, uint offset);
378 extern uint si_pcie_writereg(void *sih, uint addrtype, uint offset, uint val);
379 extern void si_deepsleep_count(si_t *sih, bool arm_wakeup);
380
381 #ifdef BCMSDIO
382 extern void si_sdio_init(si_t *sih);
383 #endif // endif
384
385 extern uint16 si_d11_devid(si_t *sih);
386 extern int si_corepciid(si_t *sih, uint func, uint16 *pcivendor,
387 uint16 *pcidevice, uint8 *pciclass, uint8 *pcisubclass,
388 uint8 *pciprogif, uint8 *pciheader);
389
390 extern uint32 si_seci_access(si_t *sih, uint32 val, int access);
391 extern volatile void *si_seci_init(si_t *sih, uint8 seci_mode);
392 extern void si_seci_clk_force(si_t *sih, bool val);
393 extern bool si_seci_clk_force_status(si_t *sih);
394
395 #define si_eci(sih) 0
si_eci_init(si_t * sih)396 static INLINE void *si_eci_init(si_t *sih)
397 {
398 return NULL;
399 }
400 #define si_eci_notify_bt(sih, type, val) (0)
401 #define si_seci(sih) 0
402 #define si_seci_upd(sih, a) \
403 do { \
404 } while (0)
si_gci_init(si_t * sih)405 static INLINE void *si_gci_init(si_t *sih)
406 {
407 return NULL;
408 }
409 #define si_seci_down(sih) \
410 do { \
411 } while (0)
412 #define si_gci(sih) 0
413
414 /* OTP status */
415 extern bool si_is_otp_disabled(si_t *sih);
416 extern bool si_is_otp_powered(si_t *sih);
417 extern void si_otp_power(si_t *sih, bool on, uint32 *min_res_mask);
418
419 /* SPROM availability */
420 extern bool si_is_sprom_available(si_t *sih);
421
422 /* OTP/SROM CIS stuff */
423 extern int si_cis_source(si_t *sih);
424 #define CIS_DEFAULT 0
425 #define CIS_SROM 1
426 #define CIS_OTP 2
427
428 /* Fab-id information */
429 #define DEFAULT_FAB 0x0 /**< Original/first fab used for this chip */
430 #define CSM_FAB7 0x1 /**< CSM Fab7 chip */
431 #define TSMC_FAB12 0x2 /**< TSMC Fab12/Fab14 chip */
432 #define SMIC_FAB4 0x3 /**< SMIC Fab4 chip */
433
434 extern uint16 si_fabid(si_t *sih);
435 extern uint16 si_chipid(si_t *sih);
436
437 /*
438 * Build device path. Path size must be >= SI_DEVPATH_BUFSZ.
439 * The returned path is NULL terminated and has trailing '/'.
440 * Return 0 on success, nonzero otherwise.
441 */
442 extern int si_devpath(si_t *sih, char *path, int size);
443 extern int si_devpath_pcie(si_t *sih, char *path, int size);
444 /* Read variable with prepending the devpath to the name */
445 extern char *si_getdevpathvar(si_t *sih, const char *name);
446 extern int si_getdevpathintvar(si_t *sih, const char *name);
447 extern char *si_coded_devpathvar(si_t *sih, char *varname, int var_len,
448 const char *name);
449
450 extern uint8 si_pcieclkreq(si_t *sih, uint32 mask, uint32 val);
451 extern uint32 si_pcielcreg(si_t *sih, uint32 mask, uint32 val);
452 extern uint8 si_pcieltrenable(si_t *sih, uint32 mask, uint32 val);
453 extern uint8 si_pcieobffenable(si_t *sih, uint32 mask, uint32 val);
454 extern uint32 si_pcieltr_reg(si_t *sih, uint32 reg, uint32 mask, uint32 val);
455 extern uint32 si_pcieltrspacing_reg(si_t *sih, uint32 mask, uint32 val);
456 extern uint32 si_pcieltrhysteresiscnt_reg(si_t *sih, uint32 mask, uint32 val);
457 extern void si_pcie_set_error_injection(si_t *sih, uint32 mode);
458 extern void si_pcie_set_L1substate(si_t *sih, uint32 substate);
459 extern uint32 si_pcie_get_L1substate(si_t *sih);
460 extern void si_war42780_clkreq(si_t *sih, bool clkreq);
461 extern void si_pci_down(si_t *sih);
462 extern void si_pci_up(si_t *sih);
463 extern void si_pci_sleep(si_t *sih);
464 extern void si_pcie_war_ovr_update(si_t *sih, uint8 aspm);
465 extern void si_pcie_power_save_enable(si_t *sih, bool enable);
466 extern void si_pcie_extendL1timer(si_t *sih, bool extend);
467 extern int si_pci_fixcfg(si_t *sih);
468 extern void si_chippkg_set(si_t *sih, uint);
469 extern bool si_is_warmboot(void);
470
471 extern void si_chipcontrl_restore(si_t *sih, uint32 val);
472 extern uint32 si_chipcontrl_read(si_t *sih);
473 extern void si_chipcontrl_srom4360(si_t *sih, bool on);
474 extern void si_srom_clk_set(si_t *sih); /**< for chips with fast BP clock */
475 extern void si_btc_enable_chipcontrol(si_t *sih);
476 extern void si_pmu_avb_clk_set(si_t *sih, osl_t *osh, bool set_flag);
477 /* === debug routines === */
478
479 extern bool si_taclear(si_t *sih, bool details);
480
481 #if defined(BCMDBG_PHYDUMP)
482 struct bcmstrbuf;
483 extern int si_dump_pcieinfo(si_t *sih, struct bcmstrbuf *b);
484 extern void si_dump_pmuregs(si_t *sih, struct bcmstrbuf *b);
485 extern int si_dump_pcieregs(si_t *sih, struct bcmstrbuf *b);
486 #endif // endif
487
488 #if defined(BCMDBG_PHYDUMP)
489 extern void si_dumpregs(si_t *sih, struct bcmstrbuf *b);
490 #endif // endif
491
492 extern uint32 si_ccreg(si_t *sih, uint32 offset, uint32 mask, uint32 val);
493 extern uint32 si_pciereg(si_t *sih, uint32 offset, uint32 mask, uint32 val,
494 uint type);
495 extern int si_bpind_access(si_t *sih, uint32 addr_high, uint32 addr_low,
496 int32 *data, bool read);
497 #ifdef SR_DEBUG
498 extern void si_dump_pmu(si_t *sih, void *pmu_var);
499 extern void si_pmu_keep_on(si_t *sih, int32 int_val);
500 extern uint32 si_pmu_keep_on_get(si_t *sih);
501 extern uint32 si_power_island_set(si_t *sih, uint32 int_val);
502 extern uint32 si_power_island_get(si_t *sih);
503 #endif /* SR_DEBUG */
504 extern uint32 si_pcieserdesreg(si_t *sih, uint32 mdioslave, uint32 offset,
505 uint32 mask, uint32 val);
506 extern void si_pcie_set_request_size(si_t *sih, uint16 size);
507 extern uint16 si_pcie_get_request_size(si_t *sih);
508 extern void si_pcie_set_maxpayload_size(si_t *sih, uint16 size);
509 extern uint16 si_pcie_get_maxpayload_size(si_t *sih);
510 extern uint16 si_pcie_get_ssid(si_t *sih);
511 extern uint32 si_pcie_get_bar0(si_t *sih);
512 extern int si_pcie_configspace_cache(si_t *sih);
513 extern int si_pcie_configspace_restore(si_t *sih);
514 extern int si_pcie_configspace_get(si_t *sih, uint8 *buf, uint size);
515
516 #ifdef BCM_BACKPLANE_TIMEOUT
517 extern const si_axi_error_info_t *si_get_axi_errlog_info(si_t *sih);
518 extern void si_reset_axi_errlog_info(si_t *sih);
519 #endif /* BCM_BACKPLANE_TIMEOUT */
520
521 extern void si_update_backplane_timeouts(si_t *sih, bool enable, uint32 timeout,
522 uint32 cid);
523
524 extern uint32 si_tcm_size(si_t *sih);
525 extern bool si_has_flops(si_t *sih);
526
527 extern int si_set_sromctl(si_t *sih, uint32 value);
528 extern uint32 si_get_sromctl(si_t *sih);
529
530 extern uint32 si_gci_direct(si_t *sih, uint offset, uint32 mask, uint32 val);
531 extern uint32 si_gci_indirect(si_t *sih, uint regidx, uint offset, uint32 mask,
532 uint32 val);
533 extern uint32 si_gci_output(si_t *sih, uint reg, uint32 mask, uint32 val);
534 extern uint32 si_gci_input(si_t *sih, uint reg);
535 extern uint32 si_gci_int_enable(si_t *sih, bool enable);
536 extern void si_gci_reset(si_t *sih);
537 #ifdef BCMLTECOEX
538 extern void si_ercx_init(si_t *sih, uint32 ltecx_mux, uint32 ltecx_padnum,
539 uint32 ltecx_fnsel, uint32 ltecx_gcigpio);
540 #endif /* BCMLTECOEX */
541 extern void si_gci_seci_init(si_t *sih);
542 extern void si_wci2_init(si_t *sih, uint8 baudrate, uint32 ltecx_mux,
543 uint32 ltecx_padnum, uint32 ltecx_fnsel,
544 uint32 ltecx_gcigpio, uint32 xtalfreq);
545
546 extern bool si_btcx_wci2_init(si_t *sih);
547
548 extern void si_gci_set_functionsel(si_t *sih, uint32 pin, uint8 fnsel);
549 extern uint32 si_gci_get_functionsel(si_t *sih, uint32 pin);
550 extern void si_gci_clear_functionsel(si_t *sih, uint8 fnsel);
551 extern uint8 si_gci_get_chipctrlreg_idx(uint32 pin, uint32 *regidx,
552 uint32 *pos);
553 extern uint32 si_gci_chipcontrol(si_t *sih, uint reg, uint32 mask, uint32 val);
554 extern uint32 si_gci_chipstatus(si_t *sih, uint reg);
555 extern uint8 si_enable_device_wake(si_t *sih, uint8 *wake_status,
556 uint8 *cur_status);
557 extern uint8 si_get_device_wake_opt(si_t *sih);
558 extern void si_swdenable(si_t *sih, uint32 swdflag);
559 extern uint8 si_enable_perst_wake(si_t *sih, uint8 *perst_wake_mask,
560 uint8 *perst_cur_status);
561
562 extern uint32 si_get_pmu_reg_addr(si_t *sih, uint32 offset);
563 #define CHIPCTRLREG1 0x1
564 #define CHIPCTRLREG2 0x2
565 #define CHIPCTRLREG3 0x3
566 #define CHIPCTRLREG4 0x4
567 #define CHIPCTRLREG5 0x5
568 #define MINRESMASKREG 0x618
569 #define MAXRESMASKREG 0x61c
570 #define CHIPCTRLADDR 0x650
571 #define CHIPCTRLDATA 0x654
572 #define RSRCTABLEADDR 0x620
573 #define RSRCUPDWNTIME 0x628
574 #define PMUREG_RESREQ_MASK 0x68c
575
576 void si_update_masks(si_t *sih);
577 void si_force_islanding(si_t *sih, bool enable);
578 extern uint32 si_pmu_res_req_timer_clr(si_t *sih);
579 extern void si_pmu_rfldo(si_t *sih, bool on);
580 extern uint32 si_pcie_set_ctrlreg(si_t *sih, uint32 sperst_mask,
581 uint32 spert_val);
582 extern void si_pcie_ltr_war(si_t *sih);
583 extern void si_pcie_hw_LTR_war(si_t *sih);
584 extern void si_pcie_hw_L1SS_war(si_t *sih);
585 extern void si_pciedev_crwlpciegen2(si_t *sih);
586 extern void si_pcie_prep_D3(si_t *sih, bool enter_D3);
587 extern void si_pciedev_reg_pm_clk_period(si_t *sih);
588 extern void si_d11rsdb_core1_alt_reg_clk_dis(si_t *sih);
589 extern void si_d11rsdb_core1_alt_reg_clk_en(si_t *sih);
590 extern void si_pcie_disable_oobselltr(si_t *sih);
591 extern uint32 si_raw_reg(si_t *sih, uint32 reg, uint32 val, uint32 wrire_req);
592
593 #ifdef WLRSDB
594 extern void si_d11rsdb_core_disable(si_t *sih, uint32 bits);
595 extern void si_d11rsdb_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
596 extern void set_secondary_d11_core(si_t *sih, volatile void **secmap,
597 volatile void **secwrap);
598 #endif // endif
599
600 /* Macro to enable clock gating changes in different cores */
601 #define MEM_CLK_GATE_BIT 5
602 #define GCI_CLK_GATE_BIT 18
603
604 #define USBAPP_CLK_BIT 0
605 #define PCIE_CLK_BIT 3
606 #define ARMCR4_DBG_CLK_BIT 4
607 #define SAMPLE_SYNC_CLK_BIT 17
608 #define PCIE_TL_CLK_BIT 18
609 #define HQ_REQ_BIT 24
610 #define PLL_DIV2_BIT_START 9
611 #define PLL_DIV2_MASK (0x37 << PLL_DIV2_BIT_START)
612 #define PLL_DIV2_DIS_OP (0x37 << PLL_DIV2_BIT_START)
613
614 #define pmu_corereg(si, cc_idx, member, mask, val) \
615 (AOB_ENAB(si) ? si_pmu_corereg(si, si_findcoreidx(si, PMU_CORE_ID, 0), \
616 OFFSETOF(pmuregs_t, member), mask, val) \
617 : si_pmu_corereg(si, cc_idx, OFFSETOF(chipcregs_t, member), \
618 mask, val))
619
620 /* Used only for the regs present in the pmu core and not present in the old cc
621 * core */
622 #define PMU_REG_NEW(si, member, mask, val) \
623 si_corereg(si, si_findcoreidx(si, PMU_CORE_ID, 0), \
624 OFFSETOF(pmuregs_t, member), mask, val)
625
626 #define PMU_REG(si, member, mask, val) \
627 (AOB_ENAB(si) ? si_corereg(si, si_findcoreidx(si, PMU_CORE_ID, 0), \
628 OFFSETOF(pmuregs_t, member), mask, val) \
629 : si_corereg(si, SI_CC_IDX, OFFSETOF(chipcregs_t, member), \
630 mask, val))
631
632 /* Used only for the regs present in the pmu core and not present in the old cc
633 * core */
634 #define PMU_REG_NEW(si, member, mask, val) \
635 si_corereg(si, si_findcoreidx(si, PMU_CORE_ID, 0), \
636 OFFSETOF(pmuregs_t, member), mask, val)
637
638 #define GCI_REG(si, offset, mask, val) \
639 (AOB_ENAB(si) ? si_corereg(si, si_findcoreidx(si, GCI_CORE_ID, 0), offset, \
640 mask, val) \
641 : si_corereg(si, SI_CC_IDX, offset, mask, val))
642
643 /* Used only for the regs present in the gci core and not present in the old cc
644 * core */
645 #define GCI_REG_NEW(si, member, mask, val) \
646 si_corereg(si, si_findcoreidx(si, GCI_CORE_ID, 0), \
647 OFFSETOF(gciregs_t, member), mask, val)
648
649 #define LHL_REG(si, member, mask, val) \
650 si_corereg(si, si_findcoreidx(si, GCI_CORE_ID, 0), \
651 OFFSETOF(gciregs_t, member), mask, val)
652
653 #define CHIPC_REG(si, member, mask, val) \
654 si_corereg(si, SI_CC_IDX, OFFSETOF(chipcregs_t, member), mask, val)
655
656 /* GCI Macros */
657 #define ALLONES_32 0xFFFFFFFF
658 #define GCI_CCTL_SECIRST_OFFSET 0 /**< SeciReset */
659 #define GCI_CCTL_RSTSL_OFFSET 1 /**< ResetSeciLogic */
660 #define GCI_CCTL_SECIEN_OFFSET 2 /**< EnableSeci */
661 #define GCI_CCTL_FSL_OFFSET 3 /**< ForceSeciOutLow */
662 #define GCI_CCTL_SMODE_OFFSET 4 /**< SeciOpMode, 6:4 */
663 #define GCI_CCTL_US_OFFSET 7 /**< UpdateSeci */
664 #define GCI_CCTL_BRKONSLP_OFFSET 8 /**< BreakOnSleep */
665 #define GCI_CCTL_SILOWTOUT_OFFSET 9 /**< SeciInLowTimeout, 10:9 */
666 #define GCI_CCTL_RSTOCC_OFFSET 11 /**< ResetOffChipCoex */
667 #define GCI_CCTL_ARESEND_OFFSET 12 /**< AutoBTSigResend */
668 #define GCI_CCTL_FGCR_OFFSET 16 /**< ForceGciClkReq */
669 #define GCI_CCTL_FHCRO_OFFSET 17 /**< ForceHWClockReqOff */
670 #define GCI_CCTL_FREGCLK_OFFSET 18 /**< ForceRegClk */
671 #define GCI_CCTL_FSECICLK_OFFSET 19 /**< ForceSeciClk */
672 #define GCI_CCTL_FGCA_OFFSET 20 /**< ForceGciClkAvail */
673 #define GCI_CCTL_FGCAV_OFFSET 21 /**< ForceGciClkAvailValue */
674 #define GCI_CCTL_SCS_OFFSET 24 /**< SeciClkStretch, 31:24 */
675 #define GCI_CCTL_SCS 25 /* SeciClkStretch */
676
677 #define GCI_MODE_UART 0x0
678 #define GCI_MODE_SECI 0x1
679 #define GCI_MODE_BTSIG 0x2
680 #define GCI_MODE_GPIO 0x3
681 #define GCI_MODE_MASK 0x7
682
683 #define GCI_CCTL_LOWTOUT_DIS 0x0
684 #define GCI_CCTL_LOWTOUT_10BIT 0x1
685 #define GCI_CCTL_LOWTOUT_20BIT 0x2
686 #define GCI_CCTL_LOWTOUT_30BIT 0x3
687 #define GCI_CCTL_LOWTOUT_MASK 0x3
688
689 #define GCI_CCTL_SCS_DEF 0x19
690 #define GCI_CCTL_SCS_MASK 0xFF
691
692 #define GCI_SECIIN_MODE_OFFSET 0
693 #define GCI_SECIIN_GCIGPIO_OFFSET 4
694 #define GCI_SECIIN_RXID2IP_OFFSET 8
695
696 #define GCI_SECIIN_MODE_MASK 0x7
697 #define GCI_SECIIN_GCIGPIO_MASK 0xF
698
699 #define GCI_SECIOUT_MODE_OFFSET 0
700 #define GCI_SECIOUT_GCIGPIO_OFFSET 4
701 #define GCI_SECIOUT_LOOPBACK_OFFSET 8
702 #define GCI_SECIOUT_SECIINRELATED_OFFSET 16
703
704 #define GCI_SECIOUT_MODE_MASK 0x7
705 #define GCI_SECIOUT_GCIGPIO_MASK 0xF
706 #define GCI_SECIOUT_SECIINRELATED_MASK 0x1
707
708 #define GCI_SECIOUT_SECIINRELATED 0x1
709
710 #define GCI_SECIAUX_RXENABLE_OFFSET 0
711 #define GCI_SECIFIFO_RXENABLE_OFFSET 16
712
713 #define GCI_SECITX_ENABLE_OFFSET 0
714
715 #define GCI_GPIOCTL_INEN_OFFSET 0
716 #define GCI_GPIOCTL_OUTEN_OFFSET 1
717 #define GCI_GPIOCTL_PDN_OFFSET 4
718
719 #define GCI_GPIOIDX_OFFSET 16
720
721 #define GCI_LTECX_SECI_ID 0 /**< SECI port for LTECX */
722 #define GCI_LTECX_TXCONF_EN_OFFSET 2
723 #define GCI_LTECX_PRISEL_EN_OFFSET 3
724
725 /* To access per GCI bit registers */
726 #define GCI_REG_WIDTH 32
727
728 /* number of event summary bits */
729 #define GCI_EVENT_NUM_BITS 32
730
731 /* gci event bits per core */
732 #define GCI_EVENT_BITS_PER_CORE 4
733 #define GCI_EVENT_HWBIT_1 1
734 #define GCI_EVENT_HWBIT_2 2
735 #define GCI_EVENT_SWBIT_1 3
736 #define GCI_EVENT_SWBIT_2 4
737
738 #define GCI_MBDATA_TOWLAN_POS 96
739 #define GCI_MBACK_TOWLAN_POS 104
740 #define GCI_WAKE_TOWLAN_PO 112
741 #define GCI_SWREADY_POS 120
742
743 /* GCI bit positions */
744 /* GCI [127:000] = WLAN [127:0] */
745 #define GCI_WLAN_IP_ID 0
746 #define GCI_WLAN_BEGIN 0
747 #define GCI_WLAN_PRIO_POS (GCI_WLAN_BEGIN + 4)
748 #define GCI_WLAN_PERST_POS (GCI_WLAN_BEGIN + 15)
749
750 /* GCI [255:128] = BT [127:0] */
751 #define GCI_BT_IP_ID 1
752 #define GCI_BT_BEGIN 128
753 #define GCI_BT_MBDATA_TOWLAN_POS (GCI_BT_BEGIN + GCI_MBDATA_TOWLAN_POS)
754 #define GCI_BT_MBACK_TOWLAN_POS (GCI_BT_BEGIN + GCI_MBACK_TOWLAN_POS)
755 #define GCI_BT_WAKE_TOWLAN_POS (GCI_BT_BEGIN + GCI_WAKE_TOWLAN_PO)
756 #define GCI_BT_SWREADY_POS (GCI_BT_BEGIN + GCI_SWREADY_POS)
757
758 /* GCI [639:512] = LTE [127:0] */
759 #define GCI_LTE_IP_ID 4
760 #define GCI_LTE_BEGIN 512
761 #define GCI_LTE_FRAMESYNC_POS (GCI_LTE_BEGIN + 0)
762 #define GCI_LTE_RX_POS (GCI_LTE_BEGIN + 1)
763 #define GCI_LTE_TX_POS (GCI_LTE_BEGIN + 2)
764 #define GCI_LTE_WCI2TYPE_POS (GCI_LTE_BEGIN + 48)
765 #define GCI_LTE_WCI2TYPE_MASK 7
766 #define GCI_LTE_AUXRXDVALID_POS (GCI_LTE_BEGIN + 56)
767
768 /* Reg Index corresponding to ECI bit no x of ECI space */
769 #define GCI_REGIDX(x) ((x) / GCI_REG_WIDTH)
770 /* Bit offset of ECI bit no x in 32-bit words */
771 #define GCI_BITOFFSET(x) ((x) % GCI_REG_WIDTH)
772
773 /* BT SMEM Control Register 0 */
774 #define GCI_BT_SMEM_CTRL0_SUBCORE_ENABLE_PKILL (1 << 28)
775
776 /* End - GCI Macros */
777
778 #define AXI_OOB 0x7
779
780 extern void si_pll_sr_reinit(si_t *sih);
781 extern void si_pll_closeloop(si_t *sih);
782 void si_config_4364_d11_oob(si_t *sih, uint coreid);
783 extern void si_gci_set_femctrl(si_t *sih, osl_t *osh, bool set);
784 extern void si_gci_set_femctrl_mask_ant01(si_t *sih, osl_t *osh, bool set);
785 extern uint si_num_slaveports(si_t *sih, uint coreid);
786 extern uint32 si_get_slaveport_addr(si_t *sih, uint spidx, uint baidx,
787 uint core_id, uint coreunit);
788 extern uint32 si_get_d11_slaveport_addr(si_t *sih, uint spidx, uint baidx,
789 uint coreunit);
790 uint si_introff(si_t *sih);
791 void si_intrrestore(si_t *sih, uint intr_val);
792 void si_nvram_res_masks(si_t *sih, uint32 *min_mask, uint32 *max_mask);
793 extern uint32 si_xtalfreq(si_t *sih);
794 extern uint8 si_getspurmode(si_t *sih);
795 extern uint32 si_get_openloop_dco_code(si_t *sih);
796 extern void si_set_openloop_dco_code(si_t *sih, uint32 openloop_dco_code);
797 extern uint32 si_wrapper_dump_buf_size(si_t *sih);
798 extern uint32 si_wrapper_dump_binary(si_t *sih, uchar *p);
799 extern uint32 si_wrapper_dump_last_timeout(si_t *sih, uint32 *error,
800 uint32 *core, uint32 *ba, uchar *p);
801
802 /* SR Power Control */
803 extern uint32 si_srpwr_request(si_t *sih, uint32 mask, uint32 val);
804 extern uint32 si_srpwr_stat_spinwait(si_t *sih, uint32 mask, uint32 val);
805 extern uint32 si_srpwr_stat(si_t *sih);
806 extern uint32 si_srpwr_domain(si_t *sih);
807 extern uint32 si_srpwr_domain_all_mask(si_t *sih);
808
809 /* SR Power Control */
810 /* No capabilities bit so using chipid for now */
811 #define SRPWR_CAP(sih) (BCM4347_CHIP(sih->chip) || BCM4369_CHIP(sih->chip))
812
813 #ifdef BCMSRPWR
814 extern bool _bcmsrpwr;
815 #if defined(ROM_ENAB_RUNTIME_CHECK) || !defined(DONGLEBUILD)
816 #define SRPWR_ENAB() (_bcmsrpwr)
817 #elif defined(BCMSRPWR_DISABLED)
818 #define SRPWR_ENAB() (0)
819 #else
820 #define SRPWR_ENAB() (1)
821 #endif
822 #else
823 #define SRPWR_ENAB() (0)
824 #endif /* BCMSRPWR */
825
826 /*
827 * Multi-BackPlane architecture. Each can power up/down independently.
828 * Common backplane: shared between BT and WL
829 * ChipC, PCIe, GCI, PMU, SRs
830 * HW powers up as needed
831 * WL BackPlane (WLBP):
832 * ARM, TCM, Main, Aux
833 * Host needs to power up
834 */
835 #define MULTIBP_CAP(sih) (FALSE)
836 #define MULTIBP_ENAB(sih) ((sih) && (sih)->_multibp_enable)
837
838 uint32 si_enum_base(uint devid);
839
840 extern uint8 si_lhl_ps_mode(si_t *sih);
841
842 #ifdef UART_TRAP_DBG
843 void ai_dump_APB_Bridge_registers(si_t *sih);
844 #endif /* UART_TRAP_DBG */
845
846 void si_clrirq_idx(si_t *sih, uint core_idx);
847
848 /* return if scan core is present */
849 bool si_scan_core_present(si_t *sih);
850
851 #endif /* _siutils_h_ */
852