1 /* 2 * Include file private to the SOC Interconnect support files. 3 * 4 * Copyright (C) 1999-2019, Broadcom. 5 * 6 * Unless you and Broadcom execute a separate written software license 7 * agreement governing use of this software, this software is licensed to you 8 * under the terms of the GNU General Public License version 2 (the "GPL"), 9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 10 * following added to such license: 11 * 12 * As a special exception, the copyright holders of this software give you 13 * permission to link this software with independent modules, and to copy and 14 * distribute the resulting executable under terms of your choice, provided that 15 * you also meet, for each linked independent module, the terms and conditions 16 * of the license of that module. An independent module is a module which is 17 * not derived from this software. The special exception does not apply to any 18 * modifications of the software. 19 * 20 * Notwithstanding the above, under no circumstances may you combine this 21 * software in any way with any other Broadcom software provided under a license 22 * other than the GPL, without Broadcom's express prior written consent. 23 * 24 * 25 * <<Broadcom-WL-IPTag/Open:>> 26 * 27 * $Id: siutils_priv.h 795345 2018-12-18 16:52:03Z $ 28 */ 29 30 #ifndef _siutils_priv_h_ 31 #define _siutils_priv_h_ 32 33 #if defined(SI_ERROR_ENFORCE) 34 #define SI_ERROR(args) printf args 35 #else 36 #define SI_ERROR(args) 37 #endif // endif 38 39 #if defined(ENABLE_CORECAPTURE) 40 41 #define SI_PRINT(args) osl_wificc_logDebug args 42 43 #else 44 45 #define SI_PRINT(args) printf args 46 47 #endif /* ENABLE_CORECAPTURE */ 48 49 #define SI_MSG(args) 50 51 #ifdef BCMDBG_SI 52 #define SI_VMSG(args) printf args 53 #else 54 #define SI_VMSG(args) 55 #endif // endif 56 57 #define IS_SIM(chippkg) \ 58 ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID)) 59 60 typedef uint32 (*si_intrsoff_t)(void *intr_arg); 61 typedef void (*si_intrsrestore_t)(void *intr_arg, uint32 arg); 62 typedef bool (*si_intrsenabled_t)(void *intr_arg); 63 64 #define SI_GPIO_MAX 16 65 66 typedef struct gci_gpio_item { 67 void *arg; 68 uint8 gci_gpio; 69 uint8 status; 70 gci_gpio_handler_t handler; 71 struct gci_gpio_item *next; 72 } gci_gpio_item_t; 73 74 #define AI_SLAVE_WRAPPER 0 75 #define AI_MASTER_WRAPPER 1 76 77 typedef struct axi_wrapper { 78 uint32 mfg; 79 uint32 cid; 80 uint32 rev; 81 uint32 wrapper_type; 82 uint32 wrapper_addr; 83 uint32 wrapper_size; 84 } axi_wrapper_t; 85 86 #define SI_MAX_AXI_WRAPPERS 32 87 #define AI_REG_READ_TIMEOUT 300 /* in msec */ 88 89 /* for some combo chips, BT side accesses chipcommon->0x190, as a 16 byte addr 90 */ 91 /* register at 0x19C doesn't exist, so error is logged at the slave wrapper */ 92 #define BT_CC_SPROM_BADREG_LO 0x18000190 93 #define BT_CC_SPROM_BADREG_SIZE 4 94 #define BT_CC_SPROM_BADREG_HI 0 95 #define BCM4350_BT_AXI_ID 6 96 #define BCM4345_BT_AXI_ID 6 97 #define BCM4349_BT_AXI_ID 5 98 #define BCM4364_BT_AXI_ID 5 99 100 /* for BT logging and memory dump, ignore failed access to BT memory */ 101 #define BCM4347_BT_ADDR_HI 0 102 #define BCM4347_BT_ADDR_LO 0x19000000 /* BT address space */ 103 #define BCM4347_BT_SIZE 0x01000000 /* BT address space size */ 104 #define BCM4347_UNUSED_AXI_ID 0xffffffff 105 #define BCM4347_CC_AXI_ID 0 106 #define BCM4347_PCIE_AXI_ID 1 107 108 typedef struct si_cores_info { 109 volatile void *regs[SI_MAXCORES]; /* other regs va */ 110 111 uint coreid[SI_MAXCORES]; /**< id of each core */ 112 uint32 coresba[SI_MAXCORES]; /**< backplane address of each core */ 113 void * 114 regs2[SI_MAXCORES]; /**< va of each core second register set (usbh20) */ 115 uint32 coresba2[SI_MAXCORES]; /**< address of each core second register set 116 (usbh20) */ 117 uint32 coresba_size[SI_MAXCORES]; /**< backplane address space size */ 118 uint32 coresba2_size[SI_MAXCORES]; /**< second address space size */ 119 120 void *wrappers[SI_MAXCORES]; /**< other cores wrapper va */ 121 uint32 wrapba[SI_MAXCORES]; /**< address of controlling wrapper */ 122 123 void *wrappers2[SI_MAXCORES]; /**< other cores wrapper va */ 124 uint32 wrapba2[SI_MAXCORES]; /**< address of controlling wrapper */ 125 126 void *wrappers3[SI_MAXCORES]; /**< other cores wrapper va */ 127 uint32 wrapba3[SI_MAXCORES]; /**< address of controlling wrapper */ 128 129 uint32 cia[SI_MAXCORES]; /**< erom cia entry for each core */ 130 uint32 cib[SI_MAXCORES]; /**< erom cia entry for each core */ 131 132 uint32 csp2ba[SI_MAXCORES]; /**< Second slave port base addr 0 */ 133 uint32 csp2ba_size[SI_MAXCORES]; /**< Second slave port addr space size */ 134 } si_cores_info_t; 135 136 /** misc si info needed by some of the routines */ 137 typedef struct si_info { 138 struct si_pub pub; /**< back plane public state (must be first field) */ 139 140 void *osh; /**< osl os handle */ 141 void *sdh; /**< bcmsdh handle */ 142 143 uint dev_coreid; /**< the core provides driver functions */ 144 void *intr_arg; /**< interrupt callback function arg */ 145 si_intrsoff_t intrsoff_fn; /**< turns chip interrupts off */ 146 si_intrsrestore_t intrsrestore_fn; /**< restore chip interrupts */ 147 si_intrsenabled_t intrsenabled_fn; /**< check if interrupts are enabled */ 148 149 void *pch; /**< PCI/E core handle */ 150 151 bool memseg; /**< flag to toggle MEM_SEG register */ 152 153 char *vars; 154 uint varsz; 155 156 volatile void *curmap; /* current regs va */ 157 158 uint curidx; /**< current core index */ 159 uint numcores; /**< # discovered cores */ 160 161 void *curwrap; /**< current wrapper va */ 162 163 uint32 oob_router; /**< oob router registers for axi */ 164 uint32 oob_router1; /**< oob router registers for axi */ 165 166 si_cores_info_t *cores_info; 167 gci_gpio_item_t *gci_gpio_head; /**< gci gpio interrupts head */ 168 uint chipnew; /**< new chip number */ 169 uint second_bar0win; /**< Backplane region */ 170 uint num_br; /**< # discovered bridges */ 171 uint32 br_wrapba[SI_MAXBR]; /**< address of bridge controlling wrapper */ 172 uint32 xtalfreq; 173 uint32 openloop_dco_code; /**< OPEN loop calibration dco code */ 174 uint8 spurmode; 175 bool device_removed; 176 uint axi_num_wrappers; 177 axi_wrapper_t *axi_wrapper; 178 uint8 device_wake_opt; /* device_wake GPIO number */ 179 uint8 lhl_ps_mode; 180 } si_info_t; 181 182 #define SI_INFO(sih) ((si_info_t *)(uintptr)sih) 183 184 #define GOODCOREADDR(x, b) \ 185 (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \ 186 ISALIGNED((x), SI_CORE_SIZE)) 187 #define GOODREGS(regs) \ 188 ((regs) != NULL && ISALIGNED((uintptr)(regs), SI_CORE_SIZE)) 189 #define BADCOREADDR 0 190 #define GOODIDX(idx) (((uint)idx) < SI_MAXCORES) 191 #define NOREV -1 /**< Invalid rev */ 192 193 #define PCI(si) \ 194 ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \ 195 ((si)->pub.buscoretype == PCI_CORE_ID)) 196 197 #define PCIE_GEN1(si) \ 198 ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \ 199 ((si)->pub.buscoretype == PCIE_CORE_ID)) 200 201 #define PCIE_GEN2(si) \ 202 ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \ 203 ((si)->pub.buscoretype == PCIE2_CORE_ID)) 204 205 #define PCIE(si) (PCIE_GEN1(si) || PCIE_GEN2(si)) 206 207 #define PCMCIA(si) \ 208 ((BUSTYPE((si)->pub.bustype) == PCMCIA_BUS) && ((si)->memseg == TRUE)) 209 210 /** Newer chips can access PCI/PCIE and CC core without requiring to change PCI 211 * BAR0 WIN */ 212 #define SI_FAST(si) (PCIE(si) || (PCI(si) && ((si)->pub.buscorerev >= 13))) 213 214 #define CCREGS_FAST(si) \ 215 (((si)->curmap == NULL) \ 216 ? NULL \ 217 : ((volatile char *)((si)->curmap) + PCI_16KB0_CCREGS_OFFSET)) 218 #define PCIEREGS(si) \ 219 (((volatile char *)((si)->curmap) + PCI_16KB0_PCIREGS_OFFSET)) 220 221 /* 222 * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts 223 * before/ after core switching to avoid invalid register accesss inside ISR. 224 */ 225 #define INTR_OFF(si, intr_val) \ 226 if ((si)->intrsoff_fn && \ 227 (si)->cores_info->coreid[(si)->curidx] == (si)->dev_coreid) { \ 228 intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); \ 229 } 230 #define INTR_RESTORE(si, intr_val) \ 231 if ((si)->intrsrestore_fn && \ 232 (si)->cores_info->coreid[(si)->curidx] == (si)->dev_coreid) { \ 233 (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); \ 234 } 235 236 /* dynamic clock control defines */ 237 #define LPOMINFREQ 25000 /**< low power oscillator min */ 238 #define LPOMAXFREQ 43000 /**< low power oscillator max */ 239 #define XTALMINFREQ 19800000 /**< 20 MHz - 1% */ 240 #define XTALMAXFREQ 20200000 /**< 20 MHz + 1% */ 241 #define PCIMINFREQ 25000000 /**< 25 MHz */ 242 #define PCIMAXFREQ 34000000 /**< 33 MHz + fudge */ 243 244 #define ILP_DIV_5MHZ 0 /**< ILP = 5 MHz */ 245 #define ILP_DIV_1MHZ 4 /**< ILP = 1 MHz */ 246 247 /* GPIO Based LED powersave defines */ 248 #define DEFAULT_GPIO_ONTIME 10 /**< Default: 10% on */ 249 #define DEFAULT_GPIO_OFFTIME 90 /**< Default: 10% on */ 250 251 #ifndef DEFAULT_GPIOTIMERVAL 252 #define DEFAULT_GPIOTIMERVAL \ 253 ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME) 254 #endif // endif 255 256 /* Silicon Backplane externs */ 257 extern void sb_scan(si_t *sih, volatile void *regs, uint devid); 258 extern uint sb_coreid(si_t *sih); 259 extern uint sb_intflag(si_t *sih); 260 extern uint sb_flag(si_t *sih); 261 extern void sb_setint(si_t *sih, int siflag); 262 extern uint sb_corevendor(si_t *sih); 263 extern uint sb_corerev(si_t *sih); 264 extern uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, 265 uint val); 266 extern volatile uint32 *sb_corereg_addr(si_t *sih, uint coreidx, uint regoff); 267 extern bool sb_iscoreup(si_t *sih); 268 extern volatile void *sb_setcoreidx(si_t *sih, uint coreidx); 269 extern uint32 sb_core_cflags(si_t *sih, uint32 mask, uint32 val); 270 extern void sb_core_cflags_wo(si_t *sih, uint32 mask, uint32 val); 271 extern uint32 sb_core_sflags(si_t *sih, uint32 mask, uint32 val); 272 extern void sb_commit(si_t *sih); 273 extern uint32 sb_base(uint32 admatch); 274 extern uint32 sb_size(uint32 admatch); 275 extern void sb_core_reset(si_t *sih, uint32 bits, uint32 resetbits); 276 extern void sb_core_disable(si_t *sih, uint32 bits); 277 extern uint32 sb_addrspace(si_t *sih, uint asidx); 278 extern uint32 sb_addrspacesize(si_t *sih, uint asidx); 279 extern int sb_numaddrspaces(si_t *sih); 280 281 extern uint32 sb_set_initiator_to(si_t *sih, uint32 to, uint idx); 282 283 extern bool sb_taclear(si_t *sih, bool details); 284 285 #if defined(BCMDBG_PHYDUMP) 286 extern void sb_dumpregs(si_t *sih, struct bcmstrbuf *b); 287 #endif // endif 288 289 /* Wake-on-wireless-LAN (WOWL) */ 290 extern bool sb_pci_pmecap(si_t *sih); 291 struct osl_info; 292 extern bool sb_pci_fastpmecap(struct osl_info *osh); 293 extern bool sb_pci_pmeclr(si_t *sih); 294 extern void sb_pci_pmeen(si_t *sih); 295 extern uint sb_pcie_readreg(void *sih, uint addrtype, uint offset); 296 297 /* AMBA Interconnect exported externs */ 298 extern si_t *ai_attach(uint pcidev, osl_t *osh, void *regs, uint bustype, 299 void *sdh, char **vars, uint *varsz); 300 extern si_t *ai_kattach(osl_t *osh); 301 extern void ai_scan(si_t *sih, void *regs, uint devid); 302 303 extern uint ai_flag(si_t *sih); 304 extern uint ai_flag_alt(si_t *sih); 305 extern void ai_setint(si_t *sih, int siflag); 306 extern uint ai_coreidx(si_t *sih); 307 extern uint ai_corevendor(si_t *sih); 308 extern uint ai_corerev(si_t *sih); 309 extern uint ai_corerev_minor(si_t *sih); 310 extern volatile uint32 *ai_corereg_addr(si_t *sih, uint coreidx, uint regoff); 311 extern bool ai_iscoreup(si_t *sih); 312 extern volatile void *ai_setcoreidx(si_t *sih, uint coreidx); 313 extern volatile void *ai_setcoreidx_2ndwrap(si_t *sih, uint coreidx); 314 extern volatile void *ai_setcoreidx_3rdwrap(si_t *sih, uint coreidx); 315 extern uint32 ai_core_cflags(si_t *sih, uint32 mask, uint32 val); 316 extern void ai_core_cflags_wo(si_t *sih, uint32 mask, uint32 val); 317 extern uint32 ai_core_sflags(si_t *sih, uint32 mask, uint32 val); 318 extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, 319 uint val); 320 extern uint ai_corereg_writeonly(si_t *sih, uint coreidx, uint regoff, 321 uint mask, uint val); 322 extern void ai_core_reset(si_t *sih, uint32 bits, uint32 resetbits); 323 extern void ai_d11rsdb_core_reset(si_t *sih, uint32 bits, uint32 resetbits, 324 void *p, volatile void *s); 325 extern void ai_core_disable(si_t *sih, uint32 bits); 326 extern void ai_d11rsdb_core_disable(const si_info_t *sii, uint32 bits, 327 aidmp_t *pmacai, aidmp_t *smacai); 328 extern int ai_numaddrspaces(si_t *sih); 329 extern uint32 ai_addrspace(si_t *sih, uint spidx, uint baidx); 330 extern uint32 ai_addrspacesize(si_t *sih, uint spidx, uint baidx); 331 extern void ai_coreaddrspaceX(si_t *sih, uint asidx, uint32 *addr, 332 uint32 *size); 333 extern uint ai_wrap_reg(si_t *sih, uint32 offset, uint32 mask, uint32 val); 334 extern void ai_update_backplane_timeouts(si_t *sih, bool enable, uint32 timeout, 335 uint32 cid); 336 extern uint32 ai_clear_backplane_to(si_t *sih); 337 void ai_force_clocks(si_t *sih, uint clock_state); 338 extern uint ai_num_slaveports(si_t *sih, uint coreidx); 339 340 #ifdef BCM_BACKPLANE_TIMEOUT 341 uint32 ai_clear_backplane_to_fast(si_t *sih, void *addr); 342 #endif /* BCM_BACKPLANE_TIMEOUT */ 343 344 #if defined(AXI_TIMEOUTS) || defined(BCM_BACKPLANE_TIMEOUT) 345 extern uint32 ai_clear_backplane_to_per_core(si_t *sih, uint coreid, 346 uint coreunit, void *wrap); 347 #endif /* AXI_TIMEOUTS || BCM_BACKPLANE_TIMEOUT */ 348 349 #if defined(BCMDBG_PHYDUMP) 350 extern void ai_dumpregs(si_t *sih, struct bcmstrbuf *b); 351 #endif // endif 352 353 extern uint32 ai_wrapper_dump_buf_size(si_t *sih); 354 extern uint32 ai_wrapper_dump_binary(si_t *sih, uchar *p); 355 extern bool ai_check_enable_backplane_log(si_t *sih); 356 extern uint32 ai_wrapper_dump_last_timeout(si_t *sih, uint32 *error, 357 uint32 *core, uint32 *ba, uchar *p); 358 359 #define ub_scan(a, b, c) \ 360 do { \ 361 } while (0) 362 #define ub_flag(a) (0) 363 #define ub_setint(a, b) \ 364 do { \ 365 } while (0) 366 #define ub_coreidx(a) (0) 367 #define ub_corevendor(a) (0) 368 #define ub_corerev(a) (0) 369 #define ub_iscoreup(a) (0) 370 #define ub_setcoreidx(a, b) (0) 371 #define ub_core_cflags(a, b, c) (0) 372 #define ub_core_cflags_wo(a, b, c) \ 373 do { \ 374 } while (0) 375 #define ub_core_sflags(a, b, c) (0) 376 #define ub_corereg(a, b, c, d, e) (0) 377 #define ub_core_reset(a, b, c) \ 378 do { \ 379 } while (0) 380 #define ub_core_disable(a, b) \ 381 do { \ 382 } while (0) 383 #define ub_numaddrspaces(a) (0) 384 #define ub_addrspace(a, b) (0) 385 #define ub_addrspacesize(a, b) (0) 386 #define ub_view(a, b) \ 387 do { \ 388 } while (0) 389 #define ub_dumpregs(a, b) \ 390 do { \ 391 } while (0) 392 393 #endif /* _siutils_priv_h_ */ 394