1 /****************************************************************************** 2 * 3 * Copyright (C) 2009-2018 Realtek Corporation 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at: 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 ******************************************************************************/ 18 19 #ifndef HARDWARE_H 20 #define HARDWARE_H 21 22 #include <stdint.h> 23 #include <stddef.h> 24 25 #if __BYTE_ORDER == __LITTLE_ENDIAN 26 #define cpu_to_le16(d) (d) 27 #define cpu_to_le32(d) (d) 28 #define le16_to_cpu(d) (d) 29 #define le32_to_cpu(d) (d) 30 #elif __BYTE_ORDER == __BIG_ENDIAN 31 #define cpu_to_le16(d) bswap_16(d) 32 #define cpu_to_le32(d) bswap_32(d) 33 #define le16_to_cpu(d) bswap_16(d) 34 #define le32_to_cpu(d) bswap_32(d) 35 #else 36 #error "Unknown byte order" 37 #endif 38 39 #define FIRMWARE_DIRECTORY "/vendor/etc/firmware/%s" 40 #define BT_CONFIG_DIRECTORY "/vendor/etc/firmware/%s" 41 #define PATCH_DATA_FIELD_MAX_SIZE 252 42 #define RTK_VENDOR_CONFIG_MAGIC 0x8723ab55 43 #define MAX_PATCH_SIZE_24K (1024 * 24) // 24K 44 #define MAX_PATCH_SIZE_40K (1024 * 40) // 40K 45 46 #define MAX_ORG_CONFIG_SIZE (0x100 * 14) 47 #define MAX_ALT_CONFIG_SIZE (0x100 * 2) 48 49 struct rtk_bt_vendor_config_entry { 50 uint16_t offset; 51 uint8_t entry_len; 52 uint8_t entry_data[0]; 53 } __attribute__((packed)); 54 55 struct rtk_bt_vendor_config { 56 uint32_t signature; 57 uint16_t data_len; 58 struct rtk_bt_vendor_config_entry entry[0]; 59 } __attribute__((packed)); 60 61 #define HCI_CMD_MAX_LEN 258 62 63 #define HCI_VERSION_MASK_10 (1 << 0) // Bluetooth Core Spec 1.0b 64 #define HCI_VERSION_MASK_11 (1 << 1) // Bluetooth Core Spec 1.1 65 #define HCI_VERSION_MASK_12 (1 << 2) // Bluetooth Core Spec 1.2 66 #define HCI_VERSION_MASK_20 (1 << 3) // Bluetooth Core Spec 2.0+EDR 67 #define HCI_VERSION_MASK_21 (1 << 4) // Bluetooth Core Spec 2.1+EDR 68 #define HCI_VERSION_MASK_30 (1 << 5) // Bluetooth Core Spec 3.0+HS 69 #define HCI_VERSION_MASK_40 (1 << 6) // Bluetooth Core Spec 4.0 70 #define HCI_VERSION_MASK_41 (1 << 7) // Bluetooth Core Spec 4.1 71 #define HCI_VERSION_MASK_42 (1 << 8) // Bluetooth Core Spec 4.2 72 #define HCI_VERSION_MASK_ALL (0xFFFFFFFF) 73 74 #define HCI_REVISION_MASK_ALL (0xFFFFFFFF) 75 76 #define LMP_SUBVERSION_NONE (0x0) 77 #define LMPSUBVERSION_8723a (0x1200) 78 79 #define CHIPTYPE_NONE (0x1F) // Chip Type's range: 0x0 ~ 0xF 80 #define CHIP_TYPE_MASK_ALL (0xFFFFFFFF) 81 82 #define PROJECT_ID_MASK_ALL (0xFFFFFFFF) // temp used for unknown project id for a new chip 83 84 #define PATCH_OPTIONAL_MATCH_FLAG_CHIPTYPE (0x1) 85 86 #define CONFIG_MAC_OFFSET_GEN_1_2 (0x3C) // MAC's OFFSET in config/efuse for realtek generation 1~2 bluetooth chip 87 #define CONFIG_MAC_OFFSET_GEN_3PLUS (0x44) // MAC's OFFSET in config/efuse for rtk generation 3+ bluetooth chip 88 #define CONFIG_MAC_OFFSET_GEN_4PLUS (0x30) // MAC's OFFSET in config/efuse for rtk generation 4+ bluetooth chip 89 90 #define HCI_EVT_CMD_CMPL_OPCODE_OFFSET (3) // opcode's offset in COMMAND Completed Event 91 #define HCI_EVT_CMD_CMPL_STATUS_OFFSET (5) // status's offset in COMMAND Completed Event 92 93 #define HCI_EVT_CMD_CMPL_OP1001_HCI_VERSION_OFFSET \ 94 (6) // HCI_Version's offset in COMMAND Completed Event for OpCode 0x1001(Read Local Version Information Command) 95 #define HCI_EVT_CMD_CMPL_OP1001_HCI_REVISION_OFFSET \ 96 (7) // HCI_Revision's offset in COMMAND Completed Event for OpCode 0x1001(Read Local Version Information Command) 97 #define HCI_EVT_CMD_CMPL_OP1001_LMP_SUBVERSION_OFFSET \ 98 (12) // LMP Subversion's offset in COMMAND Completed Event for OpCode 0x1001(Read Local Version Information Command) 99 #define HCI_EVT_CMD_CMPL_OP0C14_LOCAL_NAME_OFFSET \ 100 (6) // Local Name's offset in COMMAND Completed Event for OpCode 0x0C14(Read Local Name Command) 101 #define HCI_EVT_CMD_CMPL_OP1009_BDADDR_OFFSET \ 102 (6) // BD_ADDR's offset in COMMAND Completed Event for OpCode 0x1009(Read BD_ADDR Command) 103 #define HCI_EVT_CMD_CMPL_OPFC6D_EVERSION_OFFSET \ 104 (6) // eversion's offset in COMMAND Completed Event for OpCode 0xfc6d(Read eVERSION Vendor Command) 105 #define HCI_EVT_CMD_CMPL_OPFC61_CHIPTYPE_OFFSET \ 106 (6) // chip type's offset in COMMAND Completed Event for OpCode 0xfc61(Read ChipType Vendor Command) 107 108 #define HCI_CMD_PREAMBLE_SIZE (3) 109 #define HCI_CMD_READ_CHIP_TYPE_SIZE (5) 110 111 #define H5_SYNC_REQ_SIZE (2) 112 #define H5_SYNC_RESP_SIZE (2) 113 #define H5_CONF_REQ_SIZE (3) 114 #define H5_CONF_RESP_SIZE (2) 115 116 /****************************************************************************** 117 ** Local type definitions 118 ******************************************************************************/ 119 120 /* Hardware Configuration State */ 121 enum { 122 HW_CFG_H5_INIT = 1, 123 HW_CFG_READ_LOCAL_VER, 124 HW_CFG_READ_ECO_VER, // eco version 125 HW_CFG_READ_CHIP_TYPE, 126 HW_CFG_START, 127 HW_CFG_SET_UART_BAUD_HOST, // change FW baudrate 128 HW_CFG_SET_UART_BAUD_CONTROLLER, // change Host baudrate 129 HW_CFG_SET_UART_HW_FLOW_CONTROL, 130 HW_CFG_RESET_CHANNEL_CONTROLLER, 131 HW_RESET_CONTROLLER, 132 HARDWARE_INIT_COMPLETE, 133 HW_CFG_DL_FW_PATCH 134 }; 135 136 /* h/w config control block */ 137 typedef struct { 138 uint32_t max_patch_size; 139 uint32_t baudrate; 140 uint16_t lmp_subversion; 141 uint16_t lmp_subversion_default; 142 uint16_t lmp_sub_current; 143 uint8_t state; /* Hardware configuration state */ 144 uint8_t eversion; 145 uint32_t project_id_mask; 146 uint8_t hci_version; 147 uint8_t hci_revision; 148 uint8_t chip_type; 149 uint8_t dl_fw_flag; 150 int fw_len; /* FW patch file len */ 151 size_t config_len; /* Config patch file len */ 152 unsigned int total_len; /* FW & config extracted buf len */ 153 uint8_t *fw_buf; /* FW patch file buf */ 154 uint8_t *config_buf; /* Config patch file buf */ 155 uint8_t *total_buf; /* FW & config extracted buf */ 156 uint8_t patch_frag_cnt; /* Patch fragment count download */ 157 uint8_t patch_frag_idx; /* Current patch fragment index */ 158 uint8_t patch_frag_len; /* Patch fragment length */ 159 uint8_t patch_frag_tail; /* Last patch fragment length */ 160 uint8_t hw_flow_cntrl; /* Uart flow control, bit7:set, bit0:enable */ 161 uint16_t vid; /* usb vendor id */ 162 uint16_t pid; /* usb product id */ 163 uint8_t heartbeat; /* heartbeat */ 164 } bt_hw_cfg_cb_t; 165 166 /* low power mode parameters */ 167 typedef struct { 168 uint8_t sleep_mode; /* 0(disable),1(UART),9(H5) */ 169 uint8_t host_stack_idle_threshold; /* Unit scale 300ms/25ms */ 170 uint8_t host_controller_idle_threshold; /* Unit scale 300ms/25ms */ 171 uint8_t bt_wake_polarity; /* 0=Active Low, 1= Active High */ 172 uint8_t host_wake_polarity; /* 0=Active Low, 1= Active High */ 173 uint8_t allow_host_sleep_during_sco; 174 uint8_t combine_sleep_mode_and_lpm; 175 uint8_t enable_uart_txd_tri_state; /* UART_TXD Tri-State */ 176 uint8_t sleep_guard_time; /* sleep guard time in 12.5ms */ 177 uint8_t wakeup_guard_time; /* wakeup guard time in 12.5ms */ 178 uint8_t txd_config; /* TXD is high in sleep state */ 179 uint8_t pulsed_host_wake; /* pulsed host wake if mode = 1 */ 180 } bt_lpm_param_t; 181 182 #define ROM_LMP_NONE 0x0000 183 #define ROM_LMP_8723a 0x1200 184 #define ROM_LMP_8723b 0x8723 185 #define ROM_LMP_8821a 0X8821 186 #define ROM_LMP_8761a 0X8761 187 #define ROM_LMP_8761b 0X8761 188 #define ROM_LMP_8703a 0x8723 189 #define ROM_LMP_8763a 0x8763 190 #define ROM_LMP_8703b 0x8703 191 #define ROM_LMP_8723c 0x8703 192 #define ROM_LMP_8822b 0x8822 193 #define ROM_LMP_8723d 0x8723 194 #define ROM_LMP_8821c 0x8821 195 #define ROM_LMP_8822c 0x8822 196 197 struct rtk_epatch_entry { 198 uint16_t chip_id; 199 uint16_t patch_length; 200 uint32_t patch_offset; 201 uint32_t svn_version; 202 uint32_t coex_version; 203 } __attribute__((packed)); 204 205 struct rtk_epatch { 206 uint8_t signature[8]; 207 uint32_t fw_version; 208 uint16_t number_of_patch; 209 struct rtk_epatch_entry entry[0]; 210 } __attribute__((packed)); 211 212 extern bt_hw_cfg_cb_t hw_cfg_cb; 213 extern struct rtk_epatch_entry *rtk_get_patch_entry(bt_hw_cfg_cb_t *cfg_cb); 214 int getmacaddr(unsigned char *addr); 215 uint8_t rtk_get_fw_project_id(uint8_t *p_buf); 216 int rtk_get_bt_firmware(uint8_t **fw_buf, char *fw_short_name); 217 uint8_t get_heartbeat_from_hardware(void); 218 219 #endif 220