1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __PHYDMADAPTIVITY_H__ 27 #define __PHYDMADAPTIVITY_H__ 28 29 #define ADAPTIVITY_VERSION "9.7.08" /*@20210121 changed by Archer, 30 *add dynamic th_l2h_ini 31 */ 32 #define ADC_BACKOFF 12 33 #define EDCCA_TH_L2H_LB 48 34 #define TH_L2H_DIFF_IGI 8 35 #define EDCCA_HL_DIFF_NORMAL 8 36 #define IGI_2_DBM(igi) (igi - 110) 37 #define L2H_INI_RECORD_NUM 4 38 #define L2H_INI_LIMIT_PERIOD 60 /*60 sec*/ 39 /*@ [PHYDM-337][Old IC] EDCCA TH = IGI + REG setting*/ 40 #define ODM_IC_PWDB_EDCCA (ODM_RTL8188E | ODM_RTL8723B | ODM_RTL8192E |\ 41 ODM_RTL8881A | ODM_RTL8821 | ODM_RTL8812) 42 43 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP)) 44 #define ADAPT_DC_BACKOFF 2 45 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) 46 #define ADAPT_DC_BACKOFF 4 47 #elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) 48 #define ADAPT_DC_BACKOFF 0 49 #endif 50 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) 51 enum phydm_regulation_type { 52 REGULATION_FCC = 0, 53 REGULATION_MKK = 1, 54 REGULATION_ETSI = 2, 55 REGULATION_WW = 3, 56 MAX_REGULATION_NUM = 4 57 }; 58 #endif 59 struct phydm_l2h_ini_recorder_strcut { 60 u8 l2h_ini_bitmap; /*@Don't add any new parameter before this*/ 61 s8 l2h_ini_hist[L2H_INI_RECORD_NUM]; 62 u32 low_rate_tx_fail_hist[L2H_INI_RECORD_NUM]; 63 u8 damping_limit_en; 64 s8 damping_limit_val; /*@Limit l2h_ini_dyn_max*/ 65 u32 limit_time; 66 u32 limit_low_rate_tx_fail; 67 }; 68 69 enum phydm_edcca_mode { 70 PHYDM_EDCCA_NORMAL_MODE = 0, 71 PHYDM_EDCCA_ADAPT_MODE = 1 72 }; 73 74 enum phydm_adapinfo { 75 PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE = 0, 76 PHYDM_ADAPINFO_TH_L2H_INI, 77 PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF, 78 PHYDM_ADAPINFO_AP_NUM_TH, 79 PHYDM_ADAPINFO_DOMAIN_CODE_2G, 80 PHYDM_ADAPINFO_DOMAIN_CODE_5G, 81 PHYDM_ADAPINFO_SWITCH_TH_L2H_INI_IN_BAND 82 }; 83 84 enum phydm_mac_edcca_type { 85 PHYDM_IGNORE_EDCCA = 0, 86 PHYDM_DONT_IGNORE_EDCCA = 1 87 }; 88 89 enum phydm_adaptivity_debug_mode { 90 PHYDM_ADAPT_MSG = 0, 91 PHYDM_ADAPT_DEBUG = 1, 92 PHYDM_ADAPT_RESUME = 2, 93 PHYDM_L2H_INI_DEBUG = 3 94 }; 95 96 struct phydm_adaptivity_struct { 97 struct phydm_l2h_ini_recorder_strcut l2h_ini_recorder_t; 98 u32 low_rate_tx_fail_th[3]; 99 u32 rts_drop_limit_time; 100 s8 l2h_ini_range_max; /*@l2h_ini_dynamic_max*/ 101 s8 l2h_ini_range_min; /*@l2h_ini_dynamic_min*/ 102 boolean rts_drop_en; 103 boolean is_dbg_low_rate_tx_fail_th; 104 boolean is_adapt_by_dig; 105 boolean mode_cvrt_en; 106 s8 th_l2h_ini_backup; 107 s8 th_edcca_hl_diff_backup; 108 s8 igi_base; 109 s8 h2l_lb; 110 s8 l2h_lb; 111 u8 ap_num_th; 112 u8 l2h_dyn_min; 113 u32 adaptivity_dbg_port; /*N:0x208, AC:0x209*/ 114 u8 debug_mode; 115 u16 igi_up_bound_lmt_cnt; /*@When igi_up_bound_lmt_cnt !=0, limit IGI upper bound to "adapt_igi_up"*/ 116 u16 igi_up_bound_lmt_val; /*@max value of igi_up_bound_lmt_cnt*/ 117 boolean igi_lmt_en; 118 u8 adapt_igi_up; 119 u32 rvrt_val[2]; /*@all rvrt_val for pause API must set to u32*/ 120 s8 th_l2h; 121 s8 th_h2l; 122 u8 regulation_2g; 123 u8 regulation_5g; 124 u8 switch_th_l2h_ini_in_band; 125 }; 126 127 #ifdef PHYDM_SUPPORT_ADAPTIVITY 128 void phydm_adaptivity_debug(void *dm_void, char input[][16], u32 *_used, 129 char *output, u32 *_out_len); 130 131 void phydm_set_edcca_val(void *dm_void, u32 *val_buf, u8 val_len); 132 #endif 133 134 void phydm_set_edcca_threshold_api(void *dm_void); 135 136 void phydm_adaptivity_info_init(void *dm_void, enum phydm_adapinfo cmn_info, 137 u32 value); 138 139 void phydm_adaptivity_info_update(void *dm_void, enum phydm_adapinfo cmn_info, 140 u32 value); 141 142 void phydm_adaptivity_init(void *dm_void); 143 144 void phydm_adaptivity(void *dm_void); 145 146 #endif 147