1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /* ************************************************************
27 * include files
28 * ************************************************************ */
29
30 #include "mp_precomp.h"
31 #include "phydm_precomp.h"
32
33 #ifdef CONFIG_ANT_DETECTION
34
35 /* @IS_ANT_DETECT_SUPPORT_SINGLE_TONE(adapter)
36 * IS_ANT_DETECT_SUPPORT_RSSI(adapter)
37 * IS_ANT_DETECT_SUPPORT_PSD(adapter) */
38
39 /* @1 [1. Single Tone method] =================================================== */
40
41 /*@
42 * Description:
43 * Set Single/Dual Antenna default setting for products that do not do detection in advance.
44 *
45 * Added by Joseph, 2012.03.22
46 * */
odm_sw_ant_div_construct_scan_chnl(void * adapter,u8 scan_chnl)47 void odm_sw_ant_div_construct_scan_chnl(
48 void *adapter,
49 u8 scan_chnl)
50 {
51 }
52
odm_sw_ant_div_select_scan_chnl(void * adapter)53 u8 odm_sw_ant_div_select_scan_chnl(
54 void *adapter)
55 {
56 return 0;
57 }
58
odm_single_dual_antenna_default_setting(void * dm_void)59 void odm_single_dual_antenna_default_setting(
60 void *dm_void)
61 {
62 struct dm_struct *dm = (struct dm_struct *)dm_void;
63 struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
64 void *adapter = dm->adapter;
65
66 u8 bt_ant_num = BT_GetPgAntNum(adapter);
67 /* Set default antenna A and B status */
68 if (bt_ant_num == 2) {
69 dm_swat_table->ANTA_ON = true;
70 dm_swat_table->ANTB_ON = true;
71
72 } else if (bt_ant_num == 1) {
73 /* Set antenna A as default */
74 dm_swat_table->ANTA_ON = true;
75 dm_swat_table->ANTB_ON = false;
76
77 } else
78 RT_ASSERT(false, ("Incorrect antenna number!!\n"));
79 }
80
81 /* @2 8723A ANT DETECT
82 *
83 * Description:
84 * Implement IQK single tone for RF DPK loopback and BB PSD scanning.
85 * This function is cooperated with BB team Neil.
86 *
87 * Added by Roger, 2011.12.15
88 * */
89 boolean
odm_single_dual_antenna_detection(void * dm_void,u8 mode)90 odm_single_dual_antenna_detection(
91 void *dm_void,
92 u8 mode)
93 {
94 struct dm_struct *dm = (struct dm_struct *)dm_void;
95 void *adapter = dm->adapter;
96 struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
97 u32 current_channel, rf_loop_reg;
98 u8 n;
99 u32 reg88c, regc08, reg874, regc50, reg948, regb2c, reg92c, reg930, reg064, afe_rrx_wait_cca;
100 u8 initial_gain = 0x5a;
101 u32 PSD_report_tmp;
102 u32 ant_a_report = 0x0, ant_b_report = 0x0, ant_0_report = 0x0;
103 boolean is_result = true;
104
105 PHYDM_DBG(dm, DBG_ANT_DIV, "%s============>\n", __func__);
106
107 if (!(dm->support_ic_type & ODM_RTL8723B))
108 return is_result;
109
110 /* Retrieve antenna detection registry info, added by Roger, 2012.11.27. */
111 if (!IS_ANT_DETECT_SUPPORT_SINGLE_TONE(((PADAPTER)adapter)))
112 return is_result;
113
114 /* @1 Backup Current RF/BB Settings */
115
116 current_channel = odm_get_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK);
117 rf_loop_reg = odm_get_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK);
118 if (dm->support_ic_type & ODM_RTL8723B) {
119 reg92c = odm_get_bb_reg(dm, REG_DPDT_CONTROL, MASKDWORD);
120 reg930 = odm_get_bb_reg(dm, rfe_ctrl_anta_src, MASKDWORD);
121 reg948 = odm_get_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD);
122 regb2c = odm_get_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD);
123 reg064 = odm_get_mac_reg(dm, REG_SYM_WLBT_PAPE_SEL, BIT(29));
124 odm_set_bb_reg(dm, REG_DPDT_CONTROL, 0x3, 0x1);
125 odm_set_bb_reg(dm, rfe_ctrl_anta_src, 0xff, 0x77);
126 odm_set_mac_reg(dm, REG_SYM_WLBT_PAPE_SEL, BIT(29), 0x1); /* @dbg 7 */
127 odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0x3c0, 0x0); /* @dbg 8 */
128 odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, BIT(31), 0x0);
129 }
130
131 ODM_delay_us(10);
132
133 /* Store A path Register 88c, c08, 874, c50 */
134 reg88c = odm_get_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD);
135 regc08 = odm_get_bb_reg(dm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD);
136 reg874 = odm_get_bb_reg(dm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD);
137 regc50 = odm_get_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD);
138
139 /* Store AFE Registers */
140 if (dm->support_ic_type & ODM_RTL8723B)
141 afe_rrx_wait_cca = odm_get_bb_reg(dm, REG_RX_WAIT_CCA, MASKDWORD);
142
143 /* Set PSD 128 pts */
144 odm_set_bb_reg(dm, REG_FPGA0_PSD_FUNCTION, BIT(14) | BIT15, 0x0); /* @128 pts */
145
146 /* To SET CH1 to do */
147 odm_set_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK, 0x7401); /* @channel 1 */
148
149 /* @AFE all on step */
150 if (dm->support_ic_type & ODM_RTL8723B)
151 odm_set_bb_reg(dm, REG_RX_WAIT_CCA, MASKDWORD, 0x01c00016);
152
153 /* @3 wire Disable */
154 odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD, 0xCCF000C0);
155
156 /* @BB IQK setting */
157 odm_set_bb_reg(dm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD, 0x000800E4);
158 odm_set_bb_reg(dm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD, 0x22208000);
159
160 /* @IQK setting tone@ 4.34Mhz */
161 odm_set_bb_reg(dm, REG_TX_IQK_TONE_A, MASKDWORD, 0x10008C1C);
162 odm_set_bb_reg(dm, REG_TX_IQK, MASKDWORD, 0x01007c00);
163
164 /* Page B init */
165 odm_set_bb_reg(dm, REG_CONFIG_ANT_A, MASKDWORD, 0x00080000);
166 odm_set_bb_reg(dm, REG_CONFIG_ANT_A, MASKDWORD, 0x0f600000);
167 odm_set_bb_reg(dm, REG_RX_IQK, MASKDWORD, 0x01004800);
168 odm_set_bb_reg(dm, REG_RX_IQK_TONE_A, MASKDWORD, 0x10008c1f);
169 if (dm->support_ic_type & ODM_RTL8723B) {
170 odm_set_bb_reg(dm, REG_TX_IQK_PI_A, MASKDWORD, 0x82150016);
171 odm_set_bb_reg(dm, REG_RX_IQK_PI_A, MASKDWORD, 0x28150016);
172 }
173 odm_set_bb_reg(dm, REG_IQK_AGC_RSP, MASKDWORD, 0x001028d0);
174 odm_set_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, 0x7f, initial_gain);
175
176 /* @IQK Single tone start */
177 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x808000);
178 odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf9000000);
179 odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf8000000);
180
181 ODM_delay_us(10000);
182
183 /* PSD report of antenna A */
184 PSD_report_tmp = 0x0;
185 for (n = 0; n < 2; n++) {
186 PSD_report_tmp = phydm_get_psd_data(dm, 14, initial_gain);
187 if (PSD_report_tmp > ant_a_report)
188 ant_a_report = PSD_report_tmp;
189 }
190
191 /* @change to Antenna B */
192 if (dm->support_ic_type & ODM_RTL8723B) {
193 odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0xfff, 0x280);
194 odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, BIT(31), 0x1);
195 }
196
197 ODM_delay_us(10);
198
199 /* PSD report of antenna B */
200 PSD_report_tmp = 0x0;
201 for (n = 0; n < 2; n++) {
202 PSD_report_tmp = phydm_get_psd_data(dm, 14, initial_gain);
203 if (PSD_report_tmp > ant_b_report)
204 ant_b_report = PSD_report_tmp;
205 }
206
207 /* @Close IQK Single Tone function */
208 odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
209
210 /* @1 Return to antanna A */
211 if (dm->support_ic_type & ODM_RTL8723B) {
212 /* @external DPDT */
213 odm_set_bb_reg(dm, REG_DPDT_CONTROL, MASKDWORD, reg92c);
214
215 /* @internal S0/S1 */
216 odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD, reg948);
217 odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD, regb2c);
218 odm_set_bb_reg(dm, rfe_ctrl_anta_src, MASKDWORD, reg930);
219 odm_set_mac_reg(dm, REG_SYM_WLBT_PAPE_SEL, BIT(29), reg064);
220 }
221
222 odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD, reg88c);
223 odm_set_bb_reg(dm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD, regc08);
224 odm_set_bb_reg(dm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD, reg874);
225 odm_set_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, 0x7F, 0x40);
226 odm_set_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD, regc50);
227 odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, current_channel);
228 odm_set_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK, rf_loop_reg);
229
230 /* Reload AFE Registers */
231 if (dm->support_ic_type & ODM_RTL8723B)
232 odm_set_bb_reg(dm, REG_RX_WAIT_CCA, MASKDWORD, afe_rrx_wait_cca);
233
234 if (dm->support_ic_type & ODM_RTL8723B) {
235 PHYDM_DBG(dm, DBG_ANT_DIV, "psd_report_A[%d]= %d\n", 2416,
236 ant_a_report);
237 PHYDM_DBG(dm, DBG_ANT_DIV, "psd_report_B[%d]= %d\n", 2416,
238 ant_b_report);
239
240 /* @2 Test ant B based on ant A is ON */
241 if (ant_a_report >= 100 && ant_b_report >= 100 && ant_a_report <= 135 && ant_b_report <= 135) {
242 u8 TH1 = 2, TH2 = 6;
243
244 if ((ant_a_report - ant_b_report < TH1) || (ant_b_report - ant_a_report < TH1)) {
245 dm_swat_table->ANTA_ON = true;
246 dm_swat_table->ANTB_ON = true;
247 PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Dual Antenna\n",
248 __func__);
249 } else if (((ant_a_report - ant_b_report >= TH1) && (ant_a_report - ant_b_report <= TH2)) ||
250 ((ant_b_report - ant_a_report >= TH1) && (ant_b_report - ant_a_report <= TH2))) {
251 dm_swat_table->ANTA_ON = false;
252 dm_swat_table->ANTB_ON = false;
253 is_result = false;
254 PHYDM_DBG(dm, DBG_ANT_DIV,
255 "%s: Need to check again\n",
256 __func__);
257 } else {
258 dm_swat_table->ANTA_ON = true;
259 dm_swat_table->ANTB_ON = false;
260 PHYDM_DBG(dm, DBG_ANT_DIV,
261 "%s: Single Antenna\n", __func__);
262 }
263 dm->ant_detected_info.is_ant_detected = true;
264 dm->ant_detected_info.db_for_ant_a = ant_a_report;
265 dm->ant_detected_info.db_for_ant_b = ant_b_report;
266 dm->ant_detected_info.db_for_ant_o = ant_0_report;
267
268 } else {
269 PHYDM_DBG(dm, DBG_ANT_DIV, "return false!!\n");
270 is_result = false;
271 }
272 }
273 return is_result;
274 }
275
276 /* @1 [2. Scan AP RSSI method] ================================================== */
277
278 boolean
odm_sw_ant_div_check_before_link(void * dm_void)279 odm_sw_ant_div_check_before_link(
280 void *dm_void)
281 {
282 #if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM)
283
284 struct dm_struct *dm = (struct dm_struct *)dm_void;
285 void *adapter = dm->adapter;
286 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
287 //PMGNT_INFO mgnt_info = &adapter->MgntInfo;
288 PMGNT_INFO mgnt_info = &(((PADAPTER)(adapter))->MgntInfo);
289 struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
290 struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
291 s8 score = 0;
292 PRT_WLAN_BSS p_tmp_bss_desc, p_test_bss_desc;
293 u8 power_target_L = 9, power_target_H = 16;
294 u8 tmp_power_diff = 0, power_diff = 0, avg_power_diff = 0, max_power_diff = 0, min_power_diff = 0xff;
295 u16 index, counter = 0;
296 static u8 scan_channel;
297 u32 tmp_swas_no_link_bk_reg948;
298
299 PHYDM_DBG(dm, DBG_ANT_DIV, "ANTA_ON = (( %d )) , ANTB_ON = (( %d ))\n",
300 dm->dm_swat_table.ANTA_ON, dm->dm_swat_table.ANTB_ON);
301
302 /* @if(HP id) */
303 {
304 if (dm->dm_swat_table.rssi_ant_dect_result == true && dm->support_ic_type == ODM_RTL8723B) {
305 PHYDM_DBG(dm, DBG_ANT_DIV,
306 "8723B RSSI-based Antenna Detection is done\n");
307 return false;
308 }
309
310 if (dm->support_ic_type == ODM_RTL8723B) {
311 if (dm_swat_table->swas_no_link_bk_reg948 == 0xff)
312 dm_swat_table->swas_no_link_bk_reg948 = odm_read_4byte(dm, REG_S0_S1_PATH_SWITCH);
313 }
314 }
315
316 if (dm->adapter == NULL) { /* @For BSOD when plug/unplug fast. //By YJ,120413 */
317 /* The ODM structure is not initialized. */
318 return false;
319 }
320
321 /* Retrieve antenna detection registry info, added by Roger, 2012.11.27. */
322 if (!IS_ANT_DETECT_SUPPORT_RSSI(((PADAPTER)adapter)))
323 return false;
324 else
325 PHYDM_DBG(dm, DBG_ANT_DIV, "Antenna Detection: RSSI method\n");
326
327 /* Since driver is going to set BB register, it shall check if there is another thread controlling BB/RF. */
328 odm_acquire_spin_lock(dm, RT_RF_STATE_SPINLOCK);
329 if (hal_data->eRFPowerState != eRfOn || mgnt_info->RFChangeInProgress || mgnt_info->bMediaConnect) {
330 odm_release_spin_lock(dm, RT_RF_STATE_SPINLOCK);
331
332 PHYDM_DBG(dm, DBG_ANT_DIV,
333 "%s: rf_change_in_progress(%x), e_rf_power_state(%x)\n",
334 __func__, mgnt_info->RFChangeInProgress,
335 hal_data->eRFPowerState);
336
337 dm_swat_table->swas_no_link_state = 0;
338
339 return false;
340 } else
341 odm_release_spin_lock(dm, RT_RF_STATE_SPINLOCK);
342 PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->swas_no_link_state = %d\n",
343 dm_swat_table->swas_no_link_state);
344 /* @1 Run AntDiv mechanism "Before Link" part. */
345 if (dm_swat_table->swas_no_link_state == 0) {
346 /* @1 Prepare to do Scan again to check current antenna state. */
347
348 /* Set check state to next step. */
349 dm_swat_table->swas_no_link_state = 1;
350
351 /* @Copy Current Scan list. */
352 mgnt_info->tmpNumBssDesc = mgnt_info->NumBssDesc;
353 PlatformMoveMemory((void *)mgnt_info->tmpbssDesc, (void *)mgnt_info->bssDesc, sizeof(RT_WLAN_BSS) * MAX_BSS_DESC);
354
355 /* @Go back to scan function again. */
356 PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Scan one more time\n",
357 __func__);
358 mgnt_info->ScanStep = 0;
359 mgnt_info->bScanAntDetect = true;
360 scan_channel = odm_sw_ant_div_select_scan_chnl(adapter);
361
362 if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8821)) {
363 if (fat_tab->rx_idle_ant == MAIN_ANT)
364 odm_update_rx_idle_ant(dm, AUX_ANT);
365 else
366 odm_update_rx_idle_ant(dm, MAIN_ANT);
367 if (scan_channel == 0) {
368 PHYDM_DBG(dm, DBG_ANT_DIV,
369 "%s: No AP List Avaiable, Using ant(%s)\n",
370 __func__,
371 (fat_tab->rx_idle_ant == MAIN_ANT) ?
372 "AUX_ANT" : "MAIN_ANT");
373
374 if (IS_5G_WIRELESS_MODE(mgnt_info->dot11CurrentWirelessMode)) {
375 dm_swat_table->ant_5g = fat_tab->rx_idle_ant;
376 PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->ant_5g=%s\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
377 } else {
378 dm_swat_table->ant_2g = fat_tab->rx_idle_ant;
379 PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->ant_2g=%s\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
380 }
381 return false;
382 }
383
384 PHYDM_DBG(dm, DBG_ANT_DIV,
385 "%s: Change to %s for testing.\n", __func__,
386 ((fat_tab->rx_idle_ant == MAIN_ANT) ?
387 "MAIN_ANT" : "AUX_ANT"));
388 } else if (dm->support_ic_type & (ODM_RTL8723B)) {
389 /*Switch Antenna to another one.*/
390
391 tmp_swas_no_link_bk_reg948 = odm_read_4byte(dm, REG_S0_S1_PATH_SWITCH);
392
393 if (dm_swat_table->cur_antenna == MAIN_ANT && tmp_swas_no_link_bk_reg948 == 0x200) {
394 odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0xfff, 0x280);
395 odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, BIT(31), 0x1);
396 dm_swat_table->cur_antenna = AUX_ANT;
397 } else {
398 PHYDM_DBG(dm, DBG_ANT_DIV,
399 "Reg[948]= (( %x )) was in wrong state\n",
400 tmp_swas_no_link_bk_reg948);
401 return false;
402 }
403 ODM_delay_us(10);
404
405 PHYDM_DBG(dm, DBG_ANT_DIV,
406 "%s: Change to (( %s-ant)) for testing.\n",
407 __func__,
408 (dm_swat_table->cur_antenna == MAIN_ANT) ?
409 "MAIN" : "AUX");
410 }
411
412 odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel);
413 PlatformSetTimer(adapter, &mgnt_info->ScanTimer, 5);
414
415 return true;
416 } else { /* @dm_swat_table->swas_no_link_state == 1 */
417 /* @1 ScanComple() is called after antenna swiched. */
418 /* @1 Check scan result and determine which antenna is going */
419 /* @1 to be used. */
420
421 PHYDM_DBG(dm, DBG_ANT_DIV, " tmp_num_bss_desc= (( %d ))\n",
422 mgnt_info->tmpNumBssDesc); /* @debug for Dino */
423
424 for (index = 0; index < mgnt_info->tmpNumBssDesc; index++) {
425 p_tmp_bss_desc = &mgnt_info->tmpbssDesc[index]; /* @Antenna 1 */
426 p_test_bss_desc = &mgnt_info->bssDesc[index]; /* @Antenna 2 */
427
428 if (PlatformCompareMemory(p_test_bss_desc->bdBssIdBuf, p_tmp_bss_desc->bdBssIdBuf, 6) != 0) {
429 PHYDM_DBG(dm, DBG_ANT_DIV,
430 "%s: ERROR!! This shall not happen.\n",
431 __func__);
432 continue;
433 }
434
435 if (dm->support_ic_type != ODM_RTL8723B) {
436 if (p_tmp_bss_desc->ChannelNumber == scan_channel) {
437 if (p_tmp_bss_desc->RecvSignalPower > p_test_bss_desc->RecvSignalPower) {
438 PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Compare scan entry: score++\n", __func__);
439 RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen);
440 PHYDM_DBG(dm, DBG_ANT_DIV, "at ch %d, Original: %d, Test: %d\n\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
441
442 score++;
443 PlatformMoveMemory(p_test_bss_desc, p_tmp_bss_desc, sizeof(RT_WLAN_BSS));
444 } else if (p_tmp_bss_desc->RecvSignalPower < p_test_bss_desc->RecvSignalPower) {
445 PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Compare scan entry: score--\n", __func__);
446 RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen);
447 PHYDM_DBG(dm, DBG_ANT_DIV, "at ch %d, Original: %d, Test: %d\n\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
448 score--;
449 } else {
450 if (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp < 5000) {
451 RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen);
452 PHYDM_DBG(dm, DBG_ANT_DIV, "at ch %d, Original: %d, Test: %d\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
453 PHYDM_DBG(dm, DBG_ANT_DIV, "The 2nd Antenna didn't get this AP\n\n");
454 }
455 }
456 }
457 } else { /* @8723B */
458 if (p_tmp_bss_desc->ChannelNumber == scan_channel) {
459 PHYDM_DBG(dm, DBG_ANT_DIV, "channel_number == scan_channel->(( %d ))\n", p_tmp_bss_desc->ChannelNumber);
460
461 if (p_tmp_bss_desc->RecvSignalPower > p_test_bss_desc->RecvSignalPower) { /* Pow(Ant1) > Pow(Ant2) */
462 counter++;
463 tmp_power_diff = (u8)(p_tmp_bss_desc->RecvSignalPower - p_test_bss_desc->RecvSignalPower);
464 power_diff = power_diff + tmp_power_diff;
465
466 PHYDM_DBG(dm, DBG_ANT_DIV, "Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
467 PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "SSID:", p_tmp_bss_desc->bdSsIdBuf);
468 PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "BSSID:", p_tmp_bss_desc->bdSsIdBuf);
469
470 #if 0
471 /* PHYDM_DBG(dm,DBG_ANT_DIV, "tmp_power_diff: (( %d)),max_power_diff: (( %d)),min_power_diff: (( %d))\n", tmp_power_diff,max_power_diff,min_power_diff); */
472 #endif
473 if (tmp_power_diff > max_power_diff)
474 max_power_diff = tmp_power_diff;
475 if (tmp_power_diff < min_power_diff)
476 min_power_diff = tmp_power_diff;
477 #if 0
478 /* PHYDM_DBG(dm,DBG_ANT_DIV, "max_power_diff: (( %d)),min_power_diff: (( %d))\n",max_power_diff,min_power_diff); */
479 #endif
480
481 PlatformMoveMemory(p_test_bss_desc, p_tmp_bss_desc, sizeof(RT_WLAN_BSS));
482 } else if (p_test_bss_desc->RecvSignalPower > p_tmp_bss_desc->RecvSignalPower) { /* Pow(Ant1) < Pow(Ant2) */
483 counter++;
484 tmp_power_diff = (u8)(p_test_bss_desc->RecvSignalPower - p_tmp_bss_desc->RecvSignalPower);
485 power_diff = power_diff + tmp_power_diff;
486 PHYDM_DBG(dm, DBG_ANT_DIV, "Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
487 PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "SSID:", p_tmp_bss_desc->bdSsIdBuf);
488 PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "BSSID:", p_tmp_bss_desc->bdSsIdBuf);
489 if (tmp_power_diff > max_power_diff)
490 max_power_diff = tmp_power_diff;
491 if (tmp_power_diff < min_power_diff)
492 min_power_diff = tmp_power_diff;
493 } else { /* Pow(Ant1) = Pow(Ant2) */
494 if (p_test_bss_desc->bdTstamp > p_tmp_bss_desc->bdTstamp) { /* Stamp(Ant1) < Stamp(Ant2) */
495 PHYDM_DBG(dm, DBG_ANT_DIV, "time_diff: %lld\n", (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp) / 1000);
496 if (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp > 5000) {
497 counter++;
498 PHYDM_DBG(dm, DBG_ANT_DIV, "Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
499 PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "SSID:", p_tmp_bss_desc->bdSsIdBuf);
500 PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "BSSID:", p_tmp_bss_desc->bdSsIdBuf);
501 min_power_diff = 0;
502 }
503 } else
504 PHYDM_DBG(dm, DBG_ANT_DIV, "[Error !!!]: Time_diff: %lld\n", (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp) / 1000);
505 }
506 }
507 }
508 }
509
510 if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8821)) {
511 if (mgnt_info->NumBssDesc != 0 && score < 0) {
512 PHYDM_DBG(dm, DBG_ANT_DIV,
513 "%s: Using ant(%s)\n", __func__,
514 (fat_tab->rx_idle_ant == MAIN_ANT) ?
515 "MAIN_ANT" : "AUX_ANT");
516 } else {
517 PHYDM_DBG(dm, DBG_ANT_DIV,
518 "%s: Remain ant(%s)\n", __func__,
519 (fat_tab->rx_idle_ant == MAIN_ANT) ?
520 "AUX_ANT" : "MAIN_ANT");
521
522 if (fat_tab->rx_idle_ant == MAIN_ANT)
523 odm_update_rx_idle_ant(dm, AUX_ANT);
524 else
525 odm_update_rx_idle_ant(dm, MAIN_ANT);
526 }
527
528 if (IS_5G_WIRELESS_MODE(mgnt_info->dot11CurrentWirelessMode)) {
529 dm_swat_table->ant_5g = fat_tab->rx_idle_ant;
530 PHYDM_DBG(dm, DBG_ANT_DIV,
531 "dm_swat_table->ant_5g=%s\n",
532 (fat_tab->rx_idle_ant == MAIN_ANT) ?
533 "MAIN_ANT" : "AUX_ANT");
534 } else {
535 dm_swat_table->ant_2g = fat_tab->rx_idle_ant;
536 PHYDM_DBG(dm, DBG_ANT_DIV,
537 "dm_swat_table->ant_2g=%s\n",
538 (fat_tab->rx_idle_ant == MAIN_ANT) ?
539 "MAIN_ANT" : "AUX_ANT");
540 }
541 } else if (dm->support_ic_type == ODM_RTL8723B) {
542 if (counter == 0) {
543 if (dm->dm_swat_table.pre_aux_fail_detec == false) {
544 dm->dm_swat_table.pre_aux_fail_detec = true;
545 dm->dm_swat_table.rssi_ant_dect_result = false;
546 PHYDM_DBG(dm, DBG_ANT_DIV, "counter=(( 0 )) , [[ Cannot find any AP with Aux-ant ]] -> Scan Target-channel again\n");
547
548 /* @3 [ Scan again ] */
549 odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel);
550 PlatformSetTimer(adapter, &mgnt_info->ScanTimer, 5);
551 return true;
552 } else { /* pre_aux_fail_detec == true */
553 /* @2 [ Single Antenna ] */
554 dm->dm_swat_table.pre_aux_fail_detec = false;
555 dm->dm_swat_table.rssi_ant_dect_result = true;
556 PHYDM_DBG(dm, DBG_ANT_DIV, "counter=(( 0 )) , [[ Still cannot find any AP ]]\n");
557 PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Single antenna\n", __func__);
558 }
559 dm->dm_swat_table.aux_fail_detec_counter++;
560 } else {
561 dm->dm_swat_table.pre_aux_fail_detec = false;
562
563 if (counter == 3) {
564 avg_power_diff = ((power_diff - max_power_diff - min_power_diff) >> 1) + ((max_power_diff + min_power_diff) >> 2);
565 PHYDM_DBG(dm, DBG_ANT_DIV, "counter: (( %d )) , power_diff: (( %d ))\n", counter, power_diff);
566 PHYDM_DBG(dm, DBG_ANT_DIV, "[ counter==3 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d ))\n", avg_power_diff, max_power_diff, min_power_diff);
567 } else if (counter >= 4) {
568 avg_power_diff = (power_diff - max_power_diff - min_power_diff) / (counter - 2);
569 PHYDM_DBG(dm, DBG_ANT_DIV, "counter: (( %d )) , power_diff: (( %d ))\n", counter, power_diff);
570 PHYDM_DBG(dm, DBG_ANT_DIV, "[ counter>=4 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d ))\n", avg_power_diff, max_power_diff, min_power_diff);
571
572 } else { /* @counter==1,2 */
573 avg_power_diff = power_diff / counter;
574 PHYDM_DBG(dm, DBG_ANT_DIV, "avg_power_diff: (( %d )) , counter: (( %d )) , power_diff: (( %d ))\n", avg_power_diff, counter, power_diff);
575 }
576
577 /* @2 [ Retry ] */
578 if (avg_power_diff >= power_target_L && avg_power_diff <= power_target_H) {
579 dm->dm_swat_table.retry_counter++;
580
581 if (dm->dm_swat_table.retry_counter <= 3) {
582 dm->dm_swat_table.rssi_ant_dect_result = false;
583 PHYDM_DBG(dm, DBG_ANT_DIV, "[[ Low confidence result ]] avg_power_diff= (( %d )) -> Scan Target-channel again ]]\n", avg_power_diff);
584
585 /* @3 [ Scan again ] */
586 odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel);
587 PlatformSetTimer(adapter, &mgnt_info->ScanTimer, 5);
588 return true;
589 } else {
590 dm->dm_swat_table.rssi_ant_dect_result = true;
591 PHYDM_DBG(dm, DBG_ANT_DIV, "[[ Still Low confidence result ]] (( retry_counter > 3 ))\n");
592 PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Single antenna\n", __func__);
593 }
594 }
595 /* @2 [ Dual Antenna ] */
596 else if ((mgnt_info->NumBssDesc != 0) && (avg_power_diff < power_target_L)) {
597 dm->dm_swat_table.rssi_ant_dect_result = true;
598 if (dm->dm_swat_table.ANTB_ON == false) {
599 dm->dm_swat_table.ANTA_ON = true;
600 dm->dm_swat_table.ANTB_ON = true;
601 }
602 PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Dual antenna\n", __func__);
603 dm->dm_swat_table.dual_ant_counter++;
604
605 /* set bt coexDM from 1ant coexDM to 2ant coexDM */
606 BT_SetBtCoexAntNum(adapter, BT_COEX_ANT_TYPE_DETECTED, 2);
607
608 /* @3 [ Init antenna diversity ] */
609 dm->support_ability |= ODM_BB_ANT_DIV;
610 odm_ant_div_init(dm);
611 }
612 /* @2 [ Single Antenna ] */
613 else if (avg_power_diff > power_target_H) {
614 dm->dm_swat_table.rssi_ant_dect_result = true;
615 if (dm->dm_swat_table.ANTB_ON == true) {
616 dm->dm_swat_table.ANTA_ON = true;
617 dm->dm_swat_table.ANTB_ON = false;
618 #if 0
619 /* @bt_set_bt_coex_ant_num(adapter, BT_COEX_ANT_TYPE_DETECTED, 1); */
620 #endif
621 }
622 PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Single antenna\n", __func__);
623 dm->dm_swat_table.single_ant_counter++;
624 }
625 }
626 #if 0
627 /* PHYDM_DBG(dm,DBG_ANT_DIV, "is_result=(( %d ))\n",dm->dm_swat_table.rssi_ant_dect_result); */
628 #endif
629 PHYDM_DBG(dm, DBG_ANT_DIV,
630 "dual_ant_counter = (( %d )), single_ant_counter = (( %d )) , retry_counter = (( %d )) , aux_fail_detec_counter = (( %d ))\n\n\n",
631 dm->dm_swat_table.dual_ant_counter,
632 dm->dm_swat_table.single_ant_counter,
633 dm->dm_swat_table.retry_counter,
634 dm->dm_swat_table.aux_fail_detec_counter);
635
636 /* @2 recover the antenna setting */
637
638 if (dm->dm_swat_table.ANTB_ON == false)
639 odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0xfff, (dm_swat_table->swas_no_link_bk_reg948));
640
641 PHYDM_DBG(dm, DBG_ANT_DIV,
642 "is_result=(( %d )), Recover Reg[948]= (( %x ))\n\n",
643 dm->dm_swat_table.rssi_ant_dect_result,
644 dm_swat_table->swas_no_link_bk_reg948);
645 }
646
647 /* @Check state reset to default and wait for next time. */
648 dm_swat_table->swas_no_link_state = 0;
649 mgnt_info->bScanAntDetect = false;
650
651 return false;
652 }
653
654 #else
655 return false;
656 #endif
657
658 return false;
659 }
660
661 /* @1 [3. PSD method] ========================================================== */
odm_single_dual_antenna_detection_psd(void * dm_void)662 void odm_single_dual_antenna_detection_psd(
663 void *dm_void)
664 {
665 struct dm_struct *dm = (struct dm_struct *)dm_void;
666 u32 channel_ori;
667 u8 initial_gain = 0x36;
668 u8 tone_idx;
669 u8 tone_lenth_1 = 7, tone_lenth_2 = 4;
670 u16 tone_idx_1[7] = {88, 104, 120, 8, 24, 40, 56};
671 u16 tone_idx_2[4] = {8, 24, 40, 56};
672 u32 psd_report_main[11] = {0}, psd_report_aux[11] = {0};
673 /* u8 tone_lenth_1=4, tone_lenth_2=2; */
674 /* u16 tone_idx_1[4]={88, 120, 24, 56}; */
675 /* u16 tone_idx_2[2]={ 24, 56}; */
676 /* u32 psd_report_main[6]={0}, psd_report_aux[6]={0}; */
677
678 u32 PSD_report_temp, max_psd_report_main = 0, max_psd_report_aux = 0;
679 u32 PSD_power_threshold;
680 u32 main_psd_result = 0, aux_psd_result = 0;
681 u32 regc50, reg948, regb2c, regc14, reg908;
682 u32 i = 0, test_num = 8;
683
684 if (dm->support_ic_type != ODM_RTL8723B)
685 return;
686
687 PHYDM_DBG(dm, DBG_ANT_DIV, "%s============>\n", __func__);
688
689 /* @2 [ Backup Current RF/BB Settings ] */
690
691 channel_ori = odm_get_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK);
692 reg948 = odm_get_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD);
693 regb2c = odm_get_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD);
694 regc50 = odm_get_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD);
695 regc14 = odm_get_bb_reg(dm, R_0xc14, MASKDWORD);
696 reg908 = odm_get_bb_reg(dm, R_0x908, MASKDWORD);
697
698 /* @2 [ setting for doing PSD function (CH4)] */
699 odm_set_bb_reg(dm, REG_FPGA0_RFMOD, BIT(24), 0); /* @disable whole CCK block */
700 odm_write_1byte(dm, REG_TXPAUSE, 0xFF); /* Turn off TX -> Pause TX Queue */
701 odm_set_bb_reg(dm, R_0xc14, MASKDWORD, 0x0); /* @[ Set IQK Matrix = 0 ] equivalent to [ Turn off CCA] */
702
703 /* PHYTXON while loop */
704 odm_set_bb_reg(dm, R_0x908, MASKDWORD, 0x803);
705 while (odm_get_bb_reg(dm, R_0xdf4, BIT(6))) {
706 i++;
707 if (i > 1000000) {
708 PHYDM_DBG(dm, DBG_ANT_DIV,
709 "Wait in %s() more than %d times!\n",
710 __FUNCTION__, i);
711 break;
712 }
713 }
714
715 odm_set_bb_reg(dm, R_0xc50, 0x7f, initial_gain);
716 odm_set_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); /* Set RF to CH4 & 40M */
717 odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0xf); /* @3 wire Disable 88c[23:20]=0xf */
718 odm_set_bb_reg(dm, REG_FPGA0_PSD_FUNCTION, BIT(14) | BIT15, 0x0); /* 128 pt */ /* Set PSD 128 ptss */
719 ODM_delay_us(3000);
720
721 /* @2 [ Doing PSD Function in (CH4)] */
722
723 /* @Antenna A */
724 PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Main-ant (CH4)\n");
725 odm_set_bb_reg(dm, R_0x948, 0xfff, 0x200);
726 ODM_delay_us(10);
727 PHYDM_DBG(dm, DBG_ANT_DIV, "dbg\n");
728 for (i = 0; i < test_num; i++) {
729 for (tone_idx = 0; tone_idx < tone_lenth_1; tone_idx++) {
730 PSD_report_temp = phydm_get_psd_data(dm, tone_idx_1[tone_idx], initial_gain);
731 /* @if( PSD_report_temp>psd_report_main[tone_idx] ) */
732 psd_report_main[tone_idx] += PSD_report_temp;
733 }
734 }
735 /* @Antenna B */
736 PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Aux-ant (CH4)\n");
737 odm_set_bb_reg(dm, R_0x948, 0xfff, 0x280);
738 ODM_delay_us(10);
739 for (i = 0; i < test_num; i++) {
740 for (tone_idx = 0; tone_idx < tone_lenth_1; tone_idx++) {
741 PSD_report_temp = phydm_get_psd_data(dm, tone_idx_1[tone_idx], initial_gain);
742 /* @if( PSD_report_temp>psd_report_aux[tone_idx] ) */
743 psd_report_aux[tone_idx] += PSD_report_temp;
744 }
745 }
746 /* @2 [ Doing PSD Function in (CH8)] */
747
748 odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0x0); /* @3 wire enable 88c[23:20]=0x0 */
749 ODM_delay_us(3000);
750
751 odm_set_bb_reg(dm, R_0xc50, 0x7f, initial_gain);
752 odm_set_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); /* Set RF to CH8 & 40M */
753
754 odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0xf); /* @3 wire Disable 88c[23:20]=0xf */
755 ODM_delay_us(3000);
756
757 /* @Antenna A */
758 PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Main-ant (CH8)\n");
759 odm_set_bb_reg(dm, R_0x948, 0xfff, 0x200);
760 ODM_delay_us(10);
761
762 for (i = 0; i < test_num; i++) {
763 for (tone_idx = 0; tone_idx < tone_lenth_2; tone_idx++) {
764 PSD_report_temp = phydm_get_psd_data(dm, tone_idx_2[tone_idx], initial_gain);
765 /* @if( PSD_report_temp>psd_report_main[tone_idx] ) */
766 psd_report_main[tone_lenth_1 + tone_idx] += PSD_report_temp;
767 }
768 }
769
770 /* @Antenna B */
771 PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Aux-ant (CH8)\n");
772 odm_set_bb_reg(dm, R_0x948, 0xfff, 0x280);
773 ODM_delay_us(10);
774
775 for (i = 0; i < test_num; i++) {
776 for (tone_idx = 0; tone_idx < tone_lenth_2; tone_idx++) {
777 PSD_report_temp = phydm_get_psd_data(dm, tone_idx_2[tone_idx], initial_gain);
778 /* @if( PSD_report_temp>psd_report_aux[tone_idx] ) */
779 psd_report_aux[tone_lenth_1 + tone_idx] += PSD_report_temp;
780 }
781 }
782
783 /* @2 [ Calculate Result ] */
784
785 PHYDM_DBG(dm, DBG_ANT_DIV, "\nMain PSD Result: (ALL)\n");
786 for (tone_idx = 0; tone_idx < (tone_lenth_1 + tone_lenth_2); tone_idx++) {
787 PHYDM_DBG(dm, DBG_ANT_DIV, "[Tone-%d]: %d,\n", (tone_idx + 1),
788 psd_report_main[tone_idx]);
789 main_psd_result += psd_report_main[tone_idx];
790 if (psd_report_main[tone_idx] > max_psd_report_main)
791 max_psd_report_main = psd_report_main[tone_idx];
792 }
793 PHYDM_DBG(dm, DBG_ANT_DIV,
794 "--------------------------- \nTotal_Main= (( %d ))\n",
795 main_psd_result);
796 PHYDM_DBG(dm, DBG_ANT_DIV, "MAX_Main = (( %d ))\n",
797 max_psd_report_main);
798
799 PHYDM_DBG(dm, DBG_ANT_DIV, "\nAux PSD Result: (ALL)\n");
800 for (tone_idx = 0; tone_idx < (tone_lenth_1 + tone_lenth_2); tone_idx++) {
801 PHYDM_DBG(dm, DBG_ANT_DIV, "[Tone-%d]: %d,\n", (tone_idx + 1),
802 psd_report_aux[tone_idx]);
803 aux_psd_result += psd_report_aux[tone_idx];
804 if (psd_report_aux[tone_idx] > max_psd_report_aux)
805 max_psd_report_aux = psd_report_aux[tone_idx];
806 }
807 PHYDM_DBG(dm, DBG_ANT_DIV,
808 "--------------------------- \nTotal_Aux= (( %d ))\n",
809 aux_psd_result);
810 PHYDM_DBG(dm, DBG_ANT_DIV, "MAX_Aux = (( %d ))\n\n",
811 max_psd_report_aux);
812
813 /* @main_psd_result=main_psd_result-max_psd_report_main; */
814 /* @aux_psd_result=aux_psd_result-max_psd_report_aux; */
815 PSD_power_threshold = (main_psd_result * 7) >> 3;
816
817 PHYDM_DBG(dm, DBG_ANT_DIV,
818 "[ Main_result, Aux_result ] = [ %d , %d ], PSD_power_threshold=(( %d ))\n",
819 main_psd_result, aux_psd_result, PSD_power_threshold);
820
821 /* @3 [ Dual Antenna ] */
822 if (aux_psd_result >= PSD_power_threshold) {
823 if (dm->dm_swat_table.ANTB_ON == false) {
824 dm->dm_swat_table.ANTA_ON = true;
825 dm->dm_swat_table.ANTB_ON = true;
826 }
827 PHYDM_DBG(dm, DBG_ANT_DIV,
828 "odm_sw_ant_div_check_before_link(): Dual antenna\n");
829
830 #if 0
831 /* set bt coexDM from 1ant coexDM to 2ant coexDM */
832 /* @bt_set_bt_coex_ant_num(adapter, BT_COEX_ANT_TYPE_DETECTED, 2); */
833 #endif
834
835 /* @Init antenna diversity */
836 dm->support_ability |= ODM_BB_ANT_DIV;
837 odm_ant_div_init(dm);
838 }
839 /* @3 [ Single Antenna ] */
840 else {
841 if (dm->dm_swat_table.ANTB_ON == true) {
842 dm->dm_swat_table.ANTA_ON = true;
843 dm->dm_swat_table.ANTB_ON = false;
844 }
845 PHYDM_DBG(dm, DBG_ANT_DIV,
846 "odm_sw_ant_div_check_before_link(): Single antenna\n");
847 }
848
849 /* @2 [ Recover all parameters ] */
850
851 odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, channel_ori);
852 odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0x0); /* @3 wire enable 88c[23:20]=0x0 */
853 odm_set_bb_reg(dm, R_0xc50, 0x7f, regc50);
854
855 odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD, reg948);
856 odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD, regb2c);
857
858 odm_set_bb_reg(dm, REG_FPGA0_RFMOD, BIT(24), 1); /* @enable whole CCK block */
859 odm_write_1byte(dm, REG_TXPAUSE, 0x0); /* Turn on TX */ /* Resume TX Queue */
860 odm_set_bb_reg(dm, R_0xc14, MASKDWORD, regc14); /* @[ Set IQK Matrix = 0 ] equivalent to [ Turn on CCA] */
861 odm_set_bb_reg(dm, R_0x908, MASKDWORD, reg908);
862
863 return;
864 }
865
odm_sw_ant_detect_init(void * dm_void)866 void odm_sw_ant_detect_init(void *dm_void)
867 {
868 #if (RTL8723B_SUPPORT == 1)
869
870 struct dm_struct *dm = (struct dm_struct *)dm_void;
871 struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
872
873 if (dm->support_ic_type != ODM_RTL8723B)
874 return;
875
876 /* @dm_swat_table->pre_antenna = MAIN_ANT; */
877 /* @dm_swat_table->cur_antenna = MAIN_ANT; */
878 dm_swat_table->swas_no_link_state = 0;
879 dm_swat_table->pre_aux_fail_detec = false;
880 dm_swat_table->swas_no_link_bk_reg948 = 0xff;
881
882 #ifdef CONFIG_PSD_TOOL
883 phydm_psd_init(dm);
884 #endif
885 #endif
886 }
887 #endif
888
889