1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __PHYDMANTDIV_H__ 27 #define __PHYDMANTDIV_H__ 28 29 /*@#define ANTDIV_VERSION "2.0" //2014.11.04*/ 30 /*@#define ANTDIV_VERSION "2.1" //2015.01.13 Dino*/ 31 /*@#define ANTDIV_VERSION "2.2" 2015.01.16 Dino*/ 32 /*@#define ANTDIV_VERSION "3.1" 2015.07.29 YuChen,remove 92c 92d 8723a*/ 33 /*@#define ANTDIV_VERSION "3.2" 2015.08.11 Stanley, disable antenna*/ 34 /*@diversity when BT is enable for 8723B*/ 35 /*@#define ANTDIV_VERSION "3.3" 2015.08.12 Stanley. 8723B does not*/ 36 /*@need to check the antenna is control by BT,*/ 37 /*@because antenna diversity only works when */ 38 /*@BT is disable or radio off*/ 39 /*@#define ANTDIV_VERSION "3.4" 2015.08.28 Dino 1.Add 8821A Smart */ 40 /*@Antenna 2. Add 8188F SW S0S1 Antenna*/ 41 /*@Diversity*/ 42 /*@#define ANTDIV_VERSION "3.5" 2015.10.07 Stanley Always check antenna*/ 43 /*@detection result from BT-coex. for 8723B,*/ 44 /*@not from PHYDM*/ 45 /*@#define ANTDIV_VERSION "3.6"*/ /*@2015.11.16 Stanley */ 46 /*@#define ANTDIV_VERSION "3.7" 2015.11.20 Dino Add SmartAnt FAT Patch */ 47 /*@#define ANTDIV_VERSION "3.8" 2015.12.21 Dino, Add SmartAnt dynamic*/ 48 /*@training packet num */ 49 /*@#define ANTDIV_VERSION "3.9" 2016.01.05 Dino, Add SmartAnt cmd for*/ 50 /*@converting single & two smtant, and add cmd*/ 51 /*@for adjust truth table */ 52 #define ANTDIV_VERSION "4.0" /*@2017.05.25 Mark, Add SW antenna diversity*/ 53 /*@for 8821c because HW transient issue */ 54 55 /* @1 ============================================================ 56 * 1 Definition 57 * 1 ============================================================ 58 */ 59 60 #define ANTDIV_INIT 0xff 61 #define MAIN_ANT 1 /*@ant A or ant Main or S1*/ 62 #define AUX_ANT 2 /*@AntB or ant Aux or S0*/ 63 #define MAX_ANT 3 /* @3 for AP using*/ 64 65 #define ANT1_2G 0 66 /* @= ANT2_5G for 8723D BTG S1 RX S0S1 diversity for 8723D, TX fixed at S1 */ 67 #define ANT2_2G 1 68 /* @= ANT1_5G for 8723D BTG S0 RX S0S1 diversity for 8723D, TX fixed at S1 */ 69 /*smart antenna*/ 70 #define SUPPORT_RF_PATH_NUM 4 71 #define SUPPORT_BEAM_PATTERN_NUM 4 72 #define NUM_ANTENNA_8821A 2 73 74 #define SUPPORT_BEAM_SET_PATTERN_NUM 16 75 76 #define NO_FIX_TX_ANT 0 77 #define FIX_TX_AT_MAIN 1 78 #define FIX_AUX_AT_MAIN 2 79 80 /* @Antenna Diversty Control type */ 81 #define ODM_AUTO_ANT 0 82 #define ODM_FIX_MAIN_ANT 1 83 #define ODM_FIX_AUX_ANT 2 84 85 #define ODM_N_ANTDIV_SUPPORT (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B |\ 86 ODM_RTL8188F | ODM_RTL8723D | ODM_RTL8195A |\ 87 ODM_RTL8197F | ODM_RTL8721D | ODM_RTL8710C) 88 #define ODM_AC_ANTDIV_SUPPORT (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 |\ 89 ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814B |\ 90 ODM_RTL8195B | ODM_RTL8814C) 91 #define ODM_JGR3_ANTDIV_SUPPORT (ODM_RTL8197G | ODM_RTL8723F) 92 #define ODM_ANTDIV_SUPPORT (ODM_N_ANTDIV_SUPPORT | ODM_AC_ANTDIV_SUPPORT |\ 93 ODM_JGR3_ANTDIV_SUPPORT) 94 #define ODM_SMART_ANT_SUPPORT (ODM_RTL8188E | ODM_RTL8192E) 95 #define ODM_HL_SMART_ANT_TYPE1_SUPPORT (ODM_RTL8821 | ODM_RTL8822B) 96 97 #define ODM_ANTDIV_2G_SUPPORT_IC (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B |\ 98 ODM_RTL8881A | ODM_RTL8188F | ODM_RTL8723D |\ 99 ODM_RTL8197F | ODM_RTL8197G|ODM_RTL8723F) 100 #define ODM_ANTDIV_5G_SUPPORT_IC (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 |\ 101 ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8195B|ODM_RTL8723F) 102 103 #define ODM_ANTDIV_SUPPORT_IC (ODM_ANTDIV_2G_SUPPORT_IC | ODM_ANTDIV_5G_SUPPORT_IC) 104 105 #define ODM_EVM_ANTDIV_IC (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8822B |\ 106 ODM_RTL8197G) 107 108 #define ODM_ANTDIV_2G BIT(0) 109 #define ODM_ANTDIV_5G BIT(1) 110 111 #define ANTDIV_ON 1 112 #define ANTDIV_OFF 0 113 114 #define ANT_PATH_A 0 115 #define ANT_PATH_B 1 116 #define ANT_PATH_AB 2 117 118 #define FAT_ON 1 119 #define FAT_OFF 0 120 121 #define TX_BY_DESC 1 122 #define TX_BY_REG 0 123 124 #define RSSI_METHOD 0 125 #define EVM_METHOD 1 126 #define CRC32_METHOD 2 127 #define TP_METHOD 3 128 129 #define INIT_ANTDIV_TIMMER 0 130 #define CANCEL_ANTDIV_TIMMER 1 131 #define RELEASE_ANTDIV_TIMMER 2 132 133 #define CRC32_FAIL 1 134 #define CRC32_OK 0 135 136 #define evm_rssi_th_high 25 137 #define evm_rssi_th_low 20 138 139 #define NORMAL_STATE_MIAN 1 140 #define NORMAL_STATE_AUX 2 141 #define TRAINING_STATE 3 142 143 #define FORCE_RSSI_DIFF 10 144 145 #define HT_IDX 16 146 #define VHT_IDX 20 147 148 #define CSI_ON 1 149 #define CSI_OFF 0 150 151 #define DIVON_CSIOFF 1 152 #define DIVOFF_CSION 2 153 154 #define BDC_DIV_TRAIN_STATE 0 155 #define bdc_bfer_train_state 1 156 #define BDC_DECISION_STATE 2 157 #define BDC_BF_HOLD_STATE 3 158 #define BDC_DIV_HOLD_STATE 4 159 160 #define BDC_MODE_1 1 161 #define BDC_MODE_2 2 162 #define BDC_MODE_3 3 163 #define BDC_MODE_4 4 164 #define BDC_MODE_NULL 0xff 165 166 /*SW S0S1 antenna diversity*/ 167 #define SWAW_STEP_INIT 0xff 168 #define SWAW_STEP_PEEK 0 169 #define SWAW_STEP_DETERMINE 1 170 171 #define RSSI_CHECK_RESET_PERIOD 10 172 #define RSSI_CHECK_THRESHOLD 50 173 174 /*@Hong Lin Smart antenna*/ 175 #define HL_SMTANT_2WIRE_DATA_LEN 24 176 177 #if (RTL8723D_SUPPORT == 1 || RTL8710C_SUPPORT == 1) 178 #ifndef CONFIG_ANTDIV_PERIOD 179 #define CONFIG_ANTDIV_PERIOD 1 180 #endif 181 #endif 182 /* @1 ============================================================ 183 * 1 structure 184 * 1 ============================================================ 185 */ 186 187 188 struct sw_antenna_switch { 189 u8 double_chk_flag; 190 /*@If current antenna RSSI > "RSSI_CHECK_THRESHOLD", than*/ 191 /*@check this antenna again*/ 192 u8 try_flag; 193 s32 pre_rssi; 194 u8 cur_antenna; 195 u8 pre_ant; 196 u8 rssi_trying; 197 u8 reset_idx; 198 u8 train_time; 199 u8 train_time_flag; 200 /*@base on RSSI difference between two antennas*/ 201 struct phydm_timer_list sw_antdiv_timer; 202 u32 pkt_cnt_sw_ant_div_by_ctrl_frame; 203 boolean is_sw_ant_div_by_ctrl_frame; 204 205 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 206 #if USE_WORKITEM 207 RT_WORK_ITEM phydm_sw_antenna_switch_workitem; 208 #endif 209 #endif 210 211 /* @AntDect (Before link Antenna Switch check) need to be moved*/ 212 u16 single_ant_counter; 213 u16 dual_ant_counter; 214 u16 aux_fail_detec_counter; 215 u16 retry_counter; 216 u8 swas_no_link_state; 217 u32 swas_no_link_bk_reg948; 218 boolean ANTA_ON; /*To indicate ant A is or not*/ 219 boolean ANTB_ON; /*@To indicate ant B is on or not*/ 220 boolean pre_aux_fail_detec; 221 boolean rssi_ant_dect_result; 222 u8 ant_5g; 223 u8 ant_2g; 224 }; 225 226 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) 227 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) 228 struct _BF_DIV_COEX_ { 229 boolean w_bfer_client[ODM_ASSOCIATE_ENTRY_NUM]; 230 boolean w_bfee_client[ODM_ASSOCIATE_ENTRY_NUM]; 231 u32 MA_rx_TP[ODM_ASSOCIATE_ENTRY_NUM]; 232 u32 MA_rx_TP_DIV[ODM_ASSOCIATE_ENTRY_NUM]; 233 234 u8 bd_ccoex_type_wbfer; 235 u8 num_txbfee_client; 236 u8 num_txbfer_client; 237 u8 bdc_try_counter; 238 u8 bdc_hold_counter; 239 u8 bdc_mode; 240 u8 bdc_active_mode; 241 u8 BDC_state; 242 u8 bdc_rx_idle_update_counter; 243 u8 num_client; 244 u8 pre_num_client; 245 u8 num_bf_tar; 246 u8 num_div_tar; 247 248 boolean is_all_div_sta_idle; 249 boolean is_all_bf_sta_idle; 250 boolean bdc_try_flag; 251 boolean BF_pass; 252 boolean DIV_pass; 253 }; 254 #endif 255 #endif 256 257 struct phydm_fat_struct { 258 u8 bssid[6]; 259 u8 antsel_rx_keep_0; 260 u8 antsel_rx_keep_1; 261 u8 antsel_rx_keep_2; 262 u8 antsel_rx_keep_3; 263 u32 ant_sum_rssi[7]; 264 u32 ant_rssi_cnt[7]; 265 u32 ant_ave_rssi[7]; 266 u8 fat_state; 267 u8 fat_state_cnt; 268 u32 train_idx; 269 u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM]; 270 u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM]; 271 u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM]; 272 u16 main_ht_cnt[HT_IDX]; 273 u16 aux_ht_cnt[HT_IDX]; 274 u16 main_vht_cnt[VHT_IDX]; 275 u16 aux_vht_cnt[VHT_IDX]; 276 u16 main_sum[ODM_ASSOCIATE_ENTRY_NUM]; 277 u16 aux_sum[ODM_ASSOCIATE_ENTRY_NUM]; 278 u16 main_cnt[ODM_ASSOCIATE_ENTRY_NUM]; 279 u16 aux_cnt[ODM_ASSOCIATE_ENTRY_NUM]; 280 u16 main_sum_cck[ODM_ASSOCIATE_ENTRY_NUM]; 281 u16 aux_sum_cck[ODM_ASSOCIATE_ENTRY_NUM]; 282 u16 main_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM]; 283 u16 aux_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM]; 284 u8 rx_idle_ant; 285 u8 rx_idle_ant2; 286 u32 rvrt_val; /*all rvrt_val for pause API must set to u32*/ 287 u8 ant_div_on_off; 288 u8 div_path_type; 289 boolean is_become_linked; 290 boolean get_stats; 291 u32 min_max_rssi; 292 u8 idx_ant_div_counter_2g; 293 u8 idx_ant_div_counter_5g; 294 u8 ant_div_2g_5g; 295 296 #ifdef ODM_EVM_ENHANCE_ANTDIV 297 /*@For 1SS RX phy rate*/ 298 u32 main_evm_sum[ODM_ASSOCIATE_ENTRY_NUM]; 299 u32 aux_evm_sum[ODM_ASSOCIATE_ENTRY_NUM]; 300 u32 main_evm_cnt[ODM_ASSOCIATE_ENTRY_NUM]; 301 u32 aux_evm_cnt[ODM_ASSOCIATE_ENTRY_NUM]; 302 303 /*@For 2SS RX phy rate*/ 304 u32 main_evm_2ss_sum[ODM_ASSOCIATE_ENTRY_NUM][2];/*@2SS with A1+B*/ 305 u32 aux_evm_2ss_sum[ODM_ASSOCIATE_ENTRY_NUM][2];/*@2SS with A2+B*/ 306 u32 main_evm_2ss_cnt[ODM_ASSOCIATE_ENTRY_NUM]; 307 u32 aux_evm_2ss_cnt[ODM_ASSOCIATE_ENTRY_NUM]; 308 309 boolean evm_method_enable; 310 u8 target_ant_evm; 311 u8 target_ant_crc32; 312 u8 target_ant_tp; 313 u8 target_ant_enhance; 314 u8 pre_target_ant_enhance; 315 u16 main_mpdu_ok_cnt; 316 u16 aux_mpdu_ok_cnt; 317 318 u32 crc32_ok_cnt; 319 u32 crc32_fail_cnt; 320 u32 main_crc32_ok_cnt; 321 u32 aux_crc32_ok_cnt; 322 u32 main_crc32_fail_cnt; 323 u32 aux_crc32_fail_cnt; 324 325 u32 main_tp; 326 u32 aux_tp; 327 u32 main_tp_cnt; 328 u32 aux_tp_cnt; 329 330 u8 pre_antdiv_rssi; 331 u8 pre_antdiv_tp; 332 #endif 333 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT)) 334 u32 cck_ctrl_frame_cnt_main; 335 u32 cck_ctrl_frame_cnt_aux; 336 u32 ofdm_ctrl_frame_cnt_main; 337 u32 ofdm_ctrl_frame_cnt_aux; 338 u32 main_ctrl_sum; 339 u32 aux_ctrl_sum; 340 u32 main_ctrl_cnt; 341 u32 aux_ctrl_cnt; 342 #endif 343 344 u8 b_fix_tx_ant; 345 boolean fix_ant_bfee; 346 boolean enable_ctrl_frame_antdiv; 347 boolean use_ctrl_frame_antdiv; 348 boolean *is_no_csi_feedback; 349 boolean force_antdiv_type; 350 u8 antdiv_type_dbg; 351 u8 hw_antsw_occur; 352 u8 *p_force_tx_by_desc; 353 u8 force_tx_by_desc; 354 /*@A temp value, will hook to driver team's outer parameter later*/ 355 u8 *p_default_s0_s1; 356 u8 default_s0_s1; 357 u8 ant_idx_vec[3]; /* for SP3T only, added by Jiao Qi on June.6,2020*/ 358 359 360 }; 361 362 /* @1 ============================================================ 363 * 1 enumeration 364 * 1 ============================================================ 365 */ 366 367 enum fat_state /*@Fast antenna training*/ 368 { 369 FAT_BEFORE_LINK_STATE = 0, 370 FAT_PREPARE_STATE = 1, 371 FAT_TRAINING_STATE = 2, 372 FAT_DECISION_STATE = 3 373 }; 374 375 enum ant_div_type { 376 NO_ANTDIV = 0xFF, 377 CG_TRX_HW_ANTDIV = 0x01, 378 CGCS_RX_HW_ANTDIV = 0x02, 379 FIXED_HW_ANTDIV = 0x03, 380 CG_TRX_SMART_ANTDIV = 0x04, 381 CGCS_RX_SW_ANTDIV = 0x05, 382 S0S1_SW_ANTDIV = 0x06, /*@8723B intrnal switch S0 S1*/ 383 S0S1_TRX_HW_ANTDIV = 0x07, /*TRX S0S1 diversity for 8723D*/ 384 HL_SW_SMART_ANT_TYPE1 = 0x10, 385 /*@Hong-Lin Smart antenna use for 8821AE which is a 2 ant. entitys,*/ 386 /*@and each ant. is equipped with 4 antenna patterns*/ 387 HL_SW_SMART_ANT_TYPE2 = 0x11 388 /*@Hong-Bo Smart antenna use for 8822B which is a 2 ant. entitys*/ 389 }; 390 391 /* @1 ============================================================ 392 * 1 function prototype 393 * 1 ============================================================ 394 */ 395 396 void odm_stop_antenna_switch_dm(void *dm_void); 397 398 void phydm_enable_antenna_diversity(void *dm_void); 399 400 void odm_set_ant_config(void *dm_void, u8 ant_setting /* @0=A, 1=B, 2=C,....*/ 401 ); 402 403 #define sw_ant_div_rest_after_link odm_sw_ant_div_rest_after_link 404 405 void odm_sw_ant_div_rest_after_link(void *dm_void); 406 407 void odm_ant_div_on_off(void *dm_void, u8 swch, u8 path); 408 409 void odm_tx_by_tx_desc_or_reg(void *dm_void, u8 swch); 410 411 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) 412 413 void phydm_antdiv_reset_statistic(void *dm_void, u32 macid); 414 415 void odm_update_rx_idle_ant(void *dm_void, u8 ant); 416 417 void odm_update_rx_idle_ant_sp3t(void *dm_void, u8 ant); 418 419 void phydm_update_rx_idle_ant_pathb(void *dm_void, u8 ant); 420 421 void phydm_set_antdiv_val(void *dm_void, u32 *val_buf, u8 val_len); 422 423 #if (RTL8723B_SUPPORT == 1) 424 void odm_update_rx_idle_ant_8723b(void *dm_void, u8 ant, u32 default_ant, 425 u32 optional_ant); 426 #endif 427 428 #if (RTL8188F_SUPPORT == 1) 429 void phydm_update_rx_idle_antenna_8188F(void *dm_void, u32 default_ant); 430 #endif 431 432 #if (RTL8723D_SUPPORT == 1) 433 434 void phydm_set_tx_ant_pwr_8723d(void *dm_void, u8 ant); 435 436 void odm_update_rx_idle_ant_8723d(void *dm_void, u8 ant, u32 default_ant, 437 u32 optional_ant); 438 439 #endif 440 441 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY 442 443 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 444 void odm_sw_antdiv_callback(struct phydm_timer_list *timer); 445 446 void odm_sw_antdiv_workitem_callback(void *context); 447 448 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) 449 450 void odm_sw_antdiv_workitem_callback(void *context); 451 452 void odm_sw_antdiv_callback(void *function_context); 453 454 #elif (DM_ODM_SUPPORT_TYPE == ODM_IOT) 455 456 void odm_sw_antdiv_callback(void *dm_void); 457 458 #endif 459 460 void odm_s0s1_sw_ant_div_by_ctrl_frame(void *dm_void, u8 step); 461 462 void odm_antsel_statistics_ctrl(void *dm_void, u8 antsel_tr_mux, 463 u32 rx_pwdb_all); 464 465 void odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(void *dm_void, 466 void *phy_info_void, 467 void *pkt_info_void); 468 469 #endif 470 471 #ifdef ODM_EVM_ENHANCE_ANTDIV 472 void phydm_evm_sw_antdiv_init(void *dm_void); 473 474 void phydm_rx_rate_for_antdiv(void *dm_void, void *pkt_info_void); 475 476 void phydm_antdiv_reset_rx_rate(void *dm_void); 477 478 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 479 void phydm_evm_antdiv_callback(struct phydm_timer_list *timer); 480 481 void phydm_evm_antdiv_workitem_callback(void *context); 482 483 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) 484 void phydm_evm_antdiv_callback(void *dm_void); 485 486 void phydm_evm_antdiv_workitem_callback(void *context); 487 488 #else 489 void phydm_evm_antdiv_callback(void *dm_void); 490 #endif 491 492 #endif 493 494 void odm_hw_ant_div(void *dm_void); 495 496 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) ||\ 497 (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) 498 void odm_fast_ant_training( 499 void *dm_void); 500 501 void odm_fast_ant_training_callback(void *dm_void); 502 503 void odm_fast_ant_training_work_item_callback(void *dm_void); 504 #endif 505 506 void odm_ant_div_init(void *dm_void); 507 508 void odm_ant_div(void *dm_void); 509 510 void odm_antsel_statistics(void *dm_void, void *phy_info_void, 511 u8 antsel_tr_mux, u32 mac_id, u32 utility, u8 method, 512 u8 is_cck_rate); 513 514 void odm_process_rssi_for_ant_div(void *dm_void, void *phy_info_void, 515 void *pkt_info_void); 516 517 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) 518 void odm_set_tx_ant_by_tx_info(void *dm_void, u8 *desc, u8 mac_id); 519 520 #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) 521 522 struct tx_desc; 523 /*@declared tx_desc here or compile error happened when enabled 8822B*/ 524 525 void odm_set_tx_ant_by_tx_info(struct rtl8192cd_priv *priv, 526 struct tx_desc *pdesc, unsigned short aid); 527 528 #if 1 /*@def def CONFIG_WLAN_HAL*/ 529 void odm_set_tx_ant_by_tx_info_hal(struct rtl8192cd_priv *priv, 530 void *pdesc_data, u16 aid); 531 #endif /*@#ifdef CONFIG_WLAN_HAL*/ 532 #endif 533 534 void odm_ant_div_config(void *dm_void); 535 536 void odm_ant_div_timers(void *dm_void, u8 state); 537 538 void phydm_antdiv_debug(void *dm_void, char input[][16], u32 *_used, 539 char *output, u32 *_out_len); 540 541 void odm_ant_div_reset(void *dm_void); 542 543 void odm_antenna_diversity_init(void *dm_void); 544 545 void odm_antenna_diversity(void *dm_void); 546 #endif /*@#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY*/ 547 #endif /*@#ifndef __ODMANTDIV_H__*/ 548