1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /*@************************************************************
27 * include files
28 ************************************************************/
29
30 #include "mp_precomp.h"
31 #include "phydm_precomp.h"
32
33 #ifdef PHYDM_MP_SUPPORT
34 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
35
phydm_mp_set_single_tone_jgr3(void * dm_void,boolean is_single_tone,u8 path)36 void phydm_mp_set_single_tone_jgr3(void *dm_void, boolean is_single_tone,
37 u8 path)
38 {
39 struct dm_struct *dm = (struct dm_struct *)dm_void;
40 struct phydm_mp *mp = &dm->dm_mp_table;
41 u8 start = RF_PATH_A, end = RF_PATH_A;
42 u8 i = 0;
43 u8 central_ch = 0;
44 boolean is_2g_ch = false;
45
46 switch (path) {
47 case RF_PATH_A:
48 case RF_PATH_B:
49 case RF_PATH_C:
50 case RF_PATH_D:
51 start = path;
52 end = path;
53 break;
54 case RF_PATH_AB:
55 start = RF_PATH_A;
56 end = RF_PATH_B;
57 break;
58 #if (defined(PHYDM_COMPILE_IC_4SS))
59 case RF_PATH_AC:
60 start = RF_PATH_A;
61 end = RF_PATH_C;
62 break;
63 case RF_PATH_AD:
64 start = RF_PATH_A;
65 end = RF_PATH_D;
66 break;
67 case RF_PATH_BC:
68 start = RF_PATH_B;
69 end = RF_PATH_C;
70 break;
71 case RF_PATH_BD:
72 start = RF_PATH_B;
73 end = RF_PATH_D;
74 break;
75 case RF_PATH_CD:
76 start = RF_PATH_C;
77 end = RF_PATH_D;
78 break;
79 case RF_PATH_ABC:
80 start = RF_PATH_A;
81 end = RF_PATH_C;
82 break;
83 case RF_PATH_ABD:
84 start = RF_PATH_A;
85 end = RF_PATH_D;
86 break;
87 case RF_PATH_ACD:
88 start = RF_PATH_A;
89 end = RF_PATH_D;
90 break;
91 case RF_PATH_BCD:
92 start = RF_PATH_B;
93 end = RF_PATH_D;
94 break;
95 case RF_PATH_ABCD:
96 start = RF_PATH_A;
97 end = RF_PATH_D;
98 break;
99 #endif
100 }
101
102 central_ch = (u8)odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, 0xff);
103 is_2g_ch = (central_ch <= 14) ? true : false;
104
105 if (is_single_tone) {
106 /*Disable CCA*/
107 if (is_2g_ch) { /*CCK RxIQ weighting = [0,0]*/
108 if(!(dm->support_ic_type & ODM_RTL8723F)) {
109 odm_set_bb_reg(dm, R_0x1a9c, BIT(20), 0x0);
110 odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x3);
111 }
112 }
113 /*Disable CCK CCA*/
114 if(dm->support_ic_type & ODM_RTL8723F)
115 odm_set_bb_reg(dm, R_0x2a24, BIT(13), 0x1);
116 /*Disable OFDM CCA*/
117 odm_set_bb_reg(dm, R_0x1d58, 0xff8, 0x1ff);
118
119 if (dm->support_ic_type & ODM_RTL8723F) {
120 for (i = start; i <= end; i++) {
121 odm_set_rf_reg(dm, i, RF_0x5, BIT(0), 0x0);
122 mp->rf0[i] = odm_get_rf_reg(dm, i, RF_0x0, RFREG_MASK);
123 /*Tx mode: RF0x00[19:16]=4'b0010 */
124 odm_set_rf_reg(dm, i, RF_0x0, 0xF0000, 0x2);
125 /*Lowest RF gain index: RF_0x1[5:0] TX power*/
126 mp->rf1[i] = odm_get_rf_reg(dm, i, RF_0x1, RFREG_MASK);
127 odm_set_rf_reg(dm, i, RF_0x1, 0x3f, 0x0);//TX power
128 /*RF LO enabled */
129 odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x1);
130 }
131 } else {
132 for (i = start; i <= end; i++) {
133 mp->rf0[i] = odm_get_rf_reg(dm, i, RF_0x0, RFREG_MASK);
134 /*Tx mode: RF0x00[19:16]=4'b0010 */
135 odm_set_rf_reg(dm, i, RF_0x0, 0xF0000, 0x2);
136 /*Lowest RF gain index: RF_0x0[4:0] = 0*/
137 odm_set_rf_reg(dm, i, RF_0x0, 0x1f, 0x0);
138 /*RF LO enabled */
139 odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x1);
140 }
141 }
142
143 #if (RTL8814B_SUPPORT)
144 if (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8814C)) {
145 mp->rf0_syn[RF_SYN0] = config_phydm_read_syn_reg_8814b(
146 dm, RF_SYN0, RF_0x0, RFREG_MASK);
147 /*Lowest RF gain index: RF_0x0[4:0] = 0x0*/
148 config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x0,
149 0x1f, 0x0);
150 /*RF LO enabled */
151 config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x58,
152 BIT(1), 0x1);
153 /*SYN1*/
154 if (*dm->band_width == CHANNEL_WIDTH_80_80) {
155 mp->rf0_syn[RF_SYN1] = config_phydm_read_syn_reg_8814b(
156 dm, RF_SYN1, RF_0x0,
157 RFREG_MASK);
158 config_phydm_write_rf_syn_8814b(dm, RF_SYN1,
159 RF_0x0, 0x1f,
160 0x0);
161 config_phydm_write_rf_syn_8814b(dm, RF_SYN1,
162 RF_0x58, BIT(1),
163 0x1);
164 }
165 }
166 #endif
167 } else {
168 /*Enable CCA*/
169 if (is_2g_ch) { /*CCK RxIQ weighting = [1,1]*/
170 if(!(dm->support_ic_type & ODM_RTL8723F)) {
171 odm_set_bb_reg(dm, R_0x1a9c, BIT(20), 0x1);
172 odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x0);
173 }
174 }
175 /*Enable CCK CCA*/
176 if(dm->support_ic_type & ODM_RTL8723F)
177 odm_set_bb_reg(dm, R_0x2a24, BIT(13), 0x0);
178 /*Enable OFDM CCA*/
179 odm_set_bb_reg(dm, R_0x1d58, 0xff8, 0x0);
180
181 if(dm->support_ic_type & ODM_RTL8723F) {
182 for (i = start; i <= end; i++) {
183 odm_set_rf_reg(dm, i, RF_0x0, RFREG_MASK, mp->rf0[i]);
184 odm_set_rf_reg(dm, i, RF_0x1, RFREG_MASK, mp->rf1[i]);
185 /*RF LO disabled */
186 odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x0);
187 odm_set_rf_reg(dm, i, RF_0x5, BIT(0), 0x1);
188 }
189 } else {
190 for (i = start; i <= end; i++) {
191 odm_set_rf_reg(dm, i, RF_0x0, RFREG_MASK, mp->rf0[i]);
192 /*RF LO disabled */
193 odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x0);
194 }
195 }
196 #if (RTL8814B_SUPPORT)
197 if (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8814C)) {
198 config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x0,
199 RFREG_MASK,
200 mp->rf0_syn[RF_SYN0]);
201 config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x58,
202 BIT(1), 0x0);
203 /*SYN1*/
204 if (*dm->band_width == CHANNEL_WIDTH_80_80) {
205 config_phydm_write_rf_syn_8814b(dm, RF_SYN1,
206 RF_0x0,
207 RFREG_MASK,
208 mp->rf0_syn[RF_SYN1]);
209 config_phydm_write_rf_syn_8814b(dm, RF_SYN1,
210 RF_0x58, BIT(1),
211 0x0);
212 }
213 }
214 #endif
215 }
216 }
217
phydm_mp_set_carrier_supp_jgr3(void * dm_void,boolean is_carrier_supp,u32 rate_index)218 void phydm_mp_set_carrier_supp_jgr3(void *dm_void, boolean is_carrier_supp,
219 u32 rate_index)
220 {
221 struct dm_struct *dm = (struct dm_struct *)dm_void;
222 struct phydm_mp *mp = &dm->dm_mp_table;
223
224 if (is_carrier_supp) {
225 if (phydm_is_cck_rate(dm, (u8)rate_index)) {
226 /*if CCK block on? */
227 if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(1)))
228 odm_set_bb_reg(dm, R_0x1c3c, BIT(1), 1);
229
230 if(dm->support_ic_type & ODM_RTL8723F){
231 /* @Carrier suppress tx */
232 odm_set_bb_reg(dm, R_0x2a08, BIT(18), 0x1);
233 /*turn off scramble setting */
234 odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0x1);
235 /*Set CCK Tx Test Rate, set TxRate to 2Mbps */
236 odm_set_bb_reg(dm, R_0x2a08, 0x300000, 0x1);
237 /* BB and PMAC cont tx */
238 odm_set_bb_reg(dm, R_0x2a08, BIT(17), 0x1);
239 odm_set_bb_reg(dm, R_0x2a00, BIT(28), 0x1);
240 /* TX CCK ON */
241 odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x0);
242 odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x1);
243 }
244 else {
245 /*Turn Off All Test mode */
246 odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x0);
247
248 /*transmit mode */
249 odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x2);
250 /*turn off scramble setting */
251 odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x0);
252 /*Set CCK Tx Test Rate, set TxRate to 1Mbps */
253 odm_set_bb_reg(dm, R_0x1a00, 0x3000, 0x0);
254 }
255 }
256 } else { /*Stop Carrier Suppression. */
257 if (phydm_is_cck_rate(dm, (u8)rate_index)) {
258 if(dm->support_ic_type & ODM_RTL8723F) {
259 /* TX Stop */
260 odm_set_bb_reg(dm, R_0x2a00, BIT(0), 0x1);
261 /* Clear BB cont tx */
262 odm_set_bb_reg(dm, R_0x2a00, BIT(28), 0x0);
263 /* Clear PMAC cont tx */
264 odm_set_bb_reg(dm, R_0x2a08, BIT(17), 0x0);
265 /* Clear TX Stop */
266 odm_set_bb_reg(dm, R_0x2a00, BIT(0), 0x0);
267 /* normal mode */
268 odm_set_bb_reg(dm, R_0x2a08, BIT(18), 0x0);
269 /* turn on scramble setting */
270 odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0x0);
271 }
272 else {
273 /*normal mode */
274 odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x0);
275 /*turn on scramble setting */
276 odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x1);
277 }
278 /*BB Reset */
279 odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x0);
280 odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x1);
281 }
282 }
283 }
284
phydm_mp_set_single_carrier_jgr3(void * dm_void,boolean is_single_carrier)285 void phydm_mp_set_single_carrier_jgr3(void *dm_void, boolean is_single_carrier)
286 {
287 struct dm_struct *dm = (struct dm_struct *)dm_void;
288 struct phydm_mp *mp = &dm->dm_mp_table;
289
290 if (is_single_carrier) {
291 /*1. if OFDM block on? */
292 if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(0)))
293 odm_set_bb_reg(dm, R_0x1c3c, BIT(0), 1);
294
295 if (dm->support_ic_type & ODM_RTL8723F) {
296 /*3. turn on scramble setting */
297 odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0);
298 /*4. Turn On single carrier. */
299 odm_set_bb_reg(dm, R_0x1ca4, 0x7, OFDM_SINGLE_CARRIER);
300 }
301 else {
302 /*2. set CCK test mode off, set to CCK normal mode */
303 odm_set_bb_reg(dm, R_0x1a00, 0x3, 0);
304 /*3. turn on scramble setting */
305 odm_set_bb_reg(dm, R_0x1a00, BIT(3), 1);
306 /*4. Turn On single carrier. */
307 odm_set_bb_reg(dm, R_0x1ca4, 0x7, OFDM_SINGLE_CARRIER);
308 }
309 } else {
310 /*Turn off all test modes. */
311 odm_set_bb_reg(dm, R_0x1ca4, 0x7, OFDM_OFF);
312
313 /*Delay 10 ms */
314 ODM_delay_ms(10);
315
316 /*BB Reset*/
317 odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x0);
318 odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x1);
319 }
320 }
321
phydm_mp_get_tx_ok_jgr3(void * dm_void,u32 rate_index)322 void phydm_mp_get_tx_ok_jgr3(void *dm_void, u32 rate_index)
323 {
324 struct dm_struct *dm = (struct dm_struct *)dm_void;
325 struct phydm_mp *mp = &dm->dm_mp_table;
326
327 if (phydm_is_cck_rate(dm, (u8)rate_index))
328 mp->tx_phy_ok_cnt = odm_get_bb_reg(dm, R_0x2de4, MASKLWORD);
329 else
330 mp->tx_phy_ok_cnt = odm_get_bb_reg(dm, R_0x2de0, MASKLWORD);
331 }
332
phydm_mp_get_rx_ok_jgr3(void * dm_void)333 void phydm_mp_get_rx_ok_jgr3(void *dm_void)
334 {
335 struct dm_struct *dm = (struct dm_struct *)dm_void;
336 struct phydm_mp *mp = &dm->dm_mp_table;
337
338 u32 cck_ok = 0, ofdm_ok = 0, ht_ok = 0, vht_ok = 0;
339 u32 cck_err = 0, ofdm_err = 0, ht_err = 0, vht_err = 0;
340 if(dm->support_ic_type & ODM_RTL8723F)
341 cck_ok = odm_get_bb_reg(dm, R_0x2aac, MASKLWORD);
342 else
343 cck_ok = odm_get_bb_reg(dm, R_0x2c04, MASKLWORD);
344 ofdm_ok = odm_get_bb_reg(dm, R_0x2c14, MASKLWORD);
345 ht_ok = odm_get_bb_reg(dm, R_0x2c10, MASKLWORD);
346 vht_ok = odm_get_bb_reg(dm, R_0x2c0c, MASKLWORD);
347 if(dm->support_ic_type & ODM_RTL8723F)
348 cck_err = odm_get_bb_reg(dm, R_0x2aac, MASKHWORD);
349 else
350 cck_err = odm_get_bb_reg(dm, R_0x2c04, MASKHWORD);
351 ofdm_err = odm_get_bb_reg(dm, R_0x2c14, MASKHWORD);
352 ht_err = odm_get_bb_reg(dm, R_0x2c10, MASKHWORD);
353 vht_err = odm_get_bb_reg(dm, R_0x2c0c, MASKHWORD);
354
355 mp->rx_phy_ok_cnt = cck_ok + ofdm_ok + ht_ok + vht_ok;
356 mp->rx_phy_crc_err_cnt = cck_err + ofdm_err + ht_err + vht_err;
357 mp->io_value = (u32)mp->rx_phy_ok_cnt;
358 }
359 #endif
phydm_mp_set_crystal_cap(void * dm_void,u8 crystal_cap)360 void phydm_mp_set_crystal_cap(void *dm_void, u8 crystal_cap)
361 {
362 struct dm_struct *dm = (struct dm_struct *)dm_void;
363
364 phydm_set_crystal_cap(dm, crystal_cap);
365 }
366
phydm_mp_set_single_tone(void * dm_void,boolean is_single_tone,u8 path)367 void phydm_mp_set_single_tone(void *dm_void, boolean is_single_tone, u8 path)
368 {
369 struct dm_struct *dm = (struct dm_struct *)dm_void;
370
371 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
372 phydm_mp_set_single_tone_jgr3(dm, is_single_tone, path);
373 }
374
phydm_mp_set_carrier_supp(void * dm_void,boolean is_carrier_supp,u32 rate_index)375 void phydm_mp_set_carrier_supp(void *dm_void, boolean is_carrier_supp,
376 u32 rate_index)
377 {
378 struct dm_struct *dm = (struct dm_struct *)dm_void;
379
380 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
381 phydm_mp_set_carrier_supp_jgr3(dm, is_carrier_supp, rate_index);
382 }
383
phydm_mp_set_single_carrier(void * dm_void,boolean is_single_carrier)384 void phydm_mp_set_single_carrier(void *dm_void, boolean is_single_carrier)
385 {
386 struct dm_struct *dm = (struct dm_struct *)dm_void;
387
388 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
389 phydm_mp_set_single_carrier_jgr3(dm, is_single_carrier);
390 }
phydm_mp_reset_rx_counters_phy(void * dm_void)391 void phydm_mp_reset_rx_counters_phy(void *dm_void)
392 {
393 struct dm_struct *dm = (struct dm_struct *)dm_void;
394
395 phydm_reset_bb_hw_cnt(dm);
396 }
397
phydm_mp_get_tx_ok(void * dm_void,u32 rate_index)398 void phydm_mp_get_tx_ok(void *dm_void, u32 rate_index)
399 {
400 struct dm_struct *dm = (struct dm_struct *)dm_void;
401
402 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
403 phydm_mp_get_tx_ok_jgr3(dm, rate_index);
404 }
405
phydm_mp_get_rx_ok(void * dm_void)406 void phydm_mp_get_rx_ok(void *dm_void)
407 {
408 struct dm_struct *dm = (struct dm_struct *)dm_void;
409
410 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
411 phydm_mp_get_rx_ok_jgr3(dm);
412 }
413 #endif
414