1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /******************************************************************************
27 * include files
28 *****************************************************************************/
29 #include "mp_precomp.h"
30 #include "phydm_precomp.h"
31
32 #ifdef CONFIG_PSD_TOOL
phydm_get_psd_data(void * dm_void,u32 psd_tone_idx,u32 igi)33 u32 phydm_get_psd_data(void *dm_void, u32 psd_tone_idx, u32 igi)
34 {
35 struct dm_struct *dm = (struct dm_struct *)dm_void;
36 struct psd_info *dm_psd_table = &dm->dm_psd_table;
37 u32 psd_report = 0;
38
39 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
40 #if(RTL8723F_SUPPORT)
41 if (dm->support_ic_type & (ODM_RTL8723F)) {
42 odm_set_bb_reg(dm, dm_psd_table->psd_reg, 0x3ff80000, psd_tone_idx & 0x7ff);
43 /*PSD trigger start*/
44 odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(16), 1);
45 ODM_delay_us(10 << (dm_psd_table->fft_smp_point >> 7));
46 /*PSD trigger stop*/
47 odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(16), 0);
48 }
49 #endif
50 #if 0
51 odm_set_bb_reg(dm, R_0x1e8c, 0x3ff, psd_tone_idx & 0x3ff);
52 odm_set_bb_reg(dm, R_0x1e88, BIT(27) | BIT(26),
53 psd_tone_idx >> 10);
54 /*PSD trigger start*/
55 odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(18), 1);
56 ODM_delay_us(10 << (dm_psd_table->fft_smp_point >> 7));
57 /*PSD trigger stop*/
58 odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(18), 0);
59 #endif
60 } else if (dm->support_ic_type & (ODM_RTL8721D |
61 ODM_RTL8710C)) {
62 odm_set_bb_reg(dm, dm_psd_table->psd_reg, 0xfff, psd_tone_idx);
63 odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(28), 1);
64 /*PSD trigger start*/
65 ODM_delay_us(10 << (dm_psd_table->fft_smp_point >> 7));
66 odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(28), 0);
67 /*PSD trigger stop*/
68 } else {
69 odm_set_bb_reg(dm, dm_psd_table->psd_reg, 0x3ff, psd_tone_idx);
70 /*PSD trigger start*/
71 odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(22), 1);
72 ODM_delay_us(10 << (dm_psd_table->fft_smp_point >> 7));
73 /*PSD trigger stop*/
74 odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(22), 0);
75 }
76
77 /*Get PSD Report*/
78 if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8721D |
79 ODM_RTL8710C)) {
80 psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg,
81 0xffffff);
82 psd_report = psd_report >> 5;
83 } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
84 #if(RTL8723F_SUPPORT)
85 if (dm->support_ic_type & (ODM_RTL8723F)) {
86 psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg,
87 0x1ffffff);
88 }
89 #endif
90 #if 0
91 psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg,
92 0xffffff);
93 #endif
94 } else {
95 psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg,
96 0xffff);
97 }
98 psd_report = odm_convert_to_db((u64)psd_report) + igi;
99
100 return psd_report;
101 }
102
103 u8 psd_result_cali_tone_8821[7] = {21, 28, 33, 93, 98, 105, 127};
104 u8 psd_result_cali_val_8821[7] = {67, 69, 71, 72, 71, 69, 67};
105
phydm_psd(void * dm_void,u32 igi,u16 start_point,u16 stop_point)106 u8 phydm_psd(void *dm_void, u32 igi, u16 start_point, u16 stop_point)
107 {
108 struct dm_struct *dm = (struct dm_struct *)dm_void;
109 struct psd_info *dm_psd_table = &dm->dm_psd_table;
110 u32 i = 0, mod_tone_idx = 0;
111 u32 t = 0;
112 u16 fft_max_half_bw = 0;
113 u16 psd_fc_channel = dm_psd_table->psd_fc_channel;
114 u8 ag_rf_mode_reg = 0;
115 u8 is_5G = 0;
116 u32 psd_result_tmp = 0;
117 u8 psd_result = 0;
118 u8 psd_result_cali_tone[7] = {0};
119 u8 psd_result_cali_val[7] = {0};
120 u8 noise_idx = 0;
121 u8 set_result = 0;
122 u32 igi_tmp = 0x6e;
123
124 if (dm->support_ic_type == ODM_RTL8821) {
125 odm_move_memory(dm, psd_result_cali_tone,
126 psd_result_cali_tone_8821, 7);
127 odm_move_memory(dm, psd_result_cali_val,
128 psd_result_cali_val_8821, 7);
129 }
130
131 dm_psd_table->psd_in_progress = 1;
132
133 PHYDM_DBG(dm, ODM_COMP_API, "PSD Start =>\n");
134
135 /* @[Stop DIG]*/
136 /* @IGI target at 0dBm & make it can't CCA*/
137 if (phydm_pause_func(dm, F00_DIG, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_3, 1,
138 &igi_tmp) == PAUSE_FAIL) {
139 return PHYDM_SET_FAIL;
140 }
141
142 ODM_delay_us(10);
143
144 if (phydm_stop_ic_trx(dm, PHYDM_SET) == PHYDM_SET_FAIL) {
145 phydm_pause_func(dm, F00_DIG, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_3,
146 1, &igi_tmp);
147 return PHYDM_SET_FAIL;
148 }
149
150 /* @[Set IGI]*/
151 phydm_write_dig_reg(dm, (u8)igi);
152
153 /* @[Backup RF Reg]*/
154 dm_psd_table->rf_0x18_bkp = odm_get_rf_reg(dm, RF_PATH_A, RF_0x18,
155 RFREG_MASK);
156 dm_psd_table->rf_0x18_bkp_b = odm_get_rf_reg(dm, RF_PATH_B, RF_0x18,
157 RFREG_MASK);
158
159 if (psd_fc_channel > 14) {
160 is_5G = 1;
161 if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F |
162 ODM_RTL8197G)) {
163 #if 0
164 if (psd_fc_channel < 80)
165 ag_rf_mode_reg = 0x1;
166 else if (psd_fc_channel >= 80 && psd_fc_channel <= 140)
167 ag_rf_mode_reg = 0x3;
168 else if (psd_fc_channel > 140)
169 ag_rf_mode_reg = 0x5;
170 #endif
171 } else if (dm->support_ic_type & ODM_RTL8723F) {
172 if (psd_fc_channel < 80)
173 ag_rf_mode_reg = 0x1;
174 else if (psd_fc_channel >= 80 && psd_fc_channel <= 144)
175 ag_rf_mode_reg = 0x5;
176 else if (psd_fc_channel > 144)
177 ag_rf_mode_reg = 0x9;
178 } else if (dm->support_ic_type == ODM_RTL8721D) {
179 if (psd_fc_channel >= 36 && psd_fc_channel <= 64)
180 ag_rf_mode_reg = 0x1;
181 else if (psd_fc_channel >= 100 && psd_fc_channel <= 140)
182 ag_rf_mode_reg = 0x5;
183 else if (psd_fc_channel > 140)
184 ag_rf_mode_reg = 0x9;
185 } else {
186 if (psd_fc_channel >= 36 && psd_fc_channel <= 64)
187 ag_rf_mode_reg = 0x1;
188 else if (psd_fc_channel >= 100 && psd_fc_channel <= 140)
189 ag_rf_mode_reg = 0x3;
190 else if (psd_fc_channel > 140)
191 ag_rf_mode_reg = 0x5;
192 }
193 }
194
195 /* Set RF fc*/
196 odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0xff, psd_fc_channel);
197 odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0xff, psd_fc_channel);
198 odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x300, is_5G);
199 odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0x300, is_5G);
200 if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F |
201 ODM_RTL8197G)) {
202 #if 0
203 /* @2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
204 odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x3000,
205 dm_psd_table->psd_bw_rf_reg);
206 odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0x3000,
207 dm_psd_table->psd_bw_rf_reg);
208 /* Set RF ag fc mode*/
209 odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x70000,
210 ag_rf_mode_reg);
211 odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0x70000,
212 ag_rf_mode_reg);
213 #endif
214 } else if (dm->support_ic_type & ODM_RTL8723F) {
215 /* @2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
216 odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x1c00,
217 dm_psd_table->psd_bw_rf_reg);
218 odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0x1c00,
219 dm_psd_table->psd_bw_rf_reg);
220 /* Set RF ag fc mode*/
221 odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x30000, 1);
222 odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0x30000, 1);
223 if(ag_rf_mode_reg == 1) {
224 odm_set_rf_reg(dm, RF_PATH_A, RF_0x19, 0xc0000, 0);
225 odm_set_rf_reg(dm, RF_PATH_B, RF_0x19, 0xc0000, 0);
226 }
227 else if(ag_rf_mode_reg == 5){
228 odm_set_rf_reg(dm, RF_PATH_A, RF_0x19, 0xc0000, 1);
229 odm_set_rf_reg(dm, RF_PATH_B, RF_0x19, 0xc0000, 1);
230 }
231 else {
232 odm_set_rf_reg(dm, RF_PATH_A, RF_0x19, 0xc0000, 2);
233 odm_set_rf_reg(dm, RF_PATH_B, RF_0x19, 0xc0000, 2);
234 }
235 } else {
236 /* @2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
237 if (dm->support_ic_type == ODM_RTL8721D) {
238 odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x1c00,
239 dm_psd_table->psd_bw_rf_reg);
240 #if (RTL8710C_SUPPORT == 1)
241 } else if (dm->support_ic_type == ODM_RTL8710C) {
242 odm_set_rf_reg(dm, RF_PATH_A,
243 RF_0x18, 0x1c00,
244 dm_psd_table->psd_bw_rf_reg);
245 #endif
246 } else {
247 odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0xc00,
248 dm_psd_table->psd_bw_rf_reg);
249 }
250 odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0xc00,
251 dm_psd_table->psd_bw_rf_reg);
252 /* Set RF ag fc mode*/
253 odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0xf0000,
254 ag_rf_mode_reg);
255 odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0xf0000,
256 ag_rf_mode_reg);
257 }
258
259 if (dm->support_ic_type & ODM_IC_JGR3_SERIES){
260 if (dm->support_ic_type & ODM_RTL8723F) {
261 PHYDM_DBG(dm, ODM_COMP_API, "0x1d70=((0x%x))\n",
262 odm_get_bb_reg(dm, R_0x1d70, MASKDWORD));
263 PHYDM_DBG(dm, ODM_COMP_API, "RF0x19=((0x%x))\n",
264 odm_get_rf_reg(dm, RF_PATH_A, RF_0x19, RFREG_MASK));
265 }
266 } else
267 PHYDM_DBG(dm, ODM_COMP_API, "0xc50=((0x%x))\n",
268 odm_get_bb_reg(dm, R_0xc50, MASKDWORD));
269
270 PHYDM_DBG(dm, ODM_COMP_API, "RF0x18=((0x%x))\n",
271 odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, RFREG_MASK));
272
273 /* @[Stop 3-wires]*/
274 phydm_stop_3_wire(dm, PHYDM_SET);
275
276 ODM_delay_us(10);
277
278 if (stop_point > (dm_psd_table->fft_smp_point - 1))
279 stop_point = (dm_psd_table->fft_smp_point - 1);
280
281 if (start_point > (dm_psd_table->fft_smp_point - 1))
282 start_point = (dm_psd_table->fft_smp_point - 1);
283
284 if (start_point > stop_point)
285 stop_point = start_point;
286
287 for (i = start_point; i <= stop_point; i++) {
288 fft_max_half_bw = (dm_psd_table->fft_smp_point) >> 1;
289
290 if (i < fft_max_half_bw)
291 mod_tone_idx = i + fft_max_half_bw;
292 else
293 mod_tone_idx = i - fft_max_half_bw;
294
295 psd_result_tmp = 0;
296 for (t = 0; t < dm_psd_table->sw_avg_time; t++)
297 psd_result_tmp += phydm_get_psd_data(dm, mod_tone_idx,
298 igi);
299 psd_result =
300 (u8)((psd_result_tmp / dm_psd_table->sw_avg_time)) -
301 dm_psd_table->psd_pwr_common_offset;
302
303 if (dm_psd_table->fft_smp_point == 128 &&
304 dm_psd_table->noise_k_en) {
305 if (i > psd_result_cali_tone[noise_idx])
306 noise_idx++;
307
308 if (noise_idx > 6)
309 noise_idx = 6;
310
311 if (psd_result >= psd_result_cali_val[noise_idx])
312 psd_result = psd_result -
313 psd_result_cali_val[noise_idx];
314 else
315 psd_result = 0;
316
317 dm_psd_table->psd_result[i] = psd_result;
318 }
319
320 PHYDM_DBG(dm, ODM_COMP_API, "[%d] N_cali = %d, PSD = %d\n",
321 mod_tone_idx, psd_result_cali_val[noise_idx],
322 psd_result);
323 }
324
325 /*@[Start 3-wires]*/
326 phydm_stop_3_wire(dm, PHYDM_REVERT);
327
328 ODM_delay_us(10);
329
330 /*@[Revert Reg]*/
331 set_result = phydm_stop_ic_trx(dm, PHYDM_REVERT);
332
333 odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, RFREG_MASK,
334 dm_psd_table->rf_0x18_bkp);
335 odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, RFREG_MASK,
336 dm_psd_table->rf_0x18_bkp_b);
337
338 PHYDM_DBG(dm, ODM_COMP_API, "PSD finished\n\n");
339
340 phydm_pause_func(dm, F00_DIG, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_3, 1,
341 &igi_tmp);
342 dm_psd_table->psd_in_progress = 0;
343
344 return PHYDM_SET_SUCCESS;
345 }
346
phydm_psd_para_setting(void * dm_void,u8 sw_avg_time,u8 hw_avg_time,u8 i_q_setting,u16 fft_smp_point,u8 ant_sel,u8 psd_input,u8 channel,u8 noise_k_en)347 void phydm_psd_para_setting(void *dm_void, u8 sw_avg_time, u8 hw_avg_time,
348 u8 i_q_setting, u16 fft_smp_point, u8 ant_sel,
349 u8 psd_input, u8 channel, u8 noise_k_en)
350 {
351 struct dm_struct *dm = (struct dm_struct *)dm_void;
352 struct psd_info *dm_psd_table = &dm->dm_psd_table;
353 u8 fft_smp_point_idx = 0;
354
355 dm_psd_table->fft_smp_point = fft_smp_point;
356
357 if (sw_avg_time == 0)
358 sw_avg_time = 1;
359
360 dm_psd_table->sw_avg_time = sw_avg_time;
361 dm_psd_table->psd_fc_channel = channel;
362 dm_psd_table->noise_k_en = noise_k_en;
363 if (dm->support_ic_type & ODM_RTL8723F) {
364 if (fft_smp_point == 128)
365 fft_smp_point_idx = 3;
366 else if (fft_smp_point == 256)
367 fft_smp_point_idx = 2;
368 else if (fft_smp_point == 512)
369 fft_smp_point_idx = 1;
370 else if (fft_smp_point == 1024)
371 fft_smp_point_idx = 0;
372 }
373 else {
374 if (fft_smp_point == 128)
375 fft_smp_point_idx = 0;
376 else if (fft_smp_point == 256)
377 fft_smp_point_idx = 1;
378 else if (fft_smp_point == 512)
379 fft_smp_point_idx = 2;
380 else if (fft_smp_point == 1024)
381 fft_smp_point_idx = 3;
382 }
383 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
384 #if (RTL8723F_SUPPORT)
385 odm_set_bb_reg(dm, R_0x1e8c, BIT(12) | BIT(11), hw_avg_time);
386 odm_set_bb_reg(dm, R_0x1e8c, BIT(14) | BIT(13),
387 fft_smp_point_idx);
388 odm_set_bb_reg(dm, R_0x1e8c, BIT(18) | BIT(17), ant_sel);
389 odm_set_bb_reg(dm, R_0x1e88, BIT(25) | BIT(24), psd_input);
390 #else
391 #if 0
392 odm_set_bb_reg(dm, R_0x1e8c, BIT(11) | BIT(10), i_q_setting);
393 odm_set_bb_reg(dm, R_0x1e8c, BIT(13) | BIT(12), hw_avg_time);
394
395 if (fft_smp_point == 4096) {
396 odm_set_bb_reg(dm, R_0x1e88, BIT(31) | BIT(30), 0x2);
397 } else if (fft_smp_point == 2048) {
398 odm_set_bb_reg(dm, R_0x1e88, BIT(31) | BIT(30), 0x1);
399 } else {
400 odm_set_bb_reg(dm, R_0x1e88, BIT(31) | BIT(30), 0x0);
401 odm_set_bb_reg(dm, R_0x1e8c, BIT(15) | BIT(14),
402 fft_smp_point_idx);
403 }
404 odm_set_bb_reg(dm, R_0x1e8c, BIT(17) | BIT(16), ant_sel);
405 odm_set_bb_reg(dm, R_0x1e8c, BIT(23) | BIT(22), psd_input);
406 #endif
407 #endif
408 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
409 odm_set_bb_reg(dm, R_0x910, BIT(11) | BIT(10), i_q_setting);
410 odm_set_bb_reg(dm, R_0x910, BIT(13) | BIT(12), hw_avg_time);
411 odm_set_bb_reg(dm, R_0x910, BIT(15) | BIT(14),
412 fft_smp_point_idx);
413 odm_set_bb_reg(dm, R_0x910, BIT(17) | BIT(16), ant_sel);
414 odm_set_bb_reg(dm, R_0x910, BIT(23), psd_input);
415 } else if (dm->support_ic_type & (ODM_RTL8721D | ODM_RTL8710C)) {
416 odm_set_bb_reg(dm, R_0x808, BIT(19) | BIT(18), i_q_setting);
417 odm_set_bb_reg(dm, R_0x808, BIT(21) | BIT(20), hw_avg_time);
418 odm_set_bb_reg(dm, R_0x808, BIT(23) | BIT(22),
419 fft_smp_point_idx);
420 odm_set_bb_reg(dm, R_0x804, BIT(5) | BIT(4), ant_sel);
421 odm_set_bb_reg(dm, R_0x80c, BIT(23), psd_input);
422
423 #if 0
424 } else { /*ODM_IC_11N_SERIES*/
425 #endif
426 }
427 /*@bw = (*dm->band_width); //ODM_BW20M */
428 /*@channel = *(dm->channel);*/
429 }
430
phydm_psd_init(void * dm_void)431 void phydm_psd_init(void *dm_void)
432 {
433 struct dm_struct *dm = (struct dm_struct *)dm_void;
434 struct psd_info *dm_psd_table = &dm->dm_psd_table;
435
436 PHYDM_DBG(dm, ODM_COMP_API, "PSD para init\n");
437
438 dm_psd_table->psd_in_progress = false;
439
440 if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
441 #if (RTL8723F_SUPPORT)
442 if (dm->support_ic_type & ODM_RTL8723F) {
443 dm_psd_table->psd_reg = R_0x1e8c;
444 dm_psd_table->psd_report_reg = R_0x2d90;
445
446 /*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
447 dm_psd_table->psd_bw_rf_reg = 2;
448 }
449 #else
450 #if 0
451 dm_psd_table->psd_reg = R_0x1e8c;
452 dm_psd_table->psd_report_reg = R_0x2d90;
453
454 /*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
455 dm_psd_table->psd_bw_rf_reg = 1;
456 #endif
457
458 return;
459 #endif
460 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
461 dm_psd_table->psd_reg = R_0x910;
462 dm_psd_table->psd_report_reg = R_0xf44;
463
464 /*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
465 if (ODM_IC_11AC_2_SERIES)
466 dm_psd_table->psd_bw_rf_reg = 1;
467 else
468 dm_psd_table->psd_bw_rf_reg = 2;
469 } else {
470 dm_psd_table->psd_reg = R_0x808;
471 dm_psd_table->psd_report_reg = R_0x8b4;
472 /*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
473 dm_psd_table->psd_bw_rf_reg = 2;
474 }
475
476 dm_psd_table->psd_pwr_common_offset = 0;
477
478 phydm_psd_para_setting(dm, 1, 2, 3, 128, 0, 0, 7, 0);
479 #if 0
480 /*phydm_psd(dm, 0x3c, 0, 127);*/ /* target at -50dBm */
481 #endif
482 }
483
phydm_psd_debug(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)484 void phydm_psd_debug(void *dm_void, char input[][16], u32 *_used,
485 char *output, u32 *_out_len)
486 {
487 struct dm_struct *dm = (struct dm_struct *)dm_void;
488 char help[] = "-h";
489 u32 var1[10] = {0};
490 u32 used = *_used;
491 u32 out_len = *_out_len;
492 u8 i = 0;
493
494 if ((strcmp(input[1], help) == 0)) {
495 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
496 #if (RTL8723F_SUPPORT)
497 if (dm->support_ic_type & ODM_RTL8723F)
498 PDM_SNPF(out_len, used, output + used, out_len - used,
499 "{0} {sw_avg} {hw_avg 0:3} {1:I,2:Q,3:IQ} {fft_point: 128*(1:4)}\n{path_sel 0~3} {0:ADC, 1:rxdata_fir_in, 2:rx_nbi_nf_stage2} {CH} {noise_k}\n\n");
500 #endif
501 #if 0
502 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
503 PDM_SNPF(out_len, used, output + used, out_len - used,
504 "{0} {sw_avg} {hw_avg 0:3} {1:I,2:Q,3:IQ} {fft_point: 128*(1:4) 2048 4096}\n{path_sel 0~3} {0:ADC, 1:rxdata_fir_in, 2:rx_nbi_nf_stage2} {CH} {noise_k}\n\n");
505 else
506 #endif
507 #endif
508 PDM_SNPF(out_len, used, output + used, out_len - used,
509 "{0} {sw_avg} {hw_avg 0:3} {1:I,2:Q,3:IQ} {fft_point: 128*(1:4)} {path_sel 0~3} {0:ADC, 1:RXIQC} {CH} {noise_k}\n");
510
511 PDM_SNPF(out_len, used, output + used, out_len - used,
512 "{1} {IGI(hex)} {start_point} {stop_point}\n");
513 goto out;
514 }
515
516 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
517
518 if (var1[0] == 0) {
519 for (i = 1; i < 10; i++) {
520 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
521 &var1[i]);
522 }
523 PDM_SNPF(out_len, used, output + used, out_len - used,
524 "sw_avg_time=((%d)), hw_avg_time=((%d)), IQ=((%d)), fft=((%d)), path=((%d)), input =((%d)) ch=((%d)), noise_k=((%d))\n",
525 var1[1], var1[2], var1[3], var1[4], var1[5],
526 var1[6], (u8)var1[7], (u8)var1[8]);
527 phydm_psd_para_setting(dm, (u8)var1[1], (u8)var1[2],
528 (u8)var1[3], (u16)var1[4],
529 (u8)var1[5], (u8)var1[6],
530 (u8)var1[7], (u8)var1[8]);
531
532 } else if (var1[0] == 1) {
533 PHYDM_SSCANF(input[2], DCMD_HEX, &var1[1]);
534 PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
535 PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]);
536 PDM_SNPF(out_len, used, output + used, out_len - used,
537 "IGI=((0x%x)), start_point=((%d)), stop_point=((%d))\n",
538 var1[1], var1[2], var1[3]);
539 dm->debug_components |= ODM_COMP_API;
540 if (phydm_psd(dm, var1[1], (u16)var1[2], (u16)var1[3]) ==
541 PHYDM_SET_FAIL)
542 PDM_SNPF(out_len, used, output + used, out_len - used,
543 "PSD_SET_FAIL\n");
544 dm->debug_components &= ~(ODM_COMP_API);
545 }
546
547 out:
548 *_used = used;
549 *_out_len = out_len;
550 }
551
phydm_get_psd_result_table(void * dm_void,int index)552 u8 phydm_get_psd_result_table(void *dm_void, int index)
553 {
554 struct dm_struct *dm = (struct dm_struct *)dm_void;
555 struct psd_info *dm_psd_table = &dm->dm_psd_table;
556 u8 result = 0;
557
558 if (index < 128)
559 result = dm_psd_table->psd_result[index];
560
561 return result;
562 }
563
564 #endif
565