1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 /*@************************************************************
27 * include files
28 ************************************************************/
29 #include "mp_precomp.h"
30 #include "phydm_precomp.h"
31
phydm_is_vht_rate(void * dm_void,u8 rate)32 boolean phydm_is_vht_rate(void *dm_void, u8 rate)
33 {
34 return ((rate & 0x7f) >= ODM_RATEVHTSS1MCS0) ? true : false;
35 }
36
phydm_is_ht_rate(void * dm_void,u8 rate)37 boolean phydm_is_ht_rate(void *dm_void, u8 rate)
38 {
39 return (((rate & 0x7f) >= ODM_RATEMCS0) &&
40 ((rate & 0x7f) <= ODM_RATEMCS31)) ? true : false;
41 }
42
phydm_is_ofdm_rate(void * dm_void,u8 rate)43 boolean phydm_is_ofdm_rate(void *dm_void, u8 rate)
44 {
45 return (((rate & 0x7f) >= ODM_RATE6M) &&
46 ((rate & 0x7f) <= ODM_RATE54M)) ? true : false;
47 }
48
phydm_is_cck_rate(void * dm_void,u8 rate)49 boolean phydm_is_cck_rate(void *dm_void, u8 rate)
50 {
51 return ((rate & 0x7f) <= ODM_RATE11M) ? true : false;
52 }
53
phydm_legacy_rate_2_spec_rate(void * dm_void,u8 rate)54 u8 phydm_legacy_rate_2_spec_rate(void *dm_void, u8 rate)
55 {
56 u8 rate_idx = 0x0;
57 u8 legacy_spec_rate_t[8] = {PHYDM_SPEC_RATE_6M, PHYDM_SPEC_RATE_9M,
58 PHYDM_SPEC_RATE_12M, PHYDM_SPEC_RATE_18M,
59 PHYDM_SPEC_RATE_24M, PHYDM_SPEC_RATE_36M,
60 PHYDM_SPEC_RATE_48M, PHYDM_SPEC_RATE_54M};
61
62 if ((rate >= ODM_RATE6M) && (rate <= ODM_RATE54M))
63 rate_idx = rate - ODM_RATE6M;
64 return legacy_spec_rate_t[rate_idx];
65 }
66
phydm_rate_2_rate_digit(void * dm_void,u8 rate)67 u8 phydm_rate_2_rate_digit(void *dm_void, u8 rate)
68 {
69 u8 legacy_table[12] = {1, 2, 5, 11, 6, 9, 12, 18, 24, 36, 48, 54};
70 u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/
71 u8 rate_digit = 0;
72
73 if (rate_idx >= ODM_RATEVHTSS1MCS0)
74 rate_digit = (rate_idx - ODM_RATEVHTSS1MCS0) % 10;
75 else if (rate_idx >= ODM_RATEMCS0)
76 rate_digit = (rate_idx - ODM_RATEMCS0);
77 else if (rate_idx <= ODM_RATE54M)
78 rate_digit = legacy_table[rate_idx];
79
80 return rate_digit;
81 }
82
phydm_rate_type_2_num_ss(void * dm_void,enum PDM_RATE_TYPE type)83 u8 phydm_rate_type_2_num_ss(void *dm_void, enum PDM_RATE_TYPE type)
84 {
85 u8 num_ss = 1;
86
87 switch (type) {
88 case PDM_CCK:
89 case PDM_OFDM:
90 case PDM_1SS:
91 num_ss = 1;
92 break;
93 case PDM_2SS:
94 num_ss = 2;
95 break;
96 case PDM_3SS:
97 num_ss = 3;
98 break;
99 case PDM_4SS:
100 num_ss = 4;
101 break;
102 default:
103 break;
104 }
105
106 return num_ss;
107 }
108
phydm_rate_to_num_ss(void * dm_void,u8 data_rate)109 u8 phydm_rate_to_num_ss(void *dm_void, u8 data_rate)
110 {
111 u8 num_ss = 1;
112
113 if (data_rate <= ODM_RATE54M)
114 num_ss = 1;
115 else if (data_rate <= ODM_RATEMCS31)
116 num_ss = ((data_rate - ODM_RATEMCS0) >> 3) + 1;
117 else if (data_rate <= ODM_RATEVHTSS1MCS9)
118 num_ss = 1;
119 else if (data_rate <= ODM_RATEVHTSS2MCS9)
120 num_ss = 2;
121 else if (data_rate <= ODM_RATEVHTSS3MCS9)
122 num_ss = 3;
123 else if (data_rate <= ODM_RATEVHTSS4MCS9)
124 num_ss = 4;
125
126 return num_ss;
127 }
128
phydm_h2C_debug(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)129 void phydm_h2C_debug(void *dm_void, char input[][16], u32 *_used,
130 char *output, u32 *_out_len)
131 {
132 struct dm_struct *dm = (struct dm_struct *)dm_void;
133 u32 used = *_used;
134 u32 out_len = *_out_len;
135 u32 dm_value[10] = {0};
136 u8 i = 0, input_idx = 0;
137 u8 h2c_parameter[H2C_MAX_LENGTH] = {0};
138 u8 phydm_h2c_id = 0;
139
140 for (i = 0; i < 8; i++) {
141 PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]);
142 input_idx++;
143 }
144
145 if (input_idx == 0)
146 return;
147
148 phydm_h2c_id = (u8)dm_value[0];
149
150 PDM_SNPF(out_len, used, output + used, out_len - used,
151 "Phydm Send H2C_ID (( 0x%x))\n", phydm_h2c_id);
152
153 for (i = 0; i < H2C_MAX_LENGTH; i++) {
154 h2c_parameter[i] = (u8)dm_value[i + 1];
155 PDM_SNPF(out_len, used, output + used, out_len - used,
156 "H2C: Byte[%d] = ((0x%x))\n", i, h2c_parameter[i]);
157 }
158
159 odm_fill_h2c_cmd(dm, phydm_h2c_id, H2C_MAX_LENGTH, h2c_parameter);
160
161 *_used = used;
162 *_out_len = out_len;
163 }
164
phydm_fw_fix_rate(void * dm_void,u8 en,u8 macid,u8 bw,u8 rate)165 void phydm_fw_fix_rate(void *dm_void, u8 en, u8 macid, u8 bw, u8 rate)
166 {
167 struct dm_struct *dm = (struct dm_struct *)dm_void;
168 u32 reg_u32_tmp;
169
170 if (dm->support_ic_type & PHYDM_IC_8051_SERIES) {
171 reg_u32_tmp = (bw << 24) | (rate << 16) | (macid << 8) | en;
172 odm_set_mac_reg(dm, R_0x4a0, MASKDWORD, reg_u32_tmp);
173
174 } else {
175 if (en == 1)
176 reg_u32_tmp = BYTE_2_DWORD(0x60, macid, bw, rate);
177 else
178 reg_u32_tmp = 0x40000000;
179 if (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8814C))
180 odm_set_mac_reg(dm, R_0x448, MASKDWORD, reg_u32_tmp);
181 else
182 odm_set_mac_reg(dm, R_0x450, MASKDWORD, reg_u32_tmp);
183 }
184 if (en == 1) {
185 PHYDM_DBG(dm, ODM_COMP_API,
186 "FW fix TX rate[id =%d], %dM, Rate(%d)=", macid,
187 (20 << bw), rate);
188 phydm_print_rate(dm, rate, ODM_COMP_API);
189 } else {
190 PHYDM_DBG(dm, ODM_COMP_API, "Auto Rate\n");
191 }
192 }
193
phydm_ra_debug(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)194 void phydm_ra_debug(void *dm_void, char input[][16], u32 *_used, char *output,
195 u32 *_out_len)
196 {
197 struct dm_struct *dm = (struct dm_struct *)dm_void;
198 struct ra_table *ra_tab = &dm->dm_ra_table;
199 u32 used = *_used;
200 u32 out_len = *_out_len;
201 char help[] = "-h";
202 u32 var[5] = {0};
203 u8 macid = 0, bw = 0, rate = 0;
204 u8 tx_cls_en = 0, tx_cls_th = 0, tmp = 0;
205 u8 i = 0;
206
207 for (i = 0; i < 5; i++) {
208 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var[i]);
209 }
210
211 if ((strcmp(input[1], help) == 0)) {
212 PDM_SNPF(out_len, used, output + used, out_len - used,
213 "{1} {0:-,1:+} {ofst}: set offset\n");
214 PDM_SNPF(out_len, used, output + used, out_len - used,
215 "{1} {100}: show offset\n");
216 PDM_SNPF(out_len, used, output + used, out_len - used,
217 "{2} {en} {macid} {bw} {rate}: fw fix rate\n");
218 PDM_SNPF(out_len, used, output + used, out_len - used,
219 "{3} {en}: Dynamic RRSR\n");
220 PDM_SNPF(out_len, used, output + used, out_len - used,
221 "{4} {0:pkt RA, 1:TBTT RA, 100:query RA mode}\n");
222 #ifdef CONFIG_DYNAMIC_TXCOLLISION_TH
223 PDM_SNPF(out_len, used, output + used, out_len - used,
224 "{5} {0:dis, 1:en}{th; 255:auto, xx:dB}: Tx CLS\n");
225 #endif
226 } else if (var[0] == 1) { /*@Adjust PCR offset*/
227
228 if (var[1] == 100) {
229 PDM_SNPF(out_len, used, output + used, out_len - used,
230 "[Get] RA_ofst=((%s%d))\n",
231 ((ra_tab->ra_ofst_direc) ? "+" : "-"),
232 ra_tab->ra_th_ofst);
233
234 } else if (var[1] == 0) {
235 ra_tab->ra_ofst_direc = 0;
236 ra_tab->ra_th_ofst = (u8)var[2];
237 PDM_SNPF(out_len, used, output + used, out_len - used,
238 "[Set] RA_ofst=((-%d))\n", ra_tab->ra_th_ofst);
239 } else if (var[1] == 1) {
240 ra_tab->ra_ofst_direc = 1;
241 ra_tab->ra_th_ofst = (u8)var[2];
242 PDM_SNPF(out_len, used, output + used, out_len - used,
243 "[Set] RA_ofst=((+%d))\n", ra_tab->ra_th_ofst);
244 }
245
246 } else if (var[0] == 2) { /*@FW fix rate*/
247 macid = (u8)var[2];
248 bw = (u8)var[3];
249 rate = (u8)var[4];
250
251 PDM_SNPF(out_len, used, output + used, out_len - used,
252 "[FW fix TX Rate] {en, macid,bw,rate}={%d, %d, %d, 0x%x}",
253 var[1], macid, bw, rate);
254
255 phydm_fw_fix_rate(dm, (u8)var[1], macid, bw, rate);
256 } else if (var[0] == 3) { /*@Dynamic RRSR*/
257 ra_tab->dynamic_rrsr_en = (boolean)var[1];
258 PDM_SNPF(out_len, used, output + used, out_len - used,
259 "[Dynamic RRSR] enable=%d", ra_tab->dynamic_rrsr_en);
260 } else if (var[0] == 4) { /*@RA trigger mode*/
261 if (var[1] == 0 || var[1] == 1)
262 ra_tab->ra_trigger_mode = (u8)var[1];
263 PDM_SNPF(out_len, used, output + used, out_len - used,
264 "[RA trigger] mode=%d\n", ra_tab->ra_trigger_mode);
265 #ifdef CONFIG_DYNAMIC_TXCOLLISION_TH
266 } else if (var[0] == 5) { /*@Tx Collision Detection*/
267 tx_cls_en = (u8)var[1];
268 ra_tab->ra_tx_cls_th = (u8)var[2];
269 tmp = (u8)var[2];
270 tx_cls_th = (tmp < 50) ? 0 : (tmp > 81) ? 31 : tmp - 50;
271 if (tx_cls_en) {
272 odm_set_bb_reg(dm, R_0x8f8, BIT(16), 1);
273 if (ra_tab->ra_tx_cls_th != 255) {
274 phydm_tx_collsion_th_set(dm, tx_cls_th,
275 tx_cls_th);
276 }
277
278 } else {
279 odm_set_bb_reg(dm, R_0x8f8, BIT(16), 0);
280 }
281
282 if (tx_cls_en & ra_tab->ra_tx_cls_th != 255) {
283 PDM_SNPF(out_len, used, output + used, out_len - used,
284 "[Tx Collision Detec] {en, th}={%d, %d}\n",
285 tx_cls_en, tx_cls_th + 50);
286 } else if (tx_cls_en & ra_tab->ra_tx_cls_th == 255) {
287 PDM_SNPF(out_len, used, output + used, out_len - used,
288 "[Tx Collision Detec] {en, th}={%d, auto}\n",
289 tx_cls_en);
290 } else {
291 PDM_SNPF(out_len, used, output + used, out_len - used,
292 "[Tx Collision Detec] {en, th}={%d, xx}\n",
293 tx_cls_en);
294 }
295 #endif
296 } else {
297 PDM_SNPF(out_len, used, output + used, out_len - used,
298 "[Set] Error\n");
299 }
300 *_used = used;
301 *_out_len = out_len;
302 }
303
phydm_ra_mask_report_h2c_trigger(void * dm_void,struct ra_mask_rpt_trig * trig_rpt)304 void phydm_ra_mask_report_h2c_trigger(void *dm_void,
305 struct ra_mask_rpt_trig *trig_rpt)
306 {
307 struct dm_struct *dm = (struct dm_struct *)dm_void;
308 struct ra_table *ra_tab = &dm->dm_ra_table;
309
310 phydm_fw_trace_en_h2c(dm, true, 1, 2, trig_rpt->macid);
311
312 trig_rpt->ra_mask_rpt_stamp = ra_tab->ra_mask_rpt_stamp;
313 }
phydm_ra_mask_report_c2h_result(void * dm_void,struct ra_mask_rpt * rpt)314 void phydm_ra_mask_report_c2h_result(void *dm_void, struct ra_mask_rpt *rpt)
315 {
316 struct dm_struct *dm = (struct dm_struct *)dm_void;
317 struct ra_table *ra_tab = &dm->dm_ra_table;
318 u8 i = 0;
319
320 rpt->ra_mask_rpt_stamp = ra_tab->ra_mask_rpt_stamp;
321
322 odm_move_memory(dm, &rpt->ra_mask_buf[0], &ra_tab->ra_mask_buf[0], 8);
323 }
324
odm_c2h_ra_para_report_handler(void * dm_void,u8 * cmd_buf,u8 cmd_len)325 void odm_c2h_ra_para_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)
326 {
327 struct dm_struct *dm = (struct dm_struct *)dm_void;
328 struct ra_table *ra_tab = &dm->dm_ra_table;
329 u8 mode = cmd_buf[0]; /*Retry Penalty, NH, NL*/
330 u8 i;
331
332 PHYDM_DBG(dm, DBG_FW_TRACE, "[%s] [mode: %d]----------------------->\n",
333 __func__, mode);
334
335 if (mode == RADBG_DEBUG_MONITOR1) {
336 if (dm->support_ic_type & PHYDM_IC_3081_SERIES) {
337 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "RSSI =",
338 cmd_buf[1]);
339 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", "rate =",
340 cmd_buf[2] & 0x7f);
341 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "SGI =",
342 (cmd_buf[2] & 0x80) >> 7);
343 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "BW =",
344 cmd_buf[3]);
345 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "BW_max =",
346 cmd_buf[4]);
347 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n",
348 "multi_rate0 =", cmd_buf[5]);
349 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n",
350 "multi_rate1 =", cmd_buf[6]);
351 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "DISRA =",
352 cmd_buf[7]);
353 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "VHT_EN =",
354 cmd_buf[8]);
355 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n",
356 "SGI_support =", cmd_buf[9]);
357 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "try_ness =",
358 cmd_buf[10]);
359 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", "pre_rate =",
360 cmd_buf[11]);
361 } else {
362 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "RSSI =",
363 cmd_buf[1]);
364 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %x\n", "BW =",
365 cmd_buf[2]);
366 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "DISRA =",
367 cmd_buf[3]);
368 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "VHT_EN =",
369 cmd_buf[4]);
370 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n",
371 "Hightest rate =", cmd_buf[5]);
372 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n",
373 "Lowest rate =", cmd_buf[6]);
374 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n",
375 "SGI_support =", cmd_buf[7]);
376 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "Rate_ID =",
377 cmd_buf[8]);
378 }
379 } else if (mode == RADBG_DEBUG_MONITOR2) {
380 if (dm->support_ic_type & PHYDM_IC_3081_SERIES) {
381 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "rate_id =",
382 cmd_buf[1]);
383 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n",
384 "highest_rate =", cmd_buf[2]);
385 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n",
386 "lowest_rate =", cmd_buf[3]);
387
388 for (i = 4; i <= 11; i++)
389 PHYDM_DBG(dm, DBG_FW_TRACE, "RAMASK = 0x%x\n",
390 cmd_buf[i]);
391
392 odm_move_memory(dm, &ra_tab->ra_mask_buf[0], &cmd_buf[4], 8);
393 ra_tab->ra_mask_rpt_stamp++;
394 } else {
395 PHYDM_DBG(dm, DBG_FW_TRACE,
396 "%5s %x%x %x%x %x%x %x%x\n", "RA Mask:",
397 cmd_buf[8], cmd_buf[7], cmd_buf[6],
398 cmd_buf[5], cmd_buf[4], cmd_buf[3],
399 cmd_buf[2], cmd_buf[1]);
400 }
401 } else if (mode == RADBG_DEBUG_MONITOR3) {
402 for (i = 0; i < (cmd_len - 1); i++)
403 PHYDM_DBG(dm, DBG_FW_TRACE, "content[%d] = %d\n", i,
404 cmd_buf[1 + i]);
405 } else if (mode == RADBG_DEBUG_MONITOR4)
406 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s {%d.%d}\n", "RA version =",
407 cmd_buf[1], cmd_buf[2]);
408 else if (mode == RADBG_DEBUG_MONITOR5) {
409 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", "Current rate =",
410 cmd_buf[1]);
411 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "Retry ratio =",
412 cmd_buf[2]);
413 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "rate down ratio =",
414 cmd_buf[3]);
415 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", "highest rate =",
416 cmd_buf[4]);
417 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s {0x%x 0x%x}\n", "Muti-try =",
418 cmd_buf[5], cmd_buf[6]);
419 PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x%x%x%x%x\n", "RA mask =",
420 cmd_buf[11], cmd_buf[10], cmd_buf[9], cmd_buf[8],
421 cmd_buf[7]);
422 }
423 PHYDM_DBG(dm, DBG_FW_TRACE, "-------------------------------\n");
424 }
425
phydm_ra_dynamic_retry_count(void * dm_void)426 void phydm_ra_dynamic_retry_count(void *dm_void)
427 {
428 struct dm_struct *dm = (struct dm_struct *)dm_void;
429
430 if (!(dm->support_ability & ODM_BB_DYNAMIC_ARFR))
431 return;
432
433 /*PHYDM_DBG(dm, DBG_RA, "dm->pre_b_noisy = %d\n", dm->pre_b_noisy );*/
434
435 if (dm->pre_b_noisy != dm->noisy_decision) {
436 if (dm->noisy_decision) {
437 PHYDM_DBG(dm, DBG_DYN_ARFR, "Noisy Env. RA fallback\n");
438 odm_set_mac_reg(dm, R_0x430, MASKDWORD, 0x0);
439 odm_set_mac_reg(dm, R_0x434, MASKDWORD, 0x04030201);
440 } else {
441 PHYDM_DBG(dm, DBG_DYN_ARFR, "Clean Env. RA fallback\n");
442 odm_set_mac_reg(dm, R_0x430, MASKDWORD, 0x01000000);
443 odm_set_mac_reg(dm, R_0x434, MASKDWORD, 0x06050402);
444 }
445 dm->pre_b_noisy = dm->noisy_decision;
446 }
447 }
448
phydm_print_rate(void * dm_void,u8 rate,u32 dbg_component)449 void phydm_print_rate(void *dm_void, u8 rate, u32 dbg_component)
450 {
451 struct dm_struct *dm = (struct dm_struct *)dm_void;
452 u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/
453 boolean vht_en = phydm_is_vht_rate(dm, rate_idx);
454 u8 b_sgi = (rate & 0x80) >> 7;
455 u8 rate_ss = phydm_rate_to_num_ss(dm, rate_idx);
456 u8 rate_digit = phydm_rate_2_rate_digit(dm, rate_idx);
457
458 PHYDM_DBG_F(dm, dbg_component, "( %s%s%s%s%s%d%s%s)\n",
459 (vht_en && (rate_ss == 1)) ? "VHT 1ss " : "",
460 (vht_en && (rate_ss == 2)) ? "VHT 2ss " : "",
461 (vht_en && (rate_ss == 3)) ? "VHT 3ss " : "",
462 (vht_en && (rate_ss == 4)) ? "VHT 4ss " : "",
463 (rate_idx >= ODM_RATEMCS0) ? "MCS " : "",
464 rate_digit,
465 (b_sgi) ? "-S" : " ",
466 (rate_idx >= ODM_RATEMCS0) ? "" : "M");
467 }
468
phydm_print_rate_2_buff(void * dm_void,u8 rate,char * buf,u16 buf_size)469 void phydm_print_rate_2_buff(void *dm_void, u8 rate, char *buf, u16 buf_size)
470 {
471 struct dm_struct *dm = (struct dm_struct *)dm_void;
472 u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/
473 boolean vht_en = phydm_is_vht_rate(dm, rate_idx);
474 u8 b_sgi = (rate & 0x80) >> 7;
475 u8 rate_ss = phydm_rate_to_num_ss(dm, rate_idx);
476 u8 rate_digit = phydm_rate_2_rate_digit(dm, rate_idx);
477
478 PHYDM_SNPRINTF(buf, buf_size, "( %s%s%s%s%s%d%s%s)",
479 (vht_en && (rate_ss == 1)) ? "VHT 1ss " : "",
480 (vht_en && (rate_ss == 2)) ? "VHT 2ss " : "",
481 (vht_en && (rate_ss == 3)) ? "VHT 3ss " : "",
482 (vht_en && (rate_ss == 4)) ? "VHT 4ss " : "",
483 (rate_idx >= ODM_RATEMCS0) ? "MCS " : "",
484 rate_digit,
485 (b_sgi) ? "-S" : " ",
486 (rate_idx >= ODM_RATEMCS0) ? "" : "M");
487 }
488
phydm_c2h_ra_report_handler(void * dm_void,u8 * cmd_buf,u8 cmd_len)489 void phydm_c2h_ra_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)
490 {
491 struct dm_struct *dm = (struct dm_struct *)dm_void;
492 struct ra_table *ra_tab = &dm->dm_ra_table;
493 struct cmn_sta_info *sta = NULL;
494 u8 macid = cmd_buf[1];
495 u8 rate = cmd_buf[0];
496 u8 ra_ratio = 0xff;
497 u8 curr_bw = 0xff;
498 u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/
499 u8 rate_order;
500 u8 gid_index = 0;
501 u8 txcls_rate = 0;
502 char dbg_buf[PHYDM_SNPRINT_SIZE] = {0};
503
504 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
505 sta = dm->phydm_sta_info[dm->phydm_macid_table[macid]];
506 #else
507 sta = dm->phydm_sta_info[macid];
508 #endif
509
510 if (cmd_len == 7) {
511 ra_ratio = cmd_buf[5];
512 curr_bw = cmd_buf[6];
513 PHYDM_DBG(dm, DBG_RA, "[%d] PER=%d\n", macid, ra_ratio);
514 } else if (cmd_len == 8) {
515 ra_ratio = cmd_buf[5];
516 curr_bw = cmd_buf[6];
517 txcls_rate = cmd_buf[7];
518 PHYDM_DBG(dm, DBG_RA, "[%d] PER=%d TxCLS=%d\n", macid, ra_ratio,
519 txcls_rate);
520 }
521
522 if (cmd_buf[3] != 0) {
523 if (cmd_buf[3] == 0xff)
524 PHYDM_DBG(dm, DBG_RA, "FW Fix Rate\n");
525 else if (cmd_buf[3] == 1)
526 PHYDM_DBG(dm, DBG_RA, "Try Success\n");
527 else if (cmd_buf[3] == 2)
528 PHYDM_DBG(dm, DBG_RA, "Try Fail & Again\n");
529 else if (cmd_buf[3] == 3)
530 PHYDM_DBG(dm, DBG_RA, "Rate Back\n");
531 else if (cmd_buf[3] == 4)
532 PHYDM_DBG(dm, DBG_RA, "Start rate by RSSI\n");
533 else if (cmd_buf[3] == 5)
534 PHYDM_DBG(dm, DBG_RA, "Try rate\n");
535 }
536 phydm_print_rate_2_buff(dm, rate, dbg_buf, PHYDM_SNPRINT_SIZE);
537 PHYDM_DBG(dm, DBG_RA, "Tx Rate=%s (%d)\n", dbg_buf, rate);
538
539 #ifdef MU_EX_MACID
540 if (macid >= 128 && macid < (128 + MU_EX_MACID)) {
541 gid_index = macid - 128;
542 ra_tab->mu1_rate[gid_index] = rate;
543 }
544 if (macid >= ODM_ASSOCIATE_ENTRY_NUM)
545 return;
546 #endif
547 if (is_sta_active(sta)) {
548 sta->ra_info.curr_tx_rate = rate;
549 sta->ra_info.curr_tx_bw = (enum channel_width)curr_bw;
550 sta->ra_info.curr_retry_ratio = ra_ratio;
551 }
552
553 /*trigger power training*/
554 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
555
556 rate_order = phydm_rate_order_compute(dm, rate_idx);
557
558 if (dm->is_one_entry_only ||
559 (rate_order > ra_tab->highest_client_tx_order &&
560 ra_tab->power_tracking_flag == 1)) {
561 halrf_update_pwr_track(dm, rate_idx);
562 ra_tab->power_tracking_flag = 0;
563 }
564
565 #endif
566
567 #if 0
568 /*trigger dynamic rate ID*/
569 if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E))
570 phydm_update_rate_id(dm, rate, macid);
571 #endif
572 }
573
odm_ra_post_action_on_assoc(void * dm_void)574 void odm_ra_post_action_on_assoc(void *dm_void)
575 {
576 }
577
phydm_modify_RA_PCR_threshold(void * dm_void,u8 ra_ofst_direc,u8 ra_th_ofst)578 void phydm_modify_RA_PCR_threshold(void *dm_void, u8 ra_ofst_direc,
579 u8 ra_th_ofst)
580 {
581 struct dm_struct *dm = (struct dm_struct *)dm_void;
582 struct ra_table *ra_tab = &dm->dm_ra_table;
583
584 ra_tab->ra_ofst_direc = ra_ofst_direc;
585 ra_tab->ra_th_ofst = ra_th_ofst;
586 PHYDM_DBG(dm, DBG_RA_MASK, "Set ra_th_offset=(( %s%d ))\n",
587 ((ra_ofst_direc) ? "+" : "-"), ra_th_ofst);
588 }
589
590 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
591
phydm_gen_ramask_h2c_AP(void * dm_void,struct rtl8192cd_priv * priv,struct sta_info * entry,u8 rssi_level)592 void phydm_gen_ramask_h2c_AP(
593 void *dm_void,
594 struct rtl8192cd_priv *priv,
595 struct sta_info *entry,
596 u8 rssi_level)
597 {
598 struct dm_struct *dm = (struct dm_struct *)dm_void;
599
600 if (dm->support_ic_type == ODM_RTL8812) {
601 #if (RTL8812A_SUPPORT == 1)
602 UpdateHalRAMask8812(priv, entry, rssi_level);
603 #endif
604 } else if (dm->support_ic_type == ODM_RTL8188E) {
605 #if (RTL8188E_SUPPORT == 1)
606 #ifdef TXREPORT
607 add_RATid(priv, entry);
608 #endif
609 #endif
610 } else {
611 #ifdef CONFIG_WLAN_HAL
612 GET_HAL_INTERFACE(priv)->UpdateHalRAMaskHandler(priv, entry, rssi_level);
613 #endif
614 }
615 }
616
phydm_update_hal_ra_mask(void * dm_void,u32 wireless_mode,u8 rf_type,u8 bw,u8 mimo_ps_enable,u8 disable_cck_rate,u32 * ratr_bitmap_msb_in,u32 * ratr_bitmap_lsb_in,u8 tx_rate_level)617 void phydm_update_hal_ra_mask(
618 void *dm_void,
619 u32 wireless_mode,
620 u8 rf_type,
621 u8 bw,
622 u8 mimo_ps_enable,
623 u8 disable_cck_rate,
624 u32 *ratr_bitmap_msb_in,
625 u32 *ratr_bitmap_lsb_in,
626 u8 tx_rate_level)
627 {
628 struct dm_struct *dm = (struct dm_struct *)dm_void;
629 u32 ratr_bitmap = *ratr_bitmap_lsb_in;
630 u32 ratr_bitmap_msb = *ratr_bitmap_msb_in;
631
632 #if 0
633 /*PHYDM_DBG(dm, DBG_RA_MASK, "phydm_rf_type = (( %x )), rf_type = (( %x ))\n", phydm_rf_type, rf_type);*/
634 #endif
635 PHYDM_DBG(dm, DBG_RA_MASK,
636 "Platfoem original RA Mask = (( 0x %x | %x ))\n",
637 ratr_bitmap_msb, ratr_bitmap);
638
639 switch (wireless_mode) {
640 case PHYDM_WIRELESS_MODE_B: {
641 ratr_bitmap &= 0x0000000f;
642 } break;
643
644 case PHYDM_WIRELESS_MODE_G: {
645 ratr_bitmap &= 0x00000ff5;
646 } break;
647
648 case PHYDM_WIRELESS_MODE_A: {
649 ratr_bitmap &= 0x00000ff0;
650 } break;
651
652 case PHYDM_WIRELESS_MODE_N_24G:
653 case PHYDM_WIRELESS_MODE_N_5G: {
654 if (mimo_ps_enable)
655 rf_type = RF_1T1R;
656
657 if (rf_type == RF_1T1R) {
658 if (bw == CHANNEL_WIDTH_40)
659 ratr_bitmap &= 0x000ff015;
660 else
661 ratr_bitmap &= 0x000ff005;
662 } else if (rf_type == RF_2T2R || rf_type == RF_2T4R || rf_type == RF_2T3R) {
663 if (bw == CHANNEL_WIDTH_40)
664 ratr_bitmap &= 0x0ffff015;
665 else
666 ratr_bitmap &= 0x0ffff005;
667 } else { /*@3T*/
668
669 ratr_bitmap &= 0xfffff015;
670 ratr_bitmap_msb &= 0xf;
671 }
672 } break;
673
674 case PHYDM_WIRELESS_MODE_AC_24G: {
675 if (rf_type == RF_1T1R) {
676 ratr_bitmap &= 0x003ff015;
677 } else if (rf_type == RF_2T2R || rf_type == RF_2T4R || rf_type == RF_2T3R) {
678 ratr_bitmap &= 0xfffff015;
679 } else { /*@3T*/
680
681 ratr_bitmap &= 0xfffff010;
682 ratr_bitmap_msb &= 0x3ff;
683 }
684
685 if (bw == CHANNEL_WIDTH_20) { /*@AC 20MHz not support MCS9*/
686 ratr_bitmap &= 0x7fdfffff;
687 ratr_bitmap_msb &= 0x1ff;
688 }
689 } break;
690
691 case PHYDM_WIRELESS_MODE_AC_5G: {
692 if (rf_type == RF_1T1R) {
693 ratr_bitmap &= 0x003ff010;
694 } else if (rf_type == RF_2T2R || rf_type == RF_2T4R || rf_type == RF_2T3R) {
695 ratr_bitmap &= 0xfffff010;
696 } else { /*@3T*/
697
698 ratr_bitmap &= 0xfffff010;
699 ratr_bitmap_msb &= 0x3ff;
700 }
701
702 if (bw == CHANNEL_WIDTH_20) { /*@AC 20MHz not support MCS9*/
703 ratr_bitmap &= 0x7fdfffff;
704 ratr_bitmap_msb &= 0x1ff;
705 }
706 } break;
707
708 default:
709 break;
710 }
711
712 if (wireless_mode != PHYDM_WIRELESS_MODE_B) {
713 if (tx_rate_level == 0)
714 ratr_bitmap &= 0xffffffff;
715 else if (tx_rate_level == 1)
716 ratr_bitmap &= 0xfffffff0;
717 else if (tx_rate_level == 2)
718 ratr_bitmap &= 0xffffefe0;
719 else if (tx_rate_level == 3)
720 ratr_bitmap &= 0xffffcfc0;
721 else if (tx_rate_level == 4)
722 ratr_bitmap &= 0xffff8f80;
723 else if (tx_rate_level >= 5)
724 ratr_bitmap &= 0xffff0f00;
725 }
726
727 if (disable_cck_rate)
728 ratr_bitmap &= 0xfffffff0;
729
730 PHYDM_DBG(dm, DBG_RA_MASK,
731 "wireless_mode= (( 0x%x )), rf_type = (( 0x%x )), BW = (( 0x%x )), MimoPs_en = (( %d )), tx_rate_level= (( 0x%x ))\n",
732 wireless_mode, rf_type, bw, mimo_ps_enable, tx_rate_level);
733
734 #if 0
735 /*PHYDM_DBG(dm, DBG_RA_MASK, "111 Phydm modified RA Mask = (( 0x %x | %x ))\n", ratr_bitmap_msb, ratr_bitmap);*/
736 #endif
737
738 *ratr_bitmap_lsb_in = ratr_bitmap;
739 *ratr_bitmap_msb_in = ratr_bitmap_msb;
740 PHYDM_DBG(dm, DBG_RA_MASK,
741 "Phydm modified RA Mask = (( 0x %x | %x ))\n",
742 *ratr_bitmap_msb_in, *ratr_bitmap_lsb_in);
743 }
744
745 #endif
746
phydm_rate_adaptive_mask_init(void * dm_void)747 void phydm_rate_adaptive_mask_init(void *dm_void)
748 {
749 struct dm_struct *dm = (struct dm_struct *)dm_void;
750 struct ra_table *ra_t = &dm->dm_ra_table;
751
752 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
753 PADAPTER adapter = dm->adapter;
754 PMGNT_INFO mgnt_info = &(adapter->MgntInfo);
755 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)dm->adapter));
756
757 if (mgnt_info->DM_Type == dm_type_by_driver)
758 hal_data->bUseRAMask = true;
759 else
760 hal_data->bUseRAMask = false;
761
762 #endif
763
764 ra_t->ldpc_thres = 35;
765 ra_t->up_ramask_cnt = 0;
766 ra_t->up_ramask_cnt_tmp = 0;
767 }
768
phydm_refresh_rate_adaptive_mask(void * dm_void)769 void phydm_refresh_rate_adaptive_mask(void *dm_void)
770 {
771 /*@Will be removed*/
772 struct dm_struct *dm = (struct dm_struct *)dm_void;
773
774 phydm_ra_mask_watchdog(dm);
775 }
776
phydm_show_sta_info(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)777 void phydm_show_sta_info(void *dm_void, char input[][16], u32 *_used,
778 char *output, u32 *_out_len)
779 {
780 struct dm_struct *dm = (struct dm_struct *)dm_void;
781 struct cmn_sta_info *sta = NULL;
782 struct ra_sta_info *ra = NULL;
783 #ifdef CONFIG_BEAMFORMING
784 struct bf_cmn_info *bf = NULL;
785 #endif
786 char help[] = "-h";
787 u32 var[10] = {0};
788 u32 used = *_used;
789 u32 out_len = *_out_len;
790 u32 i, sta_idx_start, sta_idx_end;
791 u8 tatal_sta_num = 0;
792
793 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var[0]);
794
795 if ((strcmp(input[1], help) == 0)) {
796 PDM_SNPF(out_len, used, output + used, out_len - used,
797 "All STA: {1}\n");
798 PDM_SNPF(out_len, used, output + used, out_len - used,
799 "STA[macid]: {2} {macid}\n");
800 return;
801 } else if (var[0] == 1) {
802 sta_idx_start = 0;
803 sta_idx_end = ODM_ASSOCIATE_ENTRY_NUM;
804 } else if (var[0] == 2) {
805 sta_idx_start = var[1];
806 sta_idx_end = var[1];
807 } else {
808 PDM_SNPF(out_len, used, output + used, out_len - used,
809 "Warning input value!\n");
810 return;
811 }
812
813 for (i = sta_idx_start; i < sta_idx_end; i++) {
814 sta = dm->phydm_sta_info[i];
815
816 if (!is_sta_active(sta))
817 continue;
818
819 ra = &sta->ra_info;
820 #ifdef CONFIG_BEAMFORMING
821 bf = &sta->bf_info;
822 #endif
823
824 tatal_sta_num++;
825
826 PDM_SNPF(out_len, used, output + used, out_len - used,
827 "==[sta_idx: %d][MACID: %d]============>\n", i,
828 sta->mac_id);
829 PDM_SNPF(out_len, used, output + used, out_len - used,
830 "AID:%d\n", sta->aid);
831 PDM_SNPF(out_len, used, output + used, out_len - used,
832 "ADDR:%x-%x-%x-%x-%x-%x\n", sta->mac_addr[5],
833 sta->mac_addr[4], sta->mac_addr[3], sta->mac_addr[2],
834 sta->mac_addr[1], sta->mac_addr[0]);
835 PDM_SNPF(out_len, used, output + used, out_len - used,
836 "DM_ctrl:0x%x\n", sta->dm_ctrl);
837 PDM_SNPF(out_len, used, output + used, out_len - used,
838 "BW:%d, MIMO_Type:0x%x\n", sta->bw_mode,
839 sta->mimo_type);
840 PDM_SNPF(out_len, used, output + used, out_len - used,
841 "STBC_en:%d, LDPC_en=%d\n", sta->stbc_en,
842 sta->ldpc_en);
843
844 /*@[RSSI Info]*/
845 PDM_SNPF(out_len, used, output + used, out_len - used,
846 "RSSI{All, OFDM, CCK}={%d, %d, %d}\n",
847 sta->rssi_stat.rssi, sta->rssi_stat.rssi_ofdm,
848 sta->rssi_stat.rssi_cck);
849
850 /*@[RA Info]*/
851 PDM_SNPF(out_len, used, output + used, out_len - used,
852 "Rate_ID:%d, RSSI_LV:%d, ra_bw:%d, SGI_en:%d\n",
853 ra->rate_id, ra->rssi_level, ra->ra_bw_mode,
854 ra->is_support_sgi);
855
856 PDM_SNPF(out_len, used, output + used, out_len - used,
857 "VHT_en:%d, Wireless_set=0x%x, sm_ps=%d\n",
858 ra->is_vht_enable, sta->support_wireless_set,
859 sta->sm_ps);
860
861 PDM_SNPF(out_len, used, output + used, out_len - used,
862 "Dis{RA, PT}={%d, %d}, TxRx:%d, Noisy:%d\n",
863 ra->disable_ra, ra->disable_pt, ra->txrx_state,
864 ra->is_noisy);
865
866 PDM_SNPF(out_len, used, output + used, out_len - used,
867 "TX{Rate, BW}={0x%x, %d}, RTY:%d\n", ra->curr_tx_rate,
868 ra->curr_tx_bw, ra->curr_retry_ratio);
869
870 PDM_SNPF(out_len, used, output + used, out_len - used,
871 "RA_Mask:0x%llx\n", ra->ramask);
872
873 /*@[TP]*/
874 PDM_SNPF(out_len, used, output + used, out_len - used,
875 "TP{TX,RX}={%d, %d}\n", sta->tx_moving_average_tp,
876 sta->rx_moving_average_tp);
877
878 #ifdef CONFIG_BEAMFORMING
879 /*@[Beamforming]*/
880 PDM_SNPF(out_len, used, output + used, out_len - used,
881 "BF CAP{HT,VHT}={0x%x, 0x%x}\n", bf->ht_beamform_cap,
882 bf->vht_beamform_cap);
883 PDM_SNPF(out_len, used, output + used, out_len - used,
884 "BF {p_aid,g_id}={0x%x, 0x%x}\n\n", bf->p_aid,
885 bf->g_id);
886 #endif
887 }
888
889 if (tatal_sta_num == 0) {
890 PDM_SNPF(out_len, used, output + used, out_len - used,
891 "No Linked STA\n");
892 }
893
894 *_used = used;
895 *_out_len = out_len;
896 }
897
phydm_get_rx_stream_num(void * dm_void,enum rf_type type)898 u8 phydm_get_rx_stream_num(void *dm_void, enum rf_type type)
899 {
900 struct dm_struct *dm = (struct dm_struct *)dm_void;
901 u8 rx_num = 1;
902
903 if (type == RF_1T1R)
904 rx_num = 1;
905 else if (type == RF_2T2R || type == RF_1T2R)
906 rx_num = 2;
907 else if (type == RF_3T3R || type == RF_2T3R)
908 rx_num = 3;
909 else if (type == RF_4T4R || type == RF_3T4R || type == RF_2T4R)
910 rx_num = 4;
911 else
912 pr_debug("[Warrning] %s\n", __func__);
913
914 return rx_num;
915 }
916
phydm_get_tx_stream_num(void * dm_void,enum rf_type type)917 u8 phydm_get_tx_stream_num(void *dm_void, enum rf_type type)
918 {
919 struct dm_struct *dm = (struct dm_struct *)dm_void;
920 u8 tx_num = 1;
921
922 if (type == RF_1T1R || type == RF_1T2R)
923 tx_num = 1;
924 else if (type == RF_2T2R || type == RF_2T3R || type == RF_2T4R)
925 tx_num = 2;
926 else if (type == RF_3T3R || type == RF_3T4R)
927 tx_num = 3;
928 else if (type == RF_4T4R)
929 tx_num = 4;
930 else
931 PHYDM_DBG(dm, DBG_RA, "[Warrning] no mimo_type is found\n");
932
933 return tx_num;
934 }
935
phydm_get_bb_mod_ra_mask(void * dm_void,u8 sta_idx)936 u64 phydm_get_bb_mod_ra_mask(void *dm_void, u8 sta_idx)
937 {
938 struct dm_struct *dm = (struct dm_struct *)dm_void;
939 struct phydm_iot_center *iot_table = &dm->iot_table;
940 struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
941 struct ra_sta_info *ra = NULL;
942 enum channel_width bw = 0;
943 enum wireless_set wrls_mode = 0;
944 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
945 struct rtl8192cd_priv *priv = dm->priv;
946 #endif
947 u8 tx_stream_num = 1;
948 u8 rssi_lv = 0;
949 u64 ra_mask_bitmap = 0;
950
951 if (is_sta_active(sta)) {
952 ra = &sta->ra_info;
953 bw = ra->ra_bw_mode;
954 wrls_mode = sta->support_wireless_set;
955 tx_stream_num = phydm_get_tx_stream_num(dm, sta->mimo_type);
956 rssi_lv = ra->rssi_level;
957 ra_mask_bitmap = ra->ramask;
958 } else {
959 PHYDM_DBG(dm, DBG_RA, "[Warning] %s invalid STA\n", __func__);
960 return 0;
961 }
962
963 PHYDM_DBG(dm, DBG_RA, "macid=%d ori_RA_Mask= 0x%llx\n", sta->mac_id,
964 ra_mask_bitmap);
965 PHYDM_DBG(dm, DBG_RA,
966 "wireless_mode=0x%x, tx_ss=%d, BW=%d, MimoPs=%d, rssi_lv=%d\n",
967 wrls_mode, tx_stream_num, bw, sta->sm_ps, rssi_lv);
968
969 if (sta->sm_ps == SM_PS_STATIC) /*@mimo_ps_enable*/
970 tx_stream_num = 1;
971
972 /*@[Modify RA Mask by Wireless Mode]*/
973
974 if (wrls_mode == WIRELESS_CCK) { /*@B mode*/
975 ra_mask_bitmap &= 0x0000000f;
976 } else if (wrls_mode == WIRELESS_OFDM) { /*@G mode*/
977 ra_mask_bitmap &= 0x00000ff0;
978 } else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM)) { /*@BG mode*/
979 ra_mask_bitmap &= 0x00000ff5;
980 } else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT)) {
981 /*N_2G*/
982 if (tx_stream_num == 1) {
983 if (bw == CHANNEL_WIDTH_40)
984 ra_mask_bitmap &= 0x000ff015;
985 else
986 ra_mask_bitmap &= 0x000ff005;
987 } else if (tx_stream_num == 2) {
988 if (bw == CHANNEL_WIDTH_40)
989 ra_mask_bitmap &= 0x0ffff015;
990 else
991 ra_mask_bitmap &= 0x0ffff005;
992 } else if (tx_stream_num == 3) {
993 ra_mask_bitmap &= 0xffffff015;
994 } else {
995 ra_mask_bitmap &= 0xffffffff015;
996 }
997 } else if (wrls_mode == (WIRELESS_OFDM | WIRELESS_HT)) { /*N_5G*/
998
999 if (tx_stream_num == 1) {
1000 if (bw == CHANNEL_WIDTH_40)
1001 ra_mask_bitmap &= 0x000ff030;
1002 else
1003 ra_mask_bitmap &= 0x000ff010;
1004 } else if (tx_stream_num == 2) {
1005 if (bw == CHANNEL_WIDTH_40)
1006 ra_mask_bitmap &= 0x0ffff030;
1007 else
1008 ra_mask_bitmap &= 0x0ffff010;
1009 } else if (tx_stream_num == 3) {
1010 ra_mask_bitmap &= 0xffffff010;
1011 } else {
1012 ra_mask_bitmap &= 0xffffffff010;
1013 }
1014 } else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT)) {
1015 /*@AC_2G*/
1016 if (tx_stream_num == 1)
1017 ra_mask_bitmap &= 0x003ff015;
1018 else if (tx_stream_num == 2)
1019 ra_mask_bitmap &= 0xfffff015;
1020 else if (tx_stream_num == 3)
1021 ra_mask_bitmap &= 0x3fffffff015;
1022 else /*@AC_4SS 2G*/
1023 ra_mask_bitmap &= 0x000ffffffffff015;
1024 if (bw == CHANNEL_WIDTH_20) {
1025 /* @AC 20MHz doesn't support MCS9 except 3SS & 6SS*/
1026 ra_mask_bitmap &= 0x0007ffff7fdff015;
1027 } else if (bw == CHANNEL_WIDTH_80) {
1028 /* @AC 80MHz doesn't support 3SS MCS6*/
1029 ra_mask_bitmap &= 0x000fffbffffff015;
1030 }
1031 } else if (wrls_mode == (WIRELESS_OFDM | WIRELESS_VHT)) { /*@AC_5G*/
1032
1033 if (tx_stream_num == 1)
1034 ra_mask_bitmap &= 0x003ff010;
1035 else if (tx_stream_num == 2)
1036 ra_mask_bitmap &= 0xfffff010;
1037 else if (tx_stream_num == 3)
1038 ra_mask_bitmap &= 0x3fffffff010;
1039 else /*@AC_4SS 5G*/
1040 ra_mask_bitmap &= 0x000ffffffffff010;
1041
1042 if (bw == CHANNEL_WIDTH_20) {
1043 /* @AC 20MHz doesn't support MCS9 except 3SS & 6SS*/
1044 ra_mask_bitmap &= 0x0007ffff7fdff010;
1045 } else if (bw == CHANNEL_WIDTH_80) {
1046 /* @AC 80MHz doesn't support 3SS MCS6*/
1047 ra_mask_bitmap &= 0x000fffbffffff010;
1048 } else if (bw == CHANNEL_WIDTH_160) {
1049 /* @AC 80M+80M doesn't support 3SS & 4SS*/
1050 ra_mask_bitmap &= 0xfffff010;
1051 }
1052 } else {
1053 PHYDM_DBG(dm, DBG_RA, "[Warrning] RA mask is Not found\n");
1054 }
1055
1056 PHYDM_DBG(dm, DBG_RA, "Mod by mode=0x%llx\n", ra_mask_bitmap);
1057
1058 #if ((DM_ODM_SUPPORT_TYPE == ODM_AP) && defined(PHYDM_IC_JGR3_SERIES_SUPPORT))
1059 if (priv->pshare->veriwave_sta_num > 0) {
1060 PHYDM_DBG(dm, DBG_RA, "Mod by RSSI=0x%llx\n", ra_mask_bitmap);
1061 return ra_mask_bitmap;
1062 }
1063 #endif
1064 /*@[Modify RA Mask by RSSI level]*/
1065 if (wrls_mode != WIRELESS_CCK) {
1066 if (iot_table->patch_id_40010700) {
1067 ra_mask_bitmap &= (rssi_lv == 0 ?
1068 0xffffffffffffffff :
1069 0xfffffffffffffff0);
1070 return ra_mask_bitmap;
1071 }
1072
1073 if (rssi_lv == 0)
1074 ra_mask_bitmap &= 0xffffffffffffffff;
1075 else if (rssi_lv == 1)
1076 ra_mask_bitmap &= 0xfffffffffffffff0;
1077 else if (rssi_lv == 2)
1078 ra_mask_bitmap &= 0xffffffffffffefe0;
1079 else if (rssi_lv == 3)
1080 ra_mask_bitmap &= 0xffffffffffffcfc0;
1081 else if (rssi_lv == 4)
1082 ra_mask_bitmap &= 0xffffffffffff8f80;
1083 else if (rssi_lv >= 5)
1084 ra_mask_bitmap &= 0xffffffffffff0f00;
1085 }
1086 PHYDM_DBG(dm, DBG_RA, "Mod by RSSI=0x%llx\n", ra_mask_bitmap);
1087
1088 return ra_mask_bitmap;
1089 }
1090
phydm_get_rate_from_rssi_lv(void * dm_void,u8 sta_idx)1091 u8 phydm_get_rate_from_rssi_lv(void *dm_void, u8 sta_idx)
1092 {
1093 struct dm_struct *dm = (struct dm_struct *)dm_void;
1094 struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
1095 struct ra_sta_info *ra = NULL;
1096 enum wireless_set wrls_set = 0;
1097 u8 rssi_lv = 0;
1098 u8 rate_idx = 0;
1099 u8 rate_ofst = 0;
1100
1101 if (is_sta_active(sta)) {
1102 ra = &sta->ra_info;
1103 wrls_set = sta->support_wireless_set;
1104 rssi_lv = ra->rssi_level;
1105 } else {
1106 pr_debug("[Warning] %s: invalid STA\n", __func__);
1107 return 0;
1108 }
1109
1110 PHYDM_DBG(dm, DBG_RA, "[%s]macid=%d, wireless_set=0x%x, rssi_lv=%d\n",
1111 __func__, sta->mac_id, wrls_set, rssi_lv);
1112
1113 rate_ofst = (rssi_lv <= 1) ? 0 : (rssi_lv - 1);
1114
1115 if (wrls_set & WIRELESS_VHT) {
1116 rate_idx = ODM_RATEVHTSS1MCS0 + rate_ofst;
1117 } else if (wrls_set & WIRELESS_HT) {
1118 rate_idx = ODM_RATEMCS0 + rate_ofst;
1119 } else if (wrls_set & WIRELESS_OFDM) {
1120 rate_idx = ODM_RATE6M + rate_ofst;
1121 } else {
1122 rate_idx = ODM_RATE1M + rate_ofst;
1123
1124 if (rate_idx > ODM_RATE11M)
1125 rate_idx = ODM_RATE11M;
1126 }
1127 return rate_idx;
1128 }
1129
phydm_get_rate_id(void * dm_void,u8 sta_idx)1130 u8 phydm_get_rate_id(void *dm_void, u8 sta_idx)
1131 {
1132 struct dm_struct *dm = (struct dm_struct *)dm_void;
1133 struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
1134 struct ra_sta_info *ra = NULL;
1135 enum channel_width bw = 0;
1136 enum wireless_set wrls_mode = 0;
1137 u8 tx_stream_num = 1;
1138 u8 rate_id_idx = PHYDM_BGN_20M_1SS;
1139
1140 if (is_sta_active(sta)) {
1141 ra = &sta->ra_info;
1142 bw = ra->ra_bw_mode;
1143 wrls_mode = sta->support_wireless_set;
1144 tx_stream_num = phydm_get_tx_stream_num(dm, sta->mimo_type);
1145
1146 } else {
1147 PHYDM_DBG(dm, DBG_RA, "[Warning] %s: invalid STA\n", __func__);
1148 return 0;
1149 }
1150
1151 PHYDM_DBG(dm, DBG_RA, "macid=%d,wireless_set=0x%x,tx_SS_num=%d,BW=%d\n",
1152 sta->mac_id, wrls_mode, tx_stream_num, bw);
1153
1154 if (wrls_mode == WIRELESS_CCK) {
1155 /*@B mode*/
1156 rate_id_idx = PHYDM_B_20M;
1157 } else if (wrls_mode == WIRELESS_OFDM) {
1158 /*@G mode*/
1159 rate_id_idx = PHYDM_G;
1160 } else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM)) {
1161 /*@BG mode*/
1162 rate_id_idx = PHYDM_BG;
1163 } else if (wrls_mode == (WIRELESS_OFDM | WIRELESS_HT)) {
1164 /*@GN mode*/
1165 if (tx_stream_num == 1)
1166 rate_id_idx = PHYDM_GN_N1SS;
1167 else if (tx_stream_num == 2)
1168 rate_id_idx = PHYDM_GN_N2SS;
1169 else if (tx_stream_num == 3)
1170 rate_id_idx = PHYDM_ARFR5_N_3SS;
1171 else if (tx_stream_num == 4)
1172 rate_id_idx = PHYDM_ARFR7_N_4SS;
1173 } else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT)) {
1174 /*@BGN mode*/
1175 if (bw == CHANNEL_WIDTH_40) {
1176 if (tx_stream_num == 1)
1177 rate_id_idx = PHYDM_BGN_40M_1SS;
1178 else if (tx_stream_num == 2)
1179 rate_id_idx = PHYDM_BGN_40M_2SS;
1180 else if (tx_stream_num == 3)
1181 rate_id_idx = PHYDM_ARFR5_N_3SS;
1182 else if (tx_stream_num == 4)
1183 rate_id_idx = PHYDM_ARFR7_N_4SS;
1184
1185 } else {
1186 if (tx_stream_num == 1)
1187 rate_id_idx = PHYDM_BGN_20M_1SS;
1188 else if (tx_stream_num == 2)
1189 rate_id_idx = PHYDM_BGN_20M_2SS;
1190 else if (tx_stream_num == 3)
1191 rate_id_idx = PHYDM_ARFR5_N_3SS;
1192 else if (tx_stream_num == 4)
1193 rate_id_idx = PHYDM_ARFR7_N_4SS;
1194 }
1195 } else if (wrls_mode == (WIRELESS_OFDM | WIRELESS_VHT)) {
1196 /*@AC mode*/
1197 if (bw == CHANNEL_WIDTH_160) {
1198 if (tx_stream_num == 1)
1199 rate_id_idx = PHYDM_ARFR1_AC_1SS;
1200 else if (tx_stream_num == 2)
1201 rate_id_idx = PHYDM_ARFR0_AC_2SS;
1202 else if (tx_stream_num == 3)
1203 rate_id_idx = PHYDM_ARFR0_AC_2SS;
1204 else if (tx_stream_num == 4)
1205 rate_id_idx = PHYDM_ARFR0_AC_2SS;
1206 } else {
1207 if (tx_stream_num == 1)
1208 rate_id_idx = PHYDM_ARFR1_AC_1SS;
1209 else if (tx_stream_num == 2)
1210 rate_id_idx = PHYDM_ARFR0_AC_2SS;
1211 else if (tx_stream_num == 3)
1212 rate_id_idx = PHYDM_ARFR4_AC_3SS;
1213 else if (tx_stream_num == 4)
1214 rate_id_idx = PHYDM_ARFR6_AC_4SS;
1215 }
1216 } else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT)) {
1217 /*@AC 2.4G mode*/
1218 if (bw >= CHANNEL_WIDTH_80) {
1219 if (tx_stream_num == 1)
1220 rate_id_idx = PHYDM_ARFR1_AC_1SS;
1221 else if (tx_stream_num == 2)
1222 rate_id_idx = PHYDM_ARFR0_AC_2SS;
1223 else if (tx_stream_num == 3)
1224 rate_id_idx = PHYDM_ARFR4_AC_3SS;
1225 else if (tx_stream_num == 4)
1226 rate_id_idx = PHYDM_ARFR6_AC_4SS;
1227 } else {
1228 if (tx_stream_num == 1) {
1229 if (dm->support_ic_type & PHYDM_IC_RATEID_IDX_TYPE2)
1230 rate_id_idx = PHYDM_TYPE2_ARFR5_AC_2G_1SS;
1231 else
1232 rate_id_idx = PHYDM_ARFR2_AC_2G_1SS;
1233 } else if (tx_stream_num == 2) {
1234 if (dm->support_ic_type & PHYDM_IC_RATEID_IDX_TYPE2)
1235 rate_id_idx = PHYDM_TYPE2_ARFR3_AC_2G_2SS;
1236 else
1237 rate_id_idx = PHYDM_ARFR3_AC_2G_2SS;
1238 } else if (tx_stream_num == 3) {
1239 rate_id_idx = PHYDM_ARFR4_AC_3SS;
1240 } else if (tx_stream_num == 4) {
1241 rate_id_idx = PHYDM_ARFR6_AC_4SS;
1242 }
1243 }
1244 } else {
1245 PHYDM_DBG(dm, DBG_RA, "[Warrning] No rate_id is found\n");
1246 rate_id_idx = 0;
1247 }
1248
1249 PHYDM_DBG(dm, DBG_RA, "Rate_ID=((0x%x))\n", rate_id_idx);
1250
1251 return rate_id_idx;
1252 }
1253
1254 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
phydm_ra_mode_selection(void * dm_void,u8 mode)1255 void phydm_ra_mode_selection(void *dm_void, u8 mode)
1256 {
1257 struct dm_struct *dm = (struct dm_struct *)dm_void;
1258 struct ra_table *ra_tab = &dm->dm_ra_table;
1259 u8 pre_mode = ra_tab->ra_trigger_mode; /* 0:pkt RA, 1:TBTT RA */
1260
1261 if (mode >= 2) {
1262 PHYDM_DBG(dm, DBG_RA, "RA mode selection Fail\n");
1263 } else {
1264 ra_tab->ra_trigger_mode = mode;
1265 PHYDM_DBG(dm, DBG_RA, "RA mode, 0:pkt RA, 1:TBTT RA\n");
1266 PHYDM_DBG(dm, DBG_RA, "PreMode=%d,CurMode=%d\n", pre_mode,
1267 mode);
1268 }
1269 }
1270 #endif
1271
phydm_ra_h2c(void * dm_void,u8 sta_idx,u8 dis_ra,u8 dis_pt,u8 no_update_bw,u8 init_ra_lv,u64 ra_mask)1272 void phydm_ra_h2c(void *dm_void, u8 sta_idx, u8 dis_ra, u8 dis_pt,
1273 u8 no_update_bw, u8 init_ra_lv, u64 ra_mask)
1274 {
1275 struct dm_struct *dm = (struct dm_struct *)dm_void;
1276 struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
1277 struct ra_sta_info *ra = NULL;
1278 u8 h2c_val[H2C_MAX_LENGTH] = {0};
1279 u8 rate_id_idx = 0;
1280
1281 if (is_sta_active(sta)) {
1282 ra = &sta->ra_info;
1283 } else {
1284 PHYDM_DBG(dm, DBG_RA, "[Warning] %s invalid sta_info\n",
1285 __func__);
1286 return;
1287 }
1288
1289 PHYDM_DBG(dm, DBG_RA, "%s ======>\n", __func__);
1290 PHYDM_DBG(dm, DBG_RA, "MACID=%d\n", sta->mac_id);
1291
1292
1293 #ifdef PHYDM_POWER_TRAINING_SUPPORT
1294 if ((dm->support_ability & ODM_BB_PWR_TRAIN) && !dm->is_disable_power_training)
1295 dis_pt = false;
1296 else
1297 dis_pt = true;
1298
1299 #else
1300 dis_pt= true;
1301 #endif
1302
1303 rate_id_idx = ra->rate_id;
1304
1305 /*for compatibility issues with FW RA [PHYDM-405]*/
1306 if (dm->support_ic_type & PHYDM_IC_RATEID_IDX_TYPE2) {
1307 if (rate_id_idx == PHYDM_TYPE2_ARFR5_AC_2G_1SS)
1308 rate_id_idx = PHYDM_ARFR2_AC_2G_1SS;
1309 else if (rate_id_idx == PHYDM_TYPE2_ARFR3_AC_2G_2SS)
1310 rate_id_idx = PHYDM_ARFR3_AC_2G_2SS;
1311 }
1312
1313 h2c_val[0] = sta->mac_id;
1314 h2c_val[1] = (rate_id_idx & 0x1f) | ((init_ra_lv & 0x3) << 5) |
1315 (ra->is_support_sgi << 7);
1316 h2c_val[2] = (u8)((ra->ra_bw_mode) | (((sta->ldpc_en) ? 1 : 0) << 2) |
1317 ((no_update_bw & 0x1) << 3) |
1318 (ra->is_vht_enable << 4) |
1319 ((dis_pt & 0x1) << 6) | ((dis_ra & 0x1) << 7));
1320
1321 h2c_val[3] = (u8)(ra_mask & 0xff);
1322 h2c_val[4] = (u8)((ra_mask & 0xff00) >> 8);
1323 h2c_val[5] = (u8)((ra_mask & 0xff0000) >> 16);
1324 h2c_val[6] = (u8)((ra_mask & 0xff000000) >> 24);
1325
1326 PHYDM_DBG(dm, DBG_RA, "PHYDM h2c[0x40]=0x%x %x %x %x %x %x %x\n",
1327 h2c_val[6], h2c_val[5], h2c_val[4], h2c_val[3], h2c_val[2],
1328 h2c_val[1], h2c_val[0]);
1329
1330 odm_fill_h2c_cmd(dm, PHYDM_H2C_RA_MASK, H2C_MAX_LENGTH, h2c_val);
1331
1332 #if (defined(PHYDM_COMPILE_ABOVE_3SS))
1333 if (dm->support_ic_type & (PHYDM_IC_ABOVE_3SS)) {
1334 h2c_val[3] = (u8)((ra_mask >> 32) & 0x000000ff);
1335 h2c_val[4] = (u8)(((ra_mask >> 32) & 0x0000ff00) >> 8);
1336 h2c_val[5] = (u8)(((ra_mask >> 32) & 0x00ff0000) >> 16);
1337 h2c_val[6] = (u8)(((ra_mask >> 32) & 0xff000000) >> 24);
1338
1339 PHYDM_DBG(dm, DBG_RA, "h2c[0x46]=0x%x %x %x %x %x %x %x\n",
1340 h2c_val[6], h2c_val[5], h2c_val[4], h2c_val[3],
1341 h2c_val[2], h2c_val[1], h2c_val[0]);
1342
1343 odm_fill_h2c_cmd(dm, PHYDM_RA_MASK_ABOVE_3SS,
1344 H2C_MAX_LENGTH, h2c_val);
1345 }
1346 #endif
1347 }
1348
phydm_ra_registed(void * dm_void,u8 sta_idx,u8 rssi_from_assoc)1349 void phydm_ra_registed(void *dm_void, u8 sta_idx,
1350 /*@index of sta_info array, not MACID*/
1351 u8 rssi_from_assoc)
1352 {
1353 struct dm_struct *dm = (struct dm_struct *)dm_void;
1354 struct ra_table *ra_t = &dm->dm_ra_table;
1355 struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
1356 struct ra_sta_info *ra = NULL;
1357 u8 init_ra_lv = 0;
1358 u64 ra_mask = 0;
1359 /*@SD7 STA_idx != macid*/
1360 /*@SD4,8 STA_idx == macid, */
1361
1362 PHYDM_DBG(dm, DBG_RA_MASK, "%s ======>\n", __func__);
1363
1364 if (is_sta_active(sta)) {
1365 ra = &sta->ra_info;
1366 PHYDM_DBG(dm, DBG_RA_MASK, "sta_idx=%d, macid=%d\n", sta_idx,
1367 sta->mac_id);
1368 } else {
1369 PHYDM_DBG(dm, DBG_RA_MASK, "[Warning] %s invalid STA\n",
1370 __func__);
1371 PHYDM_DBG(dm, DBG_RA_MASK, "sta_idx=%d\n", sta_idx);
1372 return;
1373 }
1374
1375 #if (RTL8188E_SUPPORT == 1) && (RATE_ADAPTIVE_SUPPORT == 1)
1376 if (dm->support_ic_type == ODM_RTL8188E)
1377 ra->rate_id = phydm_get_rate_id_88e(dm, sta_idx);
1378 else
1379 #endif
1380 {
1381 ra->rate_id = phydm_get_rate_id(dm, sta_idx);
1382 }
1383
1384 ra_mask = phydm_get_bb_mod_ra_mask(dm, sta_idx);
1385
1386 PHYDM_DBG(dm, DBG_RA_MASK, "rssi_assoc=%d\n", rssi_from_assoc);
1387
1388 if (rssi_from_assoc > 40)
1389 init_ra_lv = 1;
1390 else if (rssi_from_assoc > 20)
1391 init_ra_lv = 2;
1392 else if (rssi_from_assoc > 1)
1393 init_ra_lv = 3;
1394 else
1395 init_ra_lv = 0;
1396
1397 if (ra_t->record_ra_info)
1398 ra_t->record_ra_info(dm, sta_idx, sta, ra_mask);
1399
1400 #if (RTL8188E_SUPPORT == 1) && (RATE_ADAPTIVE_SUPPORT == 1)
1401 if (dm->support_ic_type == ODM_RTL8188E)
1402 /*@Driver RA*/
1403 phydm_ra_update_8188e(dm, sta_idx, ra->rate_id,
1404 (u32)ra_mask, ra->is_support_sgi);
1405 else
1406 #endif
1407 {
1408 /*@FW RA*/
1409 phydm_ra_h2c(dm, sta_idx, ra->disable_ra, ra->disable_pt, 0,
1410 init_ra_lv, ra_mask);
1411 }
1412 }
1413
phydm_ra_offline(void * dm_void,u8 sta_idx)1414 void phydm_ra_offline(void *dm_void, u8 sta_idx)
1415 {
1416 struct dm_struct *dm = (struct dm_struct *)dm_void;
1417 struct ra_table *ra_t = &dm->dm_ra_table;
1418 struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx];
1419 struct ra_sta_info *ra = NULL;
1420
1421 if (is_sta_active(sta)) {
1422 ra = &sta->ra_info;
1423 } else {
1424 PHYDM_DBG(dm, DBG_RA, "[Warning] %s invalid STA\n", __func__);
1425 return;
1426 }
1427
1428 PHYDM_DBG(dm, DBG_RA, "%s ======>\n", __func__);
1429 PHYDM_DBG(dm, DBG_RA, "MACID=%d\n", sta->mac_id);
1430
1431 odm_memory_set(dm, &ra->rate_id, 0, sizeof(struct ra_sta_info));
1432 ra->disable_ra = 1;
1433 ra->disable_pt = 1;
1434
1435 if (ra_t->record_ra_info)
1436 ra_t->record_ra_info(dm, sta->mac_id, sta, 0);
1437
1438 if (dm->support_ic_type != ODM_RTL8188E)
1439 phydm_ra_h2c(dm, sta->mac_id, 1, 1, 0, 0, 0);
1440 }
1441
phydm_ra_mask_watchdog(void * dm_void)1442 void phydm_ra_mask_watchdog(void *dm_void)
1443 {
1444 struct dm_struct *dm = (struct dm_struct *)dm_void;
1445 struct ra_table *ra_t = &dm->dm_ra_table;
1446 struct cmn_sta_info *sta = NULL;
1447 struct ra_sta_info *ra = NULL;
1448 boolean force_ra_mask_en = false;
1449 u8 sta_idx;
1450 u64 ra_mask;
1451 u8 rssi_lv_new;
1452 u8 rssi = 0;
1453
1454 if (!(dm->support_ability & ODM_BB_RA_MASK))
1455 return;
1456
1457 if (!dm->is_linked || (dm->phydm_sys_up_time % 2) == 1)
1458 return;
1459
1460 PHYDM_DBG(dm, DBG_RA_MASK, "%s ======>\n", __func__);
1461
1462 ra_t->up_ramask_cnt++;
1463
1464 if (ra_t->up_ramask_cnt >= FORCED_UPDATE_RAMASK_PERIOD) {
1465 ra_t->up_ramask_cnt = 0;
1466 force_ra_mask_en = true;
1467 }
1468
1469 for (sta_idx = 0; sta_idx < ODM_ASSOCIATE_ENTRY_NUM; sta_idx++) {
1470 sta = dm->phydm_sta_info[sta_idx];
1471
1472 if (!is_sta_active(sta))
1473 continue;
1474
1475 ra = &sta->ra_info;
1476
1477 if (ra->disable_ra)
1478 continue;
1479
1480 PHYDM_DBG(dm, DBG_RA_MASK, "sta_idx=%d, macid=%d\n", sta_idx,
1481 sta->mac_id);
1482
1483 rssi = (u8)(sta->rssi_stat.rssi);
1484
1485 /*@to be modified*/
1486 #if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
1487 if (dm->support_ic_type == ODM_RTL8812 ||
1488 (dm->support_ic_type == ODM_RTL8821 &&
1489 dm->cut_version == ODM_CUT_A)
1490 ) {
1491 if (rssi < ra_t->ldpc_thres) {
1492 /*@LDPC TX enable*/
1493 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1494 set_ra_ldpc_8812(sta, true);
1495 #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1496 MgntSet_TX_LDPC(dm->adapter, sta->mac_id, true);
1497 #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
1498 /*to be added*/
1499 #endif
1500 PHYDM_DBG(dm, DBG_RA_MASK,
1501 "RSSI=%d, ldpc_en =TRUE\n", rssi);
1502
1503 } else if (rssi > (ra_t->ldpc_thres + 3)) {
1504 /*@LDPC TX disable*/
1505 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1506 set_ra_ldpc_8812(sta, false);
1507 #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1508 MgntSet_TX_LDPC(dm->adapter, sta->mac_id, false);
1509 #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
1510 /*to be added*/
1511 #endif
1512 PHYDM_DBG(dm, DBG_RA_MASK,
1513 "RSSI=%d, ldpc_en =FALSE\n", rssi);
1514 }
1515 }
1516 #endif
1517
1518 rssi_lv_new = phydm_rssi_lv_dec(dm, (u32)rssi, ra->rssi_level);
1519
1520 if (ra->rssi_level != rssi_lv_new ||
1521 (force_ra_mask_en && dm->number_linked_client < 10)) {
1522 PHYDM_DBG(dm, DBG_RA_MASK, "RSSI LV:((%d))->((%d))\n",
1523 ra->rssi_level, rssi_lv_new);
1524
1525 ra->rssi_level = rssi_lv_new;
1526
1527 ra_mask = phydm_get_bb_mod_ra_mask(dm, sta_idx);
1528
1529 if (ra_t->record_ra_info)
1530 ra_t->record_ra_info(dm, sta_idx, sta, ra_mask);
1531
1532 #if (RTL8188E_SUPPORT) && (RATE_ADAPTIVE_SUPPORT)
1533 if (dm->support_ic_type == ODM_RTL8188E)
1534 /*@Driver RA*/
1535 phydm_ra_update_8188e(dm, sta_idx, ra->rate_id,
1536 (u32)ra_mask,
1537 ra->is_support_sgi);
1538 else
1539 #endif
1540 {
1541 /*@FW RA*/
1542 phydm_ra_h2c(dm, sta_idx, ra->disable_ra,
1543 ra->disable_pt, 1, 0, ra_mask);
1544 }
1545 }
1546 }
1547 }
1548
phydm_vht_en_mapping(void * dm_void,u32 wireless_mode)1549 u8 phydm_vht_en_mapping(void *dm_void, u32 wireless_mode)
1550 {
1551 struct dm_struct *dm = (struct dm_struct *)dm_void;
1552 u8 vht_en_out = 0;
1553
1554 if (wireless_mode == PHYDM_WIRELESS_MODE_AC_5G ||
1555 wireless_mode == PHYDM_WIRELESS_MODE_AC_24G ||
1556 wireless_mode == PHYDM_WIRELESS_MODE_AC_ONLY)
1557 vht_en_out = 1;
1558
1559 PHYDM_DBG(dm, DBG_RA, "wireless_mode= (( 0x%x )), VHT_EN= (( %d ))\n",
1560 wireless_mode, vht_en_out);
1561 return vht_en_out;
1562 }
1563
phydm_rftype2rateid_2g_n20(void * dm_void,u8 rf_type)1564 u8 phydm_rftype2rateid_2g_n20(void *dm_void, u8 rf_type)
1565 {
1566 u8 rate_id_idx = 0;
1567
1568 if (rf_type == RF_1T1R)
1569 rate_id_idx = PHYDM_BGN_20M_1SS;
1570 else if (rf_type == RF_2T2R)
1571 rate_id_idx = PHYDM_BGN_20M_2SS;
1572 else if (rf_type == RF_3T3R)
1573 rate_id_idx = PHYDM_ARFR5_N_3SS;
1574 else
1575 rate_id_idx = PHYDM_ARFR7_N_4SS;
1576 return rate_id_idx;
1577 }
1578
phydm_rftype2rateid_2g_n40(void * dm_void,u8 rf_type)1579 u8 phydm_rftype2rateid_2g_n40(void *dm_void, u8 rf_type)
1580 {
1581 u8 rate_id_idx = 0;
1582
1583 if (rf_type == RF_1T1R)
1584 rate_id_idx = PHYDM_BGN_40M_1SS;
1585 else if (rf_type == RF_2T2R)
1586 rate_id_idx = PHYDM_BGN_40M_2SS;
1587 else if (rf_type == RF_3T3R)
1588 rate_id_idx = PHYDM_ARFR5_N_3SS;
1589 else
1590 rate_id_idx = PHYDM_ARFR7_N_4SS;
1591 return rate_id_idx;
1592 }
1593
phydm_rftype2rateid_5g_n(void * dm_void,u8 rf_type)1594 u8 phydm_rftype2rateid_5g_n(void *dm_void, u8 rf_type)
1595 {
1596 u8 rate_id_idx = 0;
1597
1598 if (rf_type == RF_1T1R)
1599 rate_id_idx = PHYDM_GN_N1SS;
1600 else if (rf_type == RF_2T2R)
1601 rate_id_idx = PHYDM_GN_N2SS;
1602 else if (rf_type == RF_3T3R)
1603 rate_id_idx = PHYDM_ARFR5_N_3SS;
1604 else
1605 rate_id_idx = PHYDM_ARFR7_N_4SS;
1606 return rate_id_idx;
1607 }
1608
phydm_rftype2rateid_ac80(void * dm_void,u8 rf_type)1609 u8 phydm_rftype2rateid_ac80(void *dm_void, u8 rf_type)
1610 {
1611 u8 rate_id_idx = 0;
1612
1613 if (rf_type == RF_1T1R)
1614 rate_id_idx = PHYDM_ARFR1_AC_1SS;
1615 else if (rf_type == RF_2T2R)
1616 rate_id_idx = PHYDM_ARFR0_AC_2SS;
1617 else if (rf_type == RF_3T3R)
1618 rate_id_idx = PHYDM_ARFR4_AC_3SS;
1619 else
1620 rate_id_idx = PHYDM_ARFR6_AC_4SS;
1621 return rate_id_idx;
1622 }
1623
phydm_rftype2rateid_ac40(void * dm_void,u8 rf_type)1624 u8 phydm_rftype2rateid_ac40(void *dm_void, u8 rf_type)
1625 {
1626 u8 rate_id_idx = 0;
1627
1628 if (rf_type == RF_1T1R)
1629 rate_id_idx = PHYDM_ARFR2_AC_2G_1SS;
1630 else if (rf_type == RF_2T2R)
1631 rate_id_idx = PHYDM_ARFR3_AC_2G_2SS;
1632 else if (rf_type == RF_3T3R)
1633 rate_id_idx = PHYDM_ARFR4_AC_3SS;
1634 else
1635 rate_id_idx = PHYDM_ARFR6_AC_4SS;
1636 return rate_id_idx;
1637 }
1638
phydm_rate_id_mapping(void * dm_void,u32 wireless_mode,u8 rf_type,u8 bw)1639 u8 phydm_rate_id_mapping(void *dm_void, u32 wireless_mode, u8 rf_type, u8 bw)
1640 {
1641 struct dm_struct *dm = (struct dm_struct *)dm_void;
1642 u8 rate_id_idx = 0;
1643
1644 PHYDM_DBG(dm, DBG_RA,
1645 "wireless_mode= (( 0x%x )), rf_type = (( 0x%x )), BW = (( 0x%x ))\n",
1646 wireless_mode, rf_type, bw);
1647
1648 switch (wireless_mode) {
1649 case PHYDM_WIRELESS_MODE_N_24G:
1650 if (bw == CHANNEL_WIDTH_40)
1651 rate_id_idx = phydm_rftype2rateid_2g_n40(dm, rf_type);
1652 else
1653 rate_id_idx = phydm_rftype2rateid_2g_n20(dm, rf_type);
1654 break;
1655
1656 case PHYDM_WIRELESS_MODE_N_5G:
1657 rate_id_idx = phydm_rftype2rateid_5g_n(dm, rf_type);
1658 break;
1659
1660 case PHYDM_WIRELESS_MODE_G:
1661 rate_id_idx = PHYDM_BG;
1662 break;
1663
1664 case PHYDM_WIRELESS_MODE_A:
1665 rate_id_idx = PHYDM_G;
1666 break;
1667
1668 case PHYDM_WIRELESS_MODE_B:
1669 rate_id_idx = PHYDM_B_20M;
1670 break;
1671
1672 case PHYDM_WIRELESS_MODE_AC_5G:
1673 case PHYDM_WIRELESS_MODE_AC_ONLY:
1674 rate_id_idx = phydm_rftype2rateid_ac80(dm, rf_type);
1675 break;
1676
1677 case PHYDM_WIRELESS_MODE_AC_24G:
1678 /*@Becareful to set "Lowest rate" while using PHYDM_ARFR4_AC_3SS in 2.4G/5G*/
1679 if (bw >= CHANNEL_WIDTH_80)
1680 rate_id_idx = phydm_rftype2rateid_ac80(dm, rf_type);
1681 else
1682 rate_id_idx = phydm_rftype2rateid_ac40(dm, rf_type);
1683 break;
1684
1685 default:
1686 rate_id_idx = 0;
1687 break;
1688 }
1689
1690 PHYDM_DBG(dm, DBG_RA, "RA rate ID = (( 0x%x ))\n", rate_id_idx);
1691
1692 return rate_id_idx;
1693 }
1694
phydm_rssi_lv_dec(void * dm_void,u32 rssi,u8 ratr_state)1695 u8 phydm_rssi_lv_dec(void *dm_void, u32 rssi, u8 ratr_state)
1696 {
1697 struct dm_struct *dm = (struct dm_struct *)dm_void;
1698 /*@MCS0 ~ MCS4 , VHT1SS MCS0 ~ MCS4 , G 6M~24M*/
1699 u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {20, 34, 38, 42, 46, 50, 100};
1700 u8 new_rssi_lv = 0;
1701 u8 i;
1702
1703 PHYDM_DBG(dm, DBG_RA_MASK,
1704 "curr RA level=(%d), Table_ori=[%d, %d, %d, %d, %d, %d]\n",
1705 ratr_state, rssi_lv_t[0], rssi_lv_t[1], rssi_lv_t[2],
1706 rssi_lv_t[3], rssi_lv_t[4], rssi_lv_t[5]);
1707
1708 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
1709 if (i >= (ratr_state))
1710 rssi_lv_t[i] += RA_FLOOR_UP_GAP;
1711 }
1712
1713 PHYDM_DBG(dm, DBG_RA_MASK,
1714 "RSSI=(%d), Table_mod=[%d, %d, %d, %d, %d, %d]\n", rssi,
1715 rssi_lv_t[0], rssi_lv_t[1], rssi_lv_t[2], rssi_lv_t[3],
1716 rssi_lv_t[4], rssi_lv_t[5]);
1717
1718 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
1719 if (rssi < rssi_lv_t[i]) {
1720 new_rssi_lv = i;
1721 break;
1722 }
1723 }
1724 return new_rssi_lv;
1725 }
1726
phydm_get_ofdm_qam_order(void * dm_void,u8 rate_idx)1727 enum phydm_qam_order phydm_get_ofdm_qam_order(void *dm_void, u8 rate_idx)
1728 {
1729 u8 tmp_idx = rate_idx;
1730 enum phydm_qam_order qam_order = PHYDM_QAM_BPSK;
1731 enum phydm_qam_order qam[10] = {PHYDM_QAM_BPSK, PHYDM_QAM_QPSK,
1732 PHYDM_QAM_QPSK, PHYDM_QAM_16QAM,
1733 PHYDM_QAM_16QAM, PHYDM_QAM_64QAM,
1734 PHYDM_QAM_64QAM, PHYDM_QAM_64QAM,
1735 PHYDM_QAM_256QAM, PHYDM_QAM_256QAM};
1736
1737 if (rate_idx <= ODM_RATE11M)
1738 return PHYDM_QAM_CCK;
1739
1740 if (rate_idx >= ODM_RATEVHTSS1MCS0) {
1741 if (rate_idx >= ODM_RATEVHTSS4MCS0)
1742 tmp_idx -= ODM_RATEVHTSS4MCS0;
1743 else if (rate_idx >= ODM_RATEVHTSS3MCS0)
1744 tmp_idx -= ODM_RATEVHTSS3MCS0;
1745 else if (rate_idx >= ODM_RATEVHTSS2MCS0)
1746 tmp_idx -= ODM_RATEVHTSS2MCS0;
1747 else
1748 tmp_idx -= ODM_RATEVHTSS1MCS0;
1749
1750 qam_order = qam[tmp_idx];
1751 } else if (rate_idx >= ODM_RATEMCS0) {
1752 if (rate_idx >= ODM_RATEMCS24)
1753 tmp_idx -= ODM_RATEMCS24;
1754 else if (rate_idx >= ODM_RATEMCS16)
1755 tmp_idx -= ODM_RATEMCS16;
1756 else if (rate_idx >= ODM_RATEMCS8)
1757 tmp_idx -= ODM_RATEMCS8;
1758 else
1759 tmp_idx -= ODM_RATEMCS0;
1760
1761 qam_order = qam[tmp_idx];
1762 } else {
1763 if (rate_idx > ODM_RATE6M) {
1764 tmp_idx -= ODM_RATE6M;
1765 qam_order = qam[tmp_idx - 1];
1766 } else {
1767 qam_order = PHYDM_QAM_BPSK;
1768 }
1769 }
1770
1771 return qam_order;
1772 }
1773
phydm_rate_order_compute(void * dm_void,u8 rate_idx)1774 u8 phydm_rate_order_compute(void *dm_void, u8 rate_idx)
1775 {
1776 u8 rate_order = rate_idx & 0x7f;
1777
1778 rate_idx &= 0x7f;
1779
1780 if (rate_idx >= ODM_RATEVHTSS4MCS0)
1781 rate_order -= ODM_RATEVHTSS4MCS0;
1782 else if (rate_idx >= ODM_RATEVHTSS3MCS0)
1783 rate_order -= ODM_RATEVHTSS3MCS0;
1784 else if (rate_idx >= ODM_RATEVHTSS2MCS0)
1785 rate_order -= ODM_RATEVHTSS2MCS0;
1786 else if (rate_idx >= ODM_RATEVHTSS1MCS0)
1787 rate_order -= ODM_RATEVHTSS1MCS0;
1788 else if (rate_idx >= ODM_RATEMCS24)
1789 rate_order -= ODM_RATEMCS24;
1790 else if (rate_idx >= ODM_RATEMCS16)
1791 rate_order -= ODM_RATEMCS16;
1792 else if (rate_idx >= ODM_RATEMCS8)
1793 rate_order -= ODM_RATEMCS8;
1794 else if (rate_idx >= ODM_RATEMCS0)
1795 rate_order -= ODM_RATEMCS0;
1796 else if (rate_idx >= ODM_RATE6M)
1797 rate_order -= ODM_RATE6M;
1798 else
1799 rate_order -= ODM_RATE1M;
1800
1801 if (rate_idx >= ODM_RATEMCS0)
1802 rate_order++;
1803
1804 return rate_order;
1805 }
1806
1807 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
phydm_rate2ss(void * dm_void,u8 rate_idx)1808 u8 phydm_rate2ss(void *dm_void, u8 rate_idx)
1809 {
1810 u8 ret = 0xff;
1811 u8 i, j;
1812 u8 search_idx;
1813 u32 ss_mapping_tab[4][3] = {{0x00000000, 0x003ff000, 0x000ff000},
1814 {0x00000000, 0xffc00000, 0x0ff00000},
1815 {0x000003ff, 0x0000000f, 0xf0000000},
1816 {0x000ffc00, 0x00000ff0, 0x00000000} };
1817 if (rate_idx < 32) {
1818 search_idx = rate_idx;
1819 j = 0;
1820 } else if (rate_idx < 64) {
1821 search_idx = rate_idx - 32;
1822 j = 1;
1823 } else {
1824 search_idx = rate_idx - 64;
1825 j = 2;
1826 }
1827 for (i = 0; i < 4; i++)
1828 if (ss_mapping_tab[i][j] & BIT(search_idx))
1829 ret = i;
1830 return ret;
1831 }
1832
phydm_rate2plcp(void * dm_void,u8 rate_idx)1833 u8 phydm_rate2plcp(void *dm_void, u8 rate_idx)
1834 {
1835 u8 rate2ss = 0;
1836 u8 ltftime = 0;
1837 u8 plcptime = 0xff;
1838
1839 if (rate_idx < ODM_RATE6M) {
1840 plcptime = 192;
1841 /* @CCK PLCP = 192us (long preamble) */
1842 } else if (rate_idx < ODM_RATEMCS0) {
1843 plcptime = 20;
1844 /* @LegOFDM PLCP = 20us */
1845 } else {
1846 if (rate_idx < ODM_RATEVHTSS1MCS0)
1847 plcptime = 32;
1848 /* @HT mode PLCP = 20us + 12us + 4us x Nss */
1849 else
1850 plcptime = 36;
1851 /* VHT mode PLCP = 20us + 16us + 4us x Nss */
1852 rate2ss = phydm_rate2ss(dm_void, rate_idx);
1853 if (rate2ss != 0xff)
1854 ltftime = (rate2ss + 1) * 4;
1855 else
1856 return 0xff;
1857
1858 plcptime += ltftime;
1859 }
1860 return plcptime;
1861 }
1862
phydm_get_plcp(void * dm_void,u16 macid)1863 u8 phydm_get_plcp(void *dm_void, u16 macid)
1864 {
1865 u8 plcp_time = 0;
1866 struct dm_struct *dm = (struct dm_struct *)dm_void;
1867 struct cmn_sta_info *sta = NULL;
1868 struct ra_sta_info *ra = NULL;
1869
1870 sta = dm->phydm_sta_info[macid];
1871 ra = &sta->ra_info;
1872 plcp_time = phydm_rate2plcp(dm, ra->curr_tx_rate);
1873 return plcp_time;
1874 }
1875 #endif
1876
phydm_ra_common_info_update(void * dm_void)1877 void phydm_ra_common_info_update(void *dm_void)
1878 {
1879 struct dm_struct *dm = (struct dm_struct *)dm_void;
1880 struct ra_table *ra_tab = &dm->dm_ra_table;
1881 struct cmn_sta_info *sta = NULL;
1882 u16 macid;
1883 u8 rate_order_tmp;
1884 u8 rate_idx = 0;
1885 u8 cnt = 0;
1886
1887 ra_tab->highest_client_tx_order = 0;
1888 ra_tab->power_tracking_flag = 1;
1889
1890 if (!dm->number_linked_client)
1891 return;
1892
1893 for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) {
1894 sta = dm->phydm_sta_info[macid];
1895
1896 if (!is_sta_active(sta))
1897 continue;
1898
1899 rate_idx = sta->ra_info.curr_tx_rate & 0x7f;
1900 rate_order_tmp = phydm_rate_order_compute(dm, rate_idx);
1901
1902 if (rate_order_tmp >= ra_tab->highest_client_tx_order) {
1903 ra_tab->highest_client_tx_order = rate_order_tmp;
1904 ra_tab->highest_client_tx_rate_order = macid;
1905 }
1906
1907 cnt++;
1908
1909 if (cnt == dm->number_linked_client)
1910 break;
1911 }
1912 PHYDM_DBG(dm, DBG_RA,
1913 "MACID[%d], Highest Tx order Update for power traking: %d\n",
1914 ra_tab->highest_client_tx_rate_order,
1915 ra_tab->highest_client_tx_order);
1916 }
1917
phydm_rrsr_set_register(void * dm_void,u32 rrsr_val)1918 void phydm_rrsr_set_register(void *dm_void, u32 rrsr_val)
1919 {
1920 struct dm_struct *dm = (struct dm_struct *)dm_void;
1921
1922 odm_set_mac_reg(dm, R_0x440, 0xfffff, rrsr_val);
1923 }
1924
phydm_masked_rrsr_set_register(void * dm_void,u32 rrsr_val)1925 void phydm_masked_rrsr_set_register(void *dm_void, u32 rrsr_val)
1926 {
1927 struct dm_struct *dm = (struct dm_struct *)dm_void;
1928 struct ra_table *ra_tab = &dm->dm_ra_table;
1929
1930 if (ra_tab->rrsr_val_curr == rrsr_val)
1931 return;
1932
1933 ra_tab->rrsr_val_curr = rrsr_val;
1934 odm_set_mac_reg(dm, R_0x440, 0xfffff, rrsr_val);
1935 }
1936
phydm_rrsr_mask(void * dm_void)1937 void phydm_rrsr_mask(void *dm_void)
1938 {
1939 struct dm_struct *dm = (struct dm_struct *)dm_void;
1940 struct ra_table *ra = &dm->dm_ra_table;
1941 struct cmn_sta_info *sta = NULL;
1942 u8 rate_order = 0;
1943 u8 rate_order_min = 0xff;
1944 u32 rrsr_mask = 0, rrsr_mask_ofdm = 0;
1945 u8 tx_rate_idx = 0;
1946 u8 i = 0, sta_cnt = 0;
1947
1948 if (!ra->dynamic_rrsr_en)
1949 return;
1950
1951 if (!dm->is_linked) {
1952 phydm_masked_rrsr_set_register(dm, ra->rrsr_val_init);
1953 return;
1954 }
1955
1956 #if 1
1957 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
1958 sta = dm->phydm_sta_info[i];
1959 if (!is_sta_active(sta))
1960 continue;
1961
1962 sta_cnt++;
1963 tx_rate_idx = sta->ra_info.curr_tx_rate & 0x7f;
1964 rate_order = phydm_rate_order_compute(dm, tx_rate_idx);
1965 if (rate_order < rate_order_min)
1966 rate_order_min = rate_order;
1967
1968 if (sta_cnt == dm->number_linked_client)
1969 break;
1970 }
1971 #else
1972 sta = dm->phydm_sta_info[dm->rssi_min_macid];
1973
1974 if (!is_sta_active(sta)) {
1975 PHYDM_DBG(dm, DBG_DYN_ARFR, "[Warning] %s invalid STA\n",
1976 __func__);
1977 return;
1978 }
1979
1980 rate_order = phydm_rate_order_compute(dm, sta->ra_info.curr_tx_rate);
1981 #endif
1982 if (rate_order_min == 0) {
1983 rrsr_mask = 0x1f;
1984 } else {
1985 rrsr_mask_ofdm = (u32)phydm_gen_bitmask(rate_order_min);
1986 rrsr_mask = (rrsr_mask_ofdm << 4) | 0xf;
1987 }
1988
1989 /*ra->rrsr_val_init = 0x15d;*/
1990
1991 phydm_masked_rrsr_set_register(dm, ra->rrsr_val_init & rrsr_mask);
1992
1993 PHYDM_DBG(dm, DBG_DYN_ARFR,
1994 "tx{rate, rate_order_min}={0x%x, %d}, rrsr_init=0x%x, ofdm_rrsr_mask=0x%x, rrsr_val=0x%x\n",
1995 tx_rate_idx, rate_order_min, ra->rrsr_val_init,
1996 rrsr_mask, ra->rrsr_val_curr);
1997 }
1998
phydm_ra_info_watchdog(void * dm_void)1999 void phydm_ra_info_watchdog(void *dm_void)
2000 {
2001 struct dm_struct *dm = (struct dm_struct *)dm_void;
2002
2003 phydm_ra_common_info_update(dm);
2004 phydm_ra_dynamic_retry_count(dm);
2005 phydm_rrsr_mask(dm);
2006 phydm_ra_mask_watchdog(dm);
2007
2008 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2009 odm_refresh_basic_rate_mask(dm);
2010 #endif
2011 }
2012
phydm_rrsr_en(void * dm_void,boolean en_rrsr)2013 void phydm_rrsr_en(void *dm_void, boolean en_rrsr)
2014 {
2015 struct dm_struct *dm = (struct dm_struct *)dm_void;
2016 struct ra_table *ra_tab = &dm->dm_ra_table;
2017
2018 ra_tab->dynamic_rrsr_en = en_rrsr;
2019 }
2020
phydm_arfr_table_init(void * dm_void)2021 void phydm_arfr_table_init(void *dm_void)
2022 {
2023 struct dm_struct *dm = (struct dm_struct *)dm_void;
2024
2025 if (dm->support_ic_type & PHYDM_IC_RATEID_IDX_TYPE2) {
2026 /*ARFR table3(2.4g ac 2ss) for rate_id = 16*/
2027 odm_set_mac_reg(dm, R_0x494, MASKDWORD, 0xfe01f015);
2028 odm_set_mac_reg(dm, R_0x498, MASKDWORD, 0x40000000);
2029
2030 /*ARFR table5(2.4g ac 1ss) for rate_id = 18*/
2031 odm_set_mac_reg(dm, R_0x4a4, MASKDWORD, 0x3ff015);
2032 odm_set_mac_reg(dm, R_0x4a8, MASKDWORD, 0x40000000);
2033 }
2034 }
2035
phydm_ra_info_init(void * dm_void)2036 void phydm_ra_info_init(void *dm_void)
2037 {
2038 struct dm_struct *dm = (struct dm_struct *)dm_void;
2039 struct ra_table *ra_tab = &dm->dm_ra_table;
2040
2041 ra_tab->highest_client_tx_rate_order = 0;
2042 ra_tab->highest_client_tx_order = 0;
2043 ra_tab->ra_th_ofst = 0;
2044 ra_tab->ra_ofst_direc = 0;
2045 ra_tab->rrsr_val_init = odm_get_mac_reg(dm, R_0x440, MASKDWORD);
2046 ra_tab->dynamic_rrsr_en = false;
2047 ra_tab->ra_trigger_mode = 1; // default TBTT RA
2048 ra_tab->ra_tx_cls_th = 255;
2049 #if (RTL8822B_SUPPORT == 1)
2050 if (dm->support_ic_type == ODM_RTL8822B) {
2051 u32 ret_value;
2052
2053 ret_value = odm_get_mac_reg(dm, R_0x4c8, MASKBYTE2);
2054 odm_set_mac_reg(dm, R_0x4cc, MASKBYTE3, (ret_value - 1));
2055 }
2056 #endif
2057
2058 #if 0 /*@CONFIG_RA_DYNAMIC_RTY_LIMIT*/
2059 phydm_ra_dynamic_retry_limit_init(dm);
2060 #endif
2061
2062 #if 0 /*@CONFIG_RA_DYNAMIC_RATE_ID*/
2063 phydm_ra_dynamic_rate_id_init(dm);
2064 #endif
2065
2066 phydm_arfr_table_init(dm);
2067
2068 phydm_rate_adaptive_mask_init(dm);
2069 }
2070
odm_find_rts_rate(void * dm_void,u8 tx_rate,boolean is_erp_protect)2071 u8 odm_find_rts_rate(void *dm_void, u8 tx_rate, boolean is_erp_protect)
2072 {
2073 struct dm_struct *dm = (struct dm_struct *)dm_void;
2074 u8 rts_ini_rate = ODM_RATE6M;
2075
2076 if (is_erp_protect) { /* use CCK rate as RTS*/
2077 rts_ini_rate = ODM_RATE1M;
2078 } else {
2079 switch (tx_rate) {
2080 case ODM_RATEVHTSS4MCS9:
2081 case ODM_RATEVHTSS4MCS8:
2082 case ODM_RATEVHTSS4MCS7:
2083 case ODM_RATEVHTSS4MCS6:
2084 case ODM_RATEVHTSS4MCS5:
2085 case ODM_RATEVHTSS4MCS4:
2086 case ODM_RATEVHTSS4MCS3:
2087 case ODM_RATEVHTSS3MCS9:
2088 case ODM_RATEVHTSS3MCS8:
2089 case ODM_RATEVHTSS3MCS7:
2090 case ODM_RATEVHTSS3MCS6:
2091 case ODM_RATEVHTSS3MCS5:
2092 case ODM_RATEVHTSS3MCS4:
2093 case ODM_RATEVHTSS3MCS3:
2094 case ODM_RATEVHTSS2MCS9:
2095 case ODM_RATEVHTSS2MCS8:
2096 case ODM_RATEVHTSS2MCS7:
2097 case ODM_RATEVHTSS2MCS6:
2098 case ODM_RATEVHTSS2MCS5:
2099 case ODM_RATEVHTSS2MCS4:
2100 case ODM_RATEVHTSS2MCS3:
2101 case ODM_RATEVHTSS1MCS9:
2102 case ODM_RATEVHTSS1MCS8:
2103 case ODM_RATEVHTSS1MCS7:
2104 case ODM_RATEVHTSS1MCS6:
2105 case ODM_RATEVHTSS1MCS5:
2106 case ODM_RATEVHTSS1MCS4:
2107 case ODM_RATEVHTSS1MCS3:
2108 case ODM_RATEMCS31:
2109 case ODM_RATEMCS30:
2110 case ODM_RATEMCS29:
2111 case ODM_RATEMCS28:
2112 case ODM_RATEMCS27:
2113 case ODM_RATEMCS23:
2114 case ODM_RATEMCS22:
2115 case ODM_RATEMCS21:
2116 case ODM_RATEMCS20:
2117 case ODM_RATEMCS19:
2118 case ODM_RATEMCS15:
2119 case ODM_RATEMCS14:
2120 case ODM_RATEMCS13:
2121 case ODM_RATEMCS12:
2122 case ODM_RATEMCS11:
2123 case ODM_RATEMCS7:
2124 case ODM_RATEMCS6:
2125 case ODM_RATEMCS5:
2126 case ODM_RATEMCS4:
2127 case ODM_RATEMCS3:
2128 case ODM_RATE54M:
2129 case ODM_RATE48M:
2130 case ODM_RATE36M:
2131 case ODM_RATE24M:
2132 rts_ini_rate = ODM_RATE24M;
2133 break;
2134 case ODM_RATEVHTSS4MCS2:
2135 case ODM_RATEVHTSS4MCS1:
2136 case ODM_RATEVHTSS3MCS2:
2137 case ODM_RATEVHTSS3MCS1:
2138 case ODM_RATEVHTSS2MCS2:
2139 case ODM_RATEVHTSS2MCS1:
2140 case ODM_RATEVHTSS1MCS2:
2141 case ODM_RATEVHTSS1MCS1:
2142 case ODM_RATEMCS26:
2143 case ODM_RATEMCS25:
2144 case ODM_RATEMCS18:
2145 case ODM_RATEMCS17:
2146 case ODM_RATEMCS10:
2147 case ODM_RATEMCS9:
2148 case ODM_RATEMCS2:
2149 case ODM_RATEMCS1:
2150 case ODM_RATE18M:
2151 case ODM_RATE12M:
2152 rts_ini_rate = ODM_RATE12M;
2153 break;
2154 case ODM_RATEVHTSS4MCS0:
2155 case ODM_RATEVHTSS3MCS0:
2156 case ODM_RATEVHTSS2MCS0:
2157 case ODM_RATEVHTSS1MCS0:
2158 case ODM_RATEMCS24:
2159 case ODM_RATEMCS16:
2160 case ODM_RATEMCS8:
2161 case ODM_RATEMCS0:
2162 case ODM_RATE9M:
2163 case ODM_RATE6M:
2164 rts_ini_rate = ODM_RATE6M;
2165 break;
2166 case ODM_RATE11M:
2167 case ODM_RATE5_5M:
2168 case ODM_RATE2M:
2169 case ODM_RATE1M:
2170 rts_ini_rate = ODM_RATE1M;
2171 break;
2172 default:
2173 rts_ini_rate = ODM_RATE6M;
2174 break;
2175 }
2176 }
2177
2178 if (*dm->band_type == ODM_BAND_5G) {
2179 if (rts_ini_rate < ODM_RATE6M)
2180 rts_ini_rate = ODM_RATE6M;
2181 }
2182 return rts_ini_rate;
2183 }
2184
2185 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2186
odm_refresh_basic_rate_mask(void * dm_void)2187 void odm_refresh_basic_rate_mask(
2188 void *dm_void)
2189 {
2190 struct dm_struct *dm = (struct dm_struct *)dm_void;
2191 void *adapter = dm->adapter;
2192 static u8 stage = 0;
2193 u8 cur_stage = 0;
2194 OCTET_STRING os_rate_set;
2195 PMGNT_INFO mgnt_info = GetDefaultMgntInfo(((PADAPTER)adapter));
2196 u8 rate_set[5] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M, MGN_6M};
2197
2198 if (dm->support_ic_type != ODM_RTL8812 && dm->support_ic_type != ODM_RTL8821)
2199 return;
2200
2201 if (dm->is_linked == false) /* unlink Default port information */
2202 cur_stage = 0;
2203 else if (dm->rssi_min < 40) /* @link RSSI < 40% */
2204 cur_stage = 1;
2205 else if (dm->rssi_min > 45) /* @link RSSI > 45% */
2206 cur_stage = 3;
2207 else
2208 cur_stage = 2; /* @link 25% <= RSSI <= 30% */
2209
2210 if (cur_stage != stage) {
2211 if (cur_stage == 1) {
2212 FillOctetString(os_rate_set, rate_set, 5);
2213 FilterSupportRate(mgnt_info->mBrates, &os_rate_set, false);
2214 phydm_set_hw_reg_handler_interface(dm, HW_VAR_BASIC_RATE, (u8 *)&os_rate_set);
2215 } else if (cur_stage == 3 && (stage == 1 || stage == 2))
2216 phydm_set_hw_reg_handler_interface(dm, HW_VAR_BASIC_RATE, (u8 *)(&mgnt_info->mBrates));
2217 }
2218
2219 stage = cur_stage;
2220 }
2221
2222 #endif
2223
2224 #if 0 /*@CONFIG_RA_DYNAMIC_RTY_LIMIT*/
2225
2226 void phydm_retry_limit_table_bound(
2227 void *dm_void,
2228 u8 *retry_limit,
2229 u8 offset)
2230 {
2231 struct dm_struct *dm = (struct dm_struct *)dm_void;
2232 struct ra_table *ra_tab = &dm->dm_ra_table;
2233
2234 if (*retry_limit > offset) {
2235 *retry_limit -= offset;
2236
2237 if (*retry_limit < ra_tab->retrylimit_low)
2238 *retry_limit = ra_tab->retrylimit_low;
2239 else if (*retry_limit > ra_tab->retrylimit_high)
2240 *retry_limit = ra_tab->retrylimit_high;
2241 } else
2242 *retry_limit = ra_tab->retrylimit_low;
2243 }
2244
2245 void phydm_reset_retry_limit_table(
2246 void *dm_void)
2247 {
2248 struct dm_struct *dm = (struct dm_struct *)dm_void;
2249 struct ra_table *ra_t = &dm->dm_ra_table;
2250 u8 i;
2251
2252 u8 per_rate_retrylimit_table_20M[ODM_RATEMCS15 + 1] = {
2253 1, 1, 2, 4, /*@CCK*/
2254 2, 2, 4, 6, 8, 12, 16, 18, /*OFDM*/
2255 2, 4, 6, 8, 12, 18, 20, 22, /*@20M HT-1SS*/
2256 2, 4, 6, 8, 12, 18, 20, 22 /*@20M HT-2SS*/
2257 };
2258 u8 per_rate_retrylimit_table_40M[ODM_RATEMCS15 + 1] = {
2259 1, 1, 2, 4, /*@CCK*/
2260 2, 2, 4, 6, 8, 12, 16, 18, /*OFDM*/
2261 4, 8, 12, 16, 24, 32, 32, 32, /*@40M HT-1SS*/
2262 4, 8, 12, 16, 24, 32, 32, 32 /*@40M HT-2SS*/
2263 };
2264
2265 memcpy(&ra_t->per_rate_retrylimit_20M[0],
2266 &per_rate_retrylimit_table_20M[0], PHY_NUM_RATE_IDX);
2267 memcpy(&ra_t->per_rate_retrylimit_40M[0],
2268 &per_rate_retrylimit_table_40M[0], PHY_NUM_RATE_IDX);
2269
2270 for (i = 0; i < PHY_NUM_RATE_IDX; i++) {
2271 phydm_retry_limit_table_bound(dm,
2272 &ra_t->per_rate_retrylimit_20M[i],
2273 0);
2274 phydm_retry_limit_table_bound(dm,
2275 &ra_t->per_rate_retrylimit_40M[i],
2276 0);
2277 }
2278 }
2279
2280 void phydm_ra_dynamic_retry_limit_init(
2281 void *dm_void)
2282 {
2283 struct dm_struct *dm = (struct dm_struct *)dm_void;
2284 struct ra_table *ra_tab = &dm->dm_ra_table;
2285
2286 ra_tab->retry_descend_num = RA_RETRY_DESCEND_NUM;
2287 ra_tab->retrylimit_low = RA_RETRY_LIMIT_LOW;
2288 ra_tab->retrylimit_high = RA_RETRY_LIMIT_HIGH;
2289
2290 phydm_reset_retry_limit_table(dm);
2291 }
2292
2293 void phydm_ra_dynamic_retry_limit(
2294 void *dm_void)
2295 {
2296 struct dm_struct *dm = (struct dm_struct *)dm_void;
2297 struct ra_table *ra_tab = &dm->dm_ra_table;
2298 u8 i, retry_offset;
2299 u32 ma_rx_tp;
2300
2301 if (dm->pre_number_active_client == dm->number_active_client) {
2302 PHYDM_DBG(dm, DBG_RA,
2303 "pre_number_active_client == number_active_client\n");
2304 return;
2305
2306 } else {
2307 if (dm->number_active_client == 1) {
2308 phydm_reset_retry_limit_table(dm);
2309 PHYDM_DBG(dm, DBG_RA,
2310 "one client only->reset to default value\n");
2311 } else {
2312 retry_offset = dm->number_active_client * ra_tab->retry_descend_num;
2313
2314 for (i = 0; i < PHY_NUM_RATE_IDX; i++) {
2315 phydm_retry_limit_table_bound(dm,
2316 &ra_tab->per_rate_retrylimit_20M[i],
2317 retry_offset);
2318 phydm_retry_limit_table_bound(dm,
2319 &ra_tab->per_rate_retrylimit_40M[i],
2320 retry_offset);
2321 }
2322 }
2323 }
2324 }
2325 #endif
2326
2327 #if 0 /*@CONFIG_RA_DYNAMIC_RATE_ID*/
2328 void phydm_ra_dynamic_rate_id_on_assoc(
2329 void *dm_void,
2330 u8 wireless_mode,
2331 u8 init_rate_id)
2332 {
2333 struct dm_struct *dm = (struct dm_struct *)dm_void;
2334
2335 PHYDM_DBG(dm, DBG_RA,
2336 "[ON ASSOC] rf_mode = ((0x%x)), wireless_mode = ((0x%x)), init_rate_id = ((0x%x))\n",
2337 dm->rf_type, wireless_mode, init_rate_id);
2338
2339 if (dm->rf_type == RF_2T2R || dm->rf_type == RF_2T3R || dm->rf_type == RF_2T4R) {
2340 if ((dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) &&
2341 (wireless_mode & (ODM_WM_N24G | ODM_WM_N5G))) {
2342 PHYDM_DBG(dm, DBG_RA,
2343 "[ON ASSOC] set N-2SS ARFR5 table\n");
2344 odm_set_mac_reg(dm, R_0x4a4, MASKDWORD, 0xfc1ffff); /*N-2SS, ARFR5, rate_id = 0xe*/
2345 odm_set_mac_reg(dm, R_0x4a8, MASKDWORD, 0x0); /*N-2SS, ARFR5, rate_id = 0xe*/
2346 } else if ((dm->support_ic_type & (ODM_RTL8812)) &&
2347 (wireless_mode & (ODM_WM_AC_5G | ODM_WM_AC_24G | ODM_WM_AC_ONLY))) {
2348 PHYDM_DBG(dm, DBG_RA,
2349 "[ON ASSOC] set AC-2SS ARFR0 table\n");
2350 odm_set_mac_reg(dm, R_0x444, MASKDWORD, 0x0fff); /*@AC-2SS, ARFR0, rate_id = 0x9*/
2351 odm_set_mac_reg(dm, R_0x448, MASKDWORD, 0xff01f000); /*@AC-2SS, ARFR0, rate_id = 0x9*/
2352 }
2353 }
2354 }
2355
2356 void phydm_ra_dynamic_rate_id_init(
2357 void *dm_void)
2358 {
2359 struct dm_struct *dm = (struct dm_struct *)dm_void;
2360
2361 if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) {
2362 odm_set_mac_reg(dm, R_0x4a4, MASKDWORD, 0xfc1ffff); /*N-2SS, ARFR5, rate_id = 0xe*/
2363 odm_set_mac_reg(dm, R_0x4a8, MASKDWORD, 0x0); /*N-2SS, ARFR5, rate_id = 0xe*/
2364
2365 odm_set_mac_reg(dm, R_0x444, MASKDWORD, 0x0fff); /*@AC-2SS, ARFR0, rate_id = 0x9*/
2366 odm_set_mac_reg(dm, R_0x448, MASKDWORD, 0xff01f000); /*@AC-2SS, ARFR0, rate_id = 0x9*/
2367 }
2368 }
2369
2370 void phydm_update_rate_id(
2371 void *dm_void,
2372 u8 rate,
2373 u8 platform_macid)
2374 {
2375 #if 0
2376
2377 struct dm_struct *dm = (struct dm_struct *)dm_void;
2378 struct ra_table *ra_tab = &dm->dm_ra_table;
2379 u8 current_tx_ss;
2380 u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/
2381 enum wireless_set wireless_set;
2382 u8 phydm_macid;
2383 struct cmn_sta_info *sta;
2384
2385 #if 0
2386 if (rate_idx >= ODM_RATEVHTSS2MCS0) {
2387 PHYDM_DBG(dm, DBG_RA, "rate[%d]: (( VHT2SS-MCS%d ))\n",
2388 platform_macid, (rate_idx - ODM_RATEVHTSS2MCS0));
2389 /*@dummy for SD4 check patch*/
2390 } else if (rate_idx >= ODM_RATEVHTSS1MCS0) {
2391 PHYDM_DBG(dm, DBG_RA, "rate[%d]: (( VHT1SS-MCS%d ))\n",
2392 platform_macid, (rate_idx - ODM_RATEVHTSS1MCS0));
2393 /*@dummy for SD4 check patch*/
2394 } else if (rate_idx >= ODM_RATEMCS0) {
2395 PHYDM_DBG(dm, DBG_RA, "rate[%d]: (( HT-MCS%d ))\n",
2396 platform_macid, (rate_idx - ODM_RATEMCS0));
2397 /*@dummy for SD4 check patch*/
2398 } else {
2399 PHYDM_DBG(dm, DBG_RA, "rate[%d]: (( HT-MCS%d ))\n",
2400 platform_macid, rate_idx);
2401 /*@dummy for SD4 check patch*/
2402 }
2403 #endif
2404
2405 phydm_macid = dm->phydm_macid_table[platform_macid];
2406 sta = dm->phydm_sta_info[phydm_macid];
2407
2408 if (is_sta_active(sta)) {
2409 wireless_set = sta->support_wireless_set;
2410
2411 if (dm->rf_type == RF_2T2R || dm->rf_type == RF_2T3R || dm->rf_type == RF_2T4R) {
2412 if (wireless_set & WIRELESS_HT) { /*N mode*/
2413 if (rate_idx >= ODM_RATEMCS8 && rate_idx <= ODM_RATEMCS15) { /*@2SS mode*/
2414
2415 sta->ra_info.rate_id = ARFR_5_RATE_ID;
2416 PHYDM_DBG(dm, DBG_RA, "ARFR_5\n");
2417 }
2418 } else if (wireless_set & WIRELESS_VHT) {/*@AC mode*/
2419 if (rate_idx >= ODM_RATEVHTSS2MCS0 && rate_idx <= ODM_RATEVHTSS2MCS9) {/*@2SS mode*/
2420
2421 sta->ra_info.rate_id = ARFR_0_RATE_ID;
2422 PHYDM_DBG(dm, DBG_RA, "ARFR_0\n");
2423 }
2424 } else
2425 sta->ra_info.rate_id = ARFR_0_RATE_ID;
2426
2427 PHYDM_DBG(dm, DBG_RA, "UPdate_RateID[%d]: (( 0x%x ))\n",
2428 platform_macid, sta->ra_info.rate_id);
2429 }
2430 }
2431 #endif
2432 }
2433
2434 #endif
2435