1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 #ifndef __PHYDMSOML_H__ 26 #define __PHYDMSOML_H__ 27 28 /*@#define ADAPTIVE_SOML_VERSION "1.0" Byte counter version*/ 29 #define ADAPTIVE_SOML_VERSION "2.0" /*@add avg. phy rate decision 20180126*/ 30 31 #define PHYDM_ADAPTIVE_SOML_IC (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F) 32 /*@jj add 20170822*/ 33 34 #define INIT_SOML_TIMMER 0 35 #define CANCEL_SOML_TIMMER 1 36 #define RELEASE_SOML_TIMMER 2 37 38 #define SOML_RSSI_TH_HIGH 25 39 #define SOML_RSSI_TH_LOW 20 40 41 #define HT_RATE_IDX 16 42 #define VHT_RATE_IDX 20 43 44 #define HT_ORDER_TYPE 3 45 #define VHT_ORDER_TYPE 4 46 47 #define CRC_FAIL 1 48 #define CRC_OK 0 49 50 #if 0 51 #define CFO_QPSK_TH 20 52 #define CFO_QAM16_TH 20 53 #define CFO_QAM64_TH 20 54 #define CFO_QAM256_TH 20 55 56 #define BPSK_QPSK_DIST 20 57 #define QAM16_DIST 30 58 #define QAM64_DIST 30 59 #define QAM256_DIST 20 60 #endif 61 #define HT_TYPE 1 62 #define VHT_TYPE 2 63 64 #define SOML_ON 1 65 #define SOML_OFF 0 66 67 #ifdef CONFIG_ADAPTIVE_SOML 68 69 struct adaptive_soml { 70 u32 rvrt_val; /*all rvrt_val for pause API must set to u32*/ 71 boolean is_soml_method_enable; 72 boolean get_stats; 73 u8 soml_on_off; 74 u8 soml_state_cnt; 75 u8 soml_delay_time; 76 u8 soml_intvl; 77 u8 soml_train_num; 78 u8 soml_counter; 79 u8 soml_period; 80 u8 soml_select; 81 u8 soml_last_state; 82 u8 cfo_qpsk_th; 83 u8 cfo_qam16_th; 84 u8 cfo_qam64_th; 85 u8 cfo_qam256_th; 86 u8 bpsk_qpsk_dist_th; 87 u8 qam16_dist_th; 88 u8 qam64_dist_th; 89 u8 qam256_dist_th; 90 u8 cfo_cnt; 91 s32 cfo_diff_a; 92 s32 cfo_diff_b; 93 s32 cfo_diff_sum_a; 94 s32 cfo_diff_sum_b; 95 s32 cfo_diff_avg_a; 96 s32 cfo_diff_avg_b; 97 u16 ht_cnt[HT_RATE_IDX]; 98 u16 pre_ht_cnt[HT_RATE_IDX]; 99 u16 ht_cnt_on[HT_RATE_IDX]; 100 u16 ht_cnt_off[HT_RATE_IDX]; 101 u16 ht_crc_ok_cnt_on[HT_RATE_IDX]; 102 u16 ht_crc_fail_cnt_on[HT_RATE_IDX]; 103 u16 ht_crc_ok_cnt_off[HT_RATE_IDX]; 104 u16 ht_crc_fail_cnt_off[HT_RATE_IDX]; 105 u16 vht_crc_ok_cnt_on[VHT_RATE_IDX]; 106 u16 vht_crc_fail_cnt_on[VHT_RATE_IDX]; 107 u16 vht_crc_ok_cnt_off[VHT_RATE_IDX]; 108 u16 vht_crc_fail_cnt_off[VHT_RATE_IDX]; 109 110 u16 vht_cnt[VHT_RATE_IDX]; 111 u16 pre_vht_cnt[VHT_RATE_IDX]; 112 u16 vht_cnt_on[VHT_RATE_IDX]; 113 u16 vht_cnt_off[VHT_RATE_IDX]; 114 115 u16 num_ht_qam[HT_ORDER_TYPE]; 116 u16 ht_byte[HT_RATE_IDX]; 117 u16 pre_ht_byte[HT_RATE_IDX]; 118 u16 ht_byte_on[HT_RATE_IDX]; 119 u16 ht_byte_off[HT_RATE_IDX]; 120 u16 num_vht_qam[VHT_ORDER_TYPE]; 121 u16 vht_byte[VHT_RATE_IDX]; 122 u16 pre_vht_byte[VHT_RATE_IDX]; 123 u16 vht_byte_on[VHT_RATE_IDX]; 124 u16 vht_byte_off[VHT_RATE_IDX]; 125 126 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 127 #if USE_WORKITEM 128 RT_WORK_ITEM phydm_adaptive_soml_workitem; 129 #endif 130 #endif 131 struct phydm_timer_list phydm_adaptive_soml_timer; 132 133 }; 134 135 enum qam_order { 136 BPSK_QPSK = 0, 137 QAM16 = 1, 138 QAM64 = 2, 139 QAM256 = 3 140 }; 141 142 void phydm_dynamicsoftmletting(void *dm_void); 143 144 void phydm_soml_on_off(void *dm_void, u8 swch); 145 146 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 147 void phydm_adaptive_soml_callback(struct phydm_timer_list *timer); 148 149 void phydm_adaptive_soml_workitem_callback(void *context); 150 151 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) 152 void phydm_adaptive_soml_callback(void *dm_void); 153 154 void phydm_adaptive_soml_workitem_callback(void *context); 155 156 #else 157 void phydm_adaptive_soml_callback(void *dm_void); 158 #endif 159 160 void phydm_rx_rate_for_soml(void *dm_void, void *pkt_info_void); 161 162 void phydm_rx_qam_for_soml(void *dm_void, void *pkt_info_void); 163 164 void phydm_soml_reset_rx_rate(void *dm_void); 165 166 void phydm_soml_reset_qam(void *dm_void); 167 168 void phydm_soml_cfo_process(void *dm_void, s32 *diff_a, s32 *diff_b); 169 170 void phydm_soml_debug(void *dm_void, char input[][16], u32 *_used, 171 char *output, u32 *_out_len); 172 173 void phydm_soml_statistics(void *dm_void, u8 on_off_state); 174 175 void phydm_adsl(void *dm_void); 176 177 void phydm_adaptive_soml_reset(void *dm_void); 178 179 void phydm_set_adsl_val(void *dm_void, u32 *val_buf, u8 val_len); 180 181 void phydm_soml_crc_acq(void *dm_void, u8 rate_id, boolean crc32, u32 length); 182 183 void phydm_soml_bytes_acq(void *dm_void, u8 rate_id, u32 length); 184 185 void phydm_adaptive_soml_timers(void *dm_void, u8 state); 186 187 void phydm_adaptive_soml_init(void *dm_void); 188 189 void phydm_adaptive_soml(void *dm_void); 190 191 void phydm_enable_adaptive_soml(void *dm_void); 192 193 void phydm_stop_adaptive_soml(void *dm_void); 194 195 void phydm_adaptive_soml_para_set(void *dm_void, u8 train_num, u8 intvl, 196 u8 period, u8 delay_time); 197 #endif 198 void phydm_init_soft_ml_setting(void *dm_void); 199 #endif /*@#ifndef __PHYDMSOML_H__*/ 200