1 /* 2 * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved. 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 /**************************************************************************//** 18 * @file soc.h 19 * @brief CSI Core Peripheral Access Layer Header File for 20 * CSKYSOC Device Series 21 * @version V1.0 22 * @date 02. June 2017 23 ******************************************************************************/ 24 25 #ifndef _SOC_H_ 26 #define _SOC_H_ 27 28 #include <stdint.h> 29 #include <csi_core.h> 30 #include <sys_freq.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #ifndef IHS_VALUE 37 #define IHS_VALUE (20000000) 38 #endif 39 40 #ifndef EHS_VALUE 41 #define EHS_VALUE (20000000) 42 #endif 43 44 /* ------------------------- Interrupt Number Definition ------------------------ */ 45 46 typedef enum IRQn { 47 /* ---------------------- SmartL Specific Interrupt Numbers --------------------- */ 48 UART_IRQn = 0, /* uart Interrupt */ 49 CORET_IRQn = 1, /* core Timer Interrupt */ 50 TIM0_IRQn = 2, /* timer0 Interrupt */ 51 TIM1_IRQn = 3, /* timer1 Interrupt */ 52 TIM2_IRQn = 4, /* timer1 Interrupt */ 53 TIM3_IRQn = 5, /* timer1 Interrupt */ 54 GPIO0_IRQn = 7, /* gpio0 Interrupt */ 55 GPIO1_IRQn = 8, /* gpio1 Interrupt */ 56 GPIO2_IRQn = 9, /* gpio2 Interrupt */ 57 GPIO3_IRQn = 10, /* gpio3 Interrupt */ 58 GPIO4_IRQn = 11, /* gpio4 Interrupt */ 59 GPIO5_IRQn = 12, /* gpio5 Interrupt */ 60 GPIO6_IRQn = 13, /* gpio6 Interrupt */ 61 GPIO7_IRQn = 14, /* gpio7 Interrupt */ 62 STIM0_IRQn = 16, /* stimer0 Interrupt */ 63 STIM1_IRQn = 17, /* stimer0 Interrupt */ 64 STIM2_IRQn = 18, /* stimer0 Interrupt */ 65 STIM3_IRQn = 19, /* stimer0 Interrupt */ 66 PAD_IRQn = 20, /* pad Interrupt */ 67 } 68 IRQn_Type; 69 70 /* ================================================================================ */ 71 /* ================ Device Specific Peripheral Section ================ */ 72 /* ================================================================================ */ 73 74 #define CONFIG_TIMER_NUM 4 75 #define CONFIG_USART_NUM 1 76 #define CONFIG_GPIO_NUM 8 77 #define CONFIG_GPIO_PIN_NUM 8 78 79 /* ================================================================================ */ 80 /* ================ Peripheral memory map ================ */ 81 /* ================================================================================ */ 82 /* -------------------------- CPU FPGA memory map ------------------------------- */ 83 #define CSKY_SRAM_BASE (0x20000000UL) 84 85 #define CSKY_UART_BASE (0x40015000UL) 86 #define CSKY_PMU_BASE (0x40016000UL) 87 #define CSKY_TIMER0_BASE (0x40011000UL) 88 #define CSKY_TIMER1_BASE (0x40011014UL) 89 #define CSKY_TIMER2_BASE (0x40011028UL) 90 #define CSKY_TIMER3_BASE (0x4001103cUL) 91 #define CSKY_TIMER_CONTROL_BASE (0x400110a0UL) 92 #define CSKY_CLK_GEN_BASE (0x40017000UL) 93 #define CSKY_STIMER0_BASE (0x40018000UL) 94 #define CSKY_STIMER1_BASE (0x40018014UL) 95 #define CSKY_STIMER2_BASE (0x40018028UL) 96 #define CSKY_STIMER3_BASE (0x4001803cUL) 97 #define CSKY_STIMER_CONTROL_BASE (0x400110a0UL) 98 99 #define CSKY_GPIOA_BASE (0x40019000UL) 100 #define CSKY_GPIOA_CONTROL_BASE (0x40019030UL) 101 #define CSKY_SMPU_BASE (0x4001a000UL) 102 103 /* ================================================================================ */ 104 /* ================ Peripheral declaration ================ */ 105 /* ================================================================================ */ 106 #define CSKY_UART (( CSKY_UART_TypeDef *) CSKY_UART_BASE) 107 108 #ifdef __cplusplus 109 } 110 #endif 111 112 #endif /* _SOC_H_ */ 113