1 /*
2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without modification,
6 * are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice, this list of
9 * conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice, this list
12 * of conditions and the following disclaimer in the documentation and/or other materials
13 * provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its contributors may be used
16 * to endorse or promote products derived from this software without specific prior written
17 * permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include "amba_pl011.h"
33 #include "los_event.h"
34 #include "los_task_pri.h"
35
36 EVENT_CB_S g_stShellEvent;
37
38 CHAR g_inputCmd[CMD_LENGTH];
39 INT32 g_inputIdx = 0;
40 #ifdef LOSCFG_QUICK_START
41 __attribute__ ((section(".data"))) UINT32 g_uart_fputc_en = 0;
42 #else
43 __attribute__ ((section(".data"))) UINT32 g_uart_fputc_en = 1;
44 #endif
45
46 #define REG32(addr) ((volatile UINT32 *)(UINTPTR)(addr))
47 #define UARTREG(base, reg) (*REG32((base) + (reg)))
48 #define UART_FR_TXFF (0x1U << 5)
49
UartPutcReg(UINTPTR base,CHAR c)50 STATIC VOID UartPutcReg(UINTPTR base, CHAR c)
51 {
52 /* Spin while fifo is full */
53 while (UARTREG(base, UART_FR) & UART_FR_TXFF) {}
54 UARTREG(base, UART_DR) = c;
55 }
56
uart_to_ptr(UINTPTR n)57 STATIC INLINE UINTPTR uart_to_ptr(UINTPTR n)
58 {
59 (VOID)n;
60 return UART_REG_BASE;
61 }
62
uart_putc(INT32 port,CHAR c)63 INT32 uart_putc(INT32 port, CHAR c)
64 {
65 UINTPTR base = uart_to_ptr((UINT32)port);
66 UartPutcReg(base, c);
67 return 1;
68 }
69
uart_fputc(CHAR c,VOID * f)70 CHAR uart_fputc(CHAR c, VOID *f)
71 {
72 (VOID)f;
73 if (g_uart_fputc_en == 1) {
74 if (c == '\n') {
75 (VOID)uart_putc(0, '\r');
76 }
77 return (uart_putc(0, (c)));
78 } else {
79 return 0;
80 }
81 }
82
83 LITE_OS_SEC_BSS STATIC SPIN_LOCK_INIT(g_uartOutputSpin);
84
UartPutStr(UINTPTR base,const CHAR * s,UINT32 len)85 STATIC VOID UartPutStr(UINTPTR base, const CHAR *s, UINT32 len)
86 {
87 UINT32 i;
88
89 for (i = 0; i < len; i++) {
90 if (*(s + i) == '\n') {
91 UartPutcReg(base, '\r');
92 }
93 UartPutcReg(base, *(s + i));
94 }
95 }
96
UartPutsReg(UINTPTR base,const CHAR * s,UINT32 len,BOOL isLock)97 UINT32 UartPutsReg(UINTPTR base, const CHAR *s, UINT32 len, BOOL isLock)
98 {
99 UINT32 intSave;
100
101 if (g_uart_fputc_en == 0) {
102 return 0;
103 }
104
105 if (isLock) {
106 LOS_SpinLockSave(&g_uartOutputSpin, &intSave);
107 UartPutStr(base, s, len);
108 LOS_SpinUnlockRestore(&g_uartOutputSpin, intSave);
109 } else {
110 UartPutStr(base, s, len);
111 }
112
113 return len;
114 }
115
UartPuts(const CHAR * s,UINT32 len,BOOL isLock)116 VOID UartPuts(const CHAR *s, UINT32 len, BOOL isLock)
117 {
118 UINTPTR base = uart_to_ptr(0);
119 (VOID)UartPutsReg(base, s, len, isLock);
120 }
121
uart_puts(const CHAR * s,UINTPTR len,VOID * state)122 INT32 uart_puts(const CHAR *s, UINTPTR len, VOID *state)
123 {
124 (VOID)state;
125 UINTPTR i;
126
127 for (i = 0; i < len; i++) {
128 if (*(s + i) != '\0') {
129 if (*(s + i) == '\n') {
130 (VOID)uart_fputc('\r', NULL);
131 }
132
133 (VOID)uart_fputc(*(s + i), NULL);
134 }
135 }
136
137 return (INT32)len;
138 }
139
uart_handler(VOID)140 VOID uart_handler(VOID)
141 {
142 CHAR c;
143 UINTPTR base = uart_to_ptr(0);
144
145 c = UARTREG(base, UART_DR);
146
147 switch (c) {
148 case '\r':
149 case '\n':
150 if (g_inputIdx < CMD_LENGTH - 1) {
151 g_inputCmd[g_inputIdx++] = '\0';
152 LOS_EventWrite(&g_stShellEvent, 0x1);
153 (VOID)uart_putc(0, '\r');
154 (VOID)uart_putc(0, '\n');
155 }
156 break;
157 case 0x8: /* backspace */
158 case 0x7f: /* delete */
159 if (g_inputIdx > 0) {
160 g_inputIdx--;
161 (VOID)uart_putc(0, '\b');
162 (VOID)uart_putc(0, ' ');
163 (VOID)uart_putc(0, '\b');
164 }
165 break;
166 default:
167 if (g_inputIdx < CMD_LENGTH - 1) {
168 (VOID)uart_putc(0, c);
169 g_inputCmd[g_inputIdx++] = c;
170 }
171 }
172 }
173
uart_early_init(VOID)174 VOID uart_early_init(VOID)
175 {
176 /* enable uart transmit */
177 UARTREG(UART_REG_BASE, UART_CR) = (1 << 8) | (1 << 0);
178 }
179
uart_init(VOID)180 VOID uart_init(VOID)
181 {
182 UINT32 ret;
183
184 /* uart interrupt priority should be the highest in interrupt preemption mode */
185 ret = LOS_HwiCreate(NUM_HAL_INTERRUPT_UART, 0, 0, (HWI_PROC_FUNC)uart_handler, NULL);
186 if (ret != LOS_OK) {
187 PRINT_ERR("%s,%d, uart interrupt created error:%x\n", __FUNCTION__, __LINE__, ret);
188 } else {
189 /* clear all irqs */
190 UARTREG(UART_REG_BASE, UART_ICR) = 0x3ff;
191
192 /* set fifo trigger level */
193 UARTREG(UART_REG_BASE, UART_IFLS) = 0;
194
195 /* enable rx interrupt */
196 UARTREG(UART_REG_BASE, UART_IMSC) = (1 << 4 | 1 << 6);
197
198 /* enable receive */
199 UARTREG(UART_REG_BASE, UART_CR) |= (1 << 9);
200
201 HalIrqUnmask(NUM_HAL_INTERRUPT_UART);
202 }
203 }
204