1 /* 2 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef _TARGET_CONFIG_H 17 #define _TARGET_CONFIG_H 18 19 20 #ifdef __cplusplus 21 #if __cplusplus 22 extern "C" { 23 #endif /* __cplusplus */ 24 #endif /* __cplusplus */ 25 #define IRQ_SPI_BASE 32 26 27 #define OS_SYS_CLOCK 50000000 28 #define SYS_CTRL_REG_BASE IO_DEVICE_ADDR(0x12020000) 29 #define REG_SC_CTRL 0 30 31 /* memory */ 32 #define CACHE_ALIGNED_SIZE 64 33 34 /* physical memory base and size */ 35 #define DDR_MEM_ADDR 0x40000000 36 #define DDR_MEM_SIZE 0x40000000 37 38 /* Peripheral register address base and size */ 39 #define PERIPH_PMM_BASE 0x00000000 40 #define PERIPH_PMM_SIZE 0x0F000000 41 42 #define SYS_MEM_SIZE_DEFAULT 0x4000000 43 44 45 /* hwi */ 46 /** 47 * Maximum number of supported hardware devices that generate hardware interrupts. 48 * The maximum number of hardware devices that generate hardware interrupts is 128. 49 */ 50 #define OS_HWI_MAX_NUM 96 51 52 /** 53 * Maximum interrupt number. 54 */ 55 #define OS_HWI_MAX ((OS_HWI_MAX_NUM) - 1) 56 57 /** 58 * Minimum interrupt number. 59 */ 60 #define OS_HWI_MIN 0 61 /** 62 * Maximum usable interrupt number. 63 */ 64 #define OS_USER_HWI_MAX OS_HWI_MAX 65 /** 66 * Minimum usable interrupt number. 67 */ 68 #define OS_USER_HWI_MIN OS_HWI_MIN 69 70 #define NUM_HAL_INTERRUPT_CNTPSIRQ (IRQ_PPI_BASE + 13) 71 #define NUM_HAL_INTERRUPT_CNTPNSIRQ (IRQ_PPI_BASE + 14) 72 #define OS_TICK_INT_NUM NUM_HAL_INTERRUPT_CNTPSIRQ // use secure physical timer for now 73 #define NUM_HAL_INTERRUPT_TIMER0 37 74 #define NUM_HAL_INTERRUPT_TIMER3 38 75 #define NUM_HAL_INTERRUPT_UART0 (IRQ_SPI_BASE + 1) 76 77 /* gic config */ 78 #define IRQ_PPI_BASE 16 79 #define GIC_BASE_ADDR IO_DEVICE_ADDR(0x08000000) 80 #define GICD_OFFSET 0x00000 /* interrupt distributor offset */ 81 #define GICC_OFFSET 0x10000 /* CPU interface register offset */ 82 83 /* timer config */ 84 #define BIT(n) (1U << (n)) 85 #define TIMER0_ENABLE BIT(16) 86 #define TIMER1_ENABLE BIT(17) 87 #define TIMER2_ENABLE BIT(18) 88 #define TIMER3_ENABLE BIT(19) 89 90 #define TIMER0_REG_BASE IO_DEVICE_ADDR(0x12000000) 91 #define TIMER1_REG_BASE IO_DEVICE_ADDR(0x12000020) 92 #define TIMER2_REG_BASE IO_DEVICE_ADDR(0x12001000) 93 #define TIMER3_REG_BASE IO_DEVICE_ADDR(0x12001020) 94 95 #define TIMER_TICK_REG_BASE TIMER0_REG_BASE /* timer for tick */ 96 #define TIMER_TICK_ENABLE TIMER0_ENABLE 97 #define TIMER_TIME_REG_BASE TIMER1_REG_BASE /* timer for time */ 98 #define TIMER_TIME_ENABLE TIMER1_ENABLE 99 #define HRTIMER_TIMER_REG_BASE TIMER3_REG_BASE /* timer for hrtimer */ 100 #define HRTIMER_TIMER_ENABLE TIMER3_ENABLE 101 102 #define NUM_HAL_INTERRUPT_TIMER NUM_HAL_INTERRUPT_TIMER0 103 #define NUM_HAL_INTERRUPT_HRTIMER NUM_HAL_INTERRUPT_TIMER3 104 105 #define TIMER_LOAD 0x0 106 #define TIMER_VALUE 0x4 107 #define TIMER_CONTROL 0x8 108 #define TIMER_INT_CLR 0xc 109 #define TIMER_RIS 0x10 110 #define TIMER_MIS 0x14 111 #define TIMER_BGLOAD 0x18 112 113 /* uart config */ 114 #define UART0_REG_BASE IO_DEVICE_ADDR(0x09000000) 115 #define TTY_DEVICE "/dev/uartdev-0" 116 #define UART_REG_BASE UART0_REG_BASE 117 #define NUM_HAL_INTERRUPT_UART NUM_HAL_INTERRUPT_UART0 118 119 #ifdef __cplusplus 120 #if __cplusplus 121 } 122 #endif /* __cplusplus */ 123 #endif /* __cplusplus */ 124 125 #endif 126