1 /* 2 * Copyright (C) 2016 Rockchip Electronics Co., Ltd. 3 * Authors: 4 * Zhiqin Wei <wzq@rock-chips.com> 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 */ 18 19 #ifndef RGA_DRIVER_H 20 #define RGA_DRIVER_H 21 #include <stdint.h> 22 #ifdef __cplusplus 23 extern "C" 24 { 25 #endif 26 27 #define RGA_BLIT_SYNC 0x5017 28 #define RGA_BLIT_ASYNC 0x5018 29 #define RGA_FLUSH 0x5019 30 #define RGA_GET_RESULT 0x501a 31 #define RGA_GET_VERSION 0x501b 32 33 #define RGA2_BLIT_SYNC 0x6017 34 #define RGA2_BLIT_ASYNC 0x6018 35 #define RGA2_FLUSH 0x6019 36 #define RGA2_GET_RESULT 0x601a 37 #define RGA2_GET_VERSION 0x601b 38 #define RGA2_GET_VERSION 0x601b 39 40 #define RGA_REG_CTRL_LEN 0x8 /* 8 */ 41 #define RGA_REG_CMD_LEN 0x1c /* 28 */ 42 #define RGA_CMD_BUF_SIZE 0x700 /* 16*28*4 */ 43 44 #ifndef ENABLE 45 #define ENABLE 1 46 #endif 47 48 #ifndef DISABLE 49 #define DISABLE 0 50 #endif 51 52 /* RGA process mode enum */ 53 enum { 54 bitblt_mode = 0x0, 55 color_palette_mode = 0x1, 56 color_fill_mode = 0x2, 57 line_point_drawing_mode = 0x3, 58 blur_sharp_filter_mode = 0x4, 59 pre_scaling_mode = 0x5, 60 update_palette_table_mode = 0x6, 61 update_patten_buff_mode = 0x7, 62 }; 63 64 enum { 65 rop_enable_mask = 0x2, 66 dither_enable_mask = 0x8, 67 fading_enable_mask = 0x10, 68 PD_enbale_mask = 0x20, 69 }; 70 71 enum { 72 yuv2rgb_mode0 = 0x0, /* BT.601 MPEG */ 73 yuv2rgb_mode1 = 0x1, /* BT.601 JPEG */ 74 yuv2rgb_mode2 = 0x2, /* BT.709 */ 75 76 rgb2yuv_601_full = 0x1 << 8, 77 rgb2yuv_709_full = 0x2 << 8, 78 yuv2yuv_601_limit_2_709_limit = 0x3 << 8, 79 yuv2yuv_601_limit_2_709_full = 0x4 << 8, 80 yuv2yuv_709_limit_2_601_limit = 0x5 << 8, 81 yuv2yuv_709_limit_2_601_full = 0x6 << 8, // not support 82 yuv2yuv_601_full_2_709_limit = 0x7 << 8, 83 yuv2yuv_601_full_2_709_full = 0x8 << 8, // not support 84 yuv2yuv_709_full_2_601_limit = 0x9 << 8, // not support 85 yuv2yuv_709_full_2_601_full = 0xa << 8, // not support 86 full_csc_mask = 0xf00, 87 }; 88 89 /* RGA rotate mode */ 90 enum { 91 rotate_mode0 = 0x0, /* no rotate */ 92 rotate_mode1 = 0x1, /* rotate */ 93 rotate_mode2 = 0x2, /* x_mirror */ 94 rotate_mode3 = 0x3, /* y_mirror */ 95 }; 96 97 enum { 98 color_palette_mode0 = 0x0, /* 1K */ 99 color_palette_mode1 = 0x1, /* 2K */ 100 color_palette_mode2 = 0x2, /* 4K */ 101 color_palette_mode3 = 0x3, /* 8K */ 102 }; 103 104 enum { 105 BB_BYPASS = 0x0, /* no rotate */ 106 BB_ROTATE = 0x1, /* rotate */ 107 BB_X_MIRROR = 0x2, /* x_mirror */ 108 BB_Y_MIRROR = 0x3 /* y_mirror */ 109 }; 110 111 enum { 112 nearby = 0x0, /* no rotate */ 113 bilinear = 0x1, /* rotate */ 114 bicubic = 0x2, /* x_mirror */ 115 }; 116 117 /* 118 // Alpha Red Green Blue 119 { 4, 32, {{32,24, 8, 0, 16, 8, 24,16 }}, GGL_RGBA }, // RK_FORMAT_RGBA_8888 120 { 4, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGBX_8888 121 { 3, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGB_888 122 { 4, 32, {{32,24, 24,16, 16, 8, 8, 0 }}, GGL_BGRA }, // RK_FORMAT_BGRA_8888 123 { 2, 16, {{ 0, 0, 16,11, 11, 5, 5, 0 }}, GGL_RGB }, // RK_FORMAT_RGB_565 124 { 2, 16, {{ 1, 0, 16,11, 11, 6, 6, 1 }}, GGL_RGBA }, // RK_FORMAT_RGBA_5551 125 { 2, 16, {{ 4, 0, 16,12, 12, 8, 8, 4 }}, GGL_RGBA }, // RK_FORMAT_RGBA_4444 126 { 3, 24, {{ 0, 0, 24,16, 16, 8, 8, 0 }}, GGL_BGR }, // RK_FORMAT_BGB_888 127 128 */ 129 /* In order to be compatible with RK_FORMAT_XX and HAL_PIXEL_FORMAT_XX, 130 * RK_FORMAT_XX is shifted to the left by 8 bits to distinguish. */ 131 typedef enum _Rga_SURF_FORMAT { 132 RK_FORMAT_RGBA_8888 = 0x0 << 8, 133 RK_FORMAT_RGBX_8888 = 0x1 << 8, 134 RK_FORMAT_RGB_888 = 0x2 << 8, 135 RK_FORMAT_BGRA_8888 = 0x3 << 8, 136 RK_FORMAT_RGB_565 = 0x4 << 8, 137 RK_FORMAT_RGBA_5551 = 0x5 << 8, 138 RK_FORMAT_RGBA_4444 = 0x6 << 8, 139 RK_FORMAT_BGR_888 = 0x7 << 8, 140 141 RK_FORMAT_YCbCr_422_SP = 0x8 << 8, 142 RK_FORMAT_YCbCr_422_P = 0x9 << 8, 143 RK_FORMAT_YCbCr_420_SP = 0xa << 8, 144 RK_FORMAT_YCbCr_420_P = 0xb << 8, 145 146 RK_FORMAT_YCrCb_422_SP = 0xc << 8, 147 RK_FORMAT_YCrCb_422_P = 0xd << 8, 148 RK_FORMAT_YCrCb_420_SP = 0xe << 8, 149 RK_FORMAT_YCrCb_420_P = 0xf << 8, 150 151 RK_FORMAT_BPP1 = 0x10 << 8, 152 RK_FORMAT_BPP2 = 0x11 << 8, 153 RK_FORMAT_BPP4 = 0x12 << 8, 154 RK_FORMAT_BPP8 = 0x13 << 8, 155 156 RK_FORMAT_Y4 = 0x14 << 8, 157 RK_FORMAT_YCbCr_400 = 0x15 << 8, 158 159 RK_FORMAT_BGRX_8888 = 0x16 << 8, 160 161 RK_FORMAT_YVYU_422 = 0x18 << 8, 162 RK_FORMAT_YVYU_420 = 0x19 << 8, 163 RK_FORMAT_VYUY_422 = 0x1a << 8, 164 RK_FORMAT_VYUY_420 = 0x1b << 8, 165 RK_FORMAT_YUYV_422 = 0x1c << 8, 166 RK_FORMAT_YUYV_420 = 0x1d << 8, 167 RK_FORMAT_UYVY_422 = 0x1e << 8, 168 RK_FORMAT_UYVY_420 = 0x1f << 8, 169 170 RK_FORMAT_YCbCr_420_SP_10B = 0x20 << 8, 171 RK_FORMAT_YCrCb_420_SP_10B = 0x21 << 8, 172 RK_FORMAT_YCbCr_422_10b_SP = 0x22 << 8, 173 RK_FORMAT_YCrCb_422_10b_SP = 0x23 << 8, 174 175 RK_FORMAT_BGR_565 = 0x24 << 8, 176 RK_FORMAT_BGRA_5551 = 0x25 << 8, 177 RK_FORMAT_BGRA_4444 = 0x26 << 8, 178 RK_FORMAT_UNKNOWN = 0x100 << 8, 179 } RgaSURF_FORMAT; 180 181 182 typedef struct rga_img_info_t { 183 #if defined(__arm64__) || defined(__aarch64__) 184 unsigned long yrgb_addr; /* yrgb mem addr */ 185 unsigned long uv_addr; /* cb/cr mem addr */ 186 unsigned long v_addr; /* cr mem addr */ 187 #else 188 unsigned int yrgb_addr; /* yrgb mem addr */ 189 unsigned int uv_addr; /* cb/cr mem addr */ 190 unsigned int v_addr; /* cr mem addr */ 191 #endif 192 unsigned int format; // definition by RK_FORMAT 193 unsigned short act_w; 194 unsigned short act_h; 195 unsigned short x_offset; 196 unsigned short y_offset; 197 198 unsigned short vir_w; 199 unsigned short vir_h; 200 201 unsigned short endian_mode; // for BPP 202 unsigned short alpha_swap; 203 } 204 rga_img_info_t; 205 206 207 typedef struct mdp_img_act { 208 unsigned short w; // width 209 unsigned short h; // height 210 short x_off; // x offset for the vir 211 short y_off; // y offset for the vir 212 } 213 mdp_img_act; 214 215 216 typedef struct RANGE { 217 unsigned short min; 218 unsigned short max; 219 } 220 RANGE; 221 222 typedef struct POINT { 223 unsigned short x; 224 unsigned short y; 225 } 226 POINT; 227 228 typedef struct RECT { 229 unsigned short xmin; 230 unsigned short xmax; // width - 1 231 unsigned short ymin; 232 unsigned short ymax; // height - 1 233 } RECT; 234 235 typedef struct RGB { 236 unsigned char r; 237 unsigned char g; 238 unsigned char b; 239 unsigned char res; 240 }RGB; 241 242 243 typedef struct MMU { 244 unsigned char mmu_en; 245 #if defined(__arm64__) || defined(__aarch64__) 246 unsigned long base_addr; 247 #else 248 unsigned int base_addr; 249 #endif 250 unsigned int mmu_flag; /* [0] mmu enable [1] src_flush [2] dst_flush [3] CMD_flush [4~5] page size */ 251 } MMU; 252 253 typedef struct COLOR_FILL { 254 short gr_x_a; 255 short gr_y_a; 256 short gr_x_b; 257 short gr_y_b; 258 short gr_x_g; 259 short gr_y_g; 260 short gr_x_r; 261 short gr_y_r; 262 } 263 COLOR_FILL; 264 265 typedef struct FADING { 266 unsigned char b; 267 unsigned char g; 268 unsigned char r; 269 unsigned char res; 270 } 271 FADING; 272 273 typedef struct line_draw_t { 274 POINT start_point; /* LineDraw_start_point */ 275 POINT end_point; /* LineDraw_end_point */ 276 unsigned int color; /* LineDraw_color */ 277 unsigned int flag; /* (enum) LineDrawing mode sel */ 278 unsigned int line_width; /* range 1~16 */ 279 } 280 line_draw_t; 281 282 /* color space convert coefficient. */ 283 typedef struct csc_coe_t { 284 int16_t r_v; 285 int16_t g_y; 286 int16_t b_u; 287 int32_t off; 288 } csc_coe_t; 289 290 typedef struct full_csc_t { 291 unsigned char flag; 292 csc_coe_t coe_y; 293 csc_coe_t coe_u; 294 csc_coe_t coe_v; 295 } full_csc_t; 296 297 struct rga_req { 298 unsigned char render_mode; /* (enum) process mode sel */ 299 300 rga_img_info_t src; /* src image info */ 301 rga_img_info_t dst; /* dst image info */ 302 rga_img_info_t pat; /* patten image info */ 303 304 #if defined(__arm64__) || defined(__aarch64__) 305 unsigned long rop_mask_addr; /* rop4 mask addr */ 306 unsigned long LUT_addr; /* LUT addr */ 307 #else 308 unsigned int rop_mask_addr; /* rop4 mask addr */ 309 unsigned int LUT_addr; /* LUT addr */ 310 #endif 311 312 RECT clip; /* dst clip window default value is dst_vir */ 313 /* value from [0, w-1] / [0, h-1] */ 314 315 int sina; /* dst angle default value 0 16.16 scan from table */ 316 int cosa; /* dst angle default value 0 16.16 scan from table */ 317 318 unsigned short alpha_rop_flag; /* alpha rop process flag */ 319 /* ([0] = 1 alpha_rop_enable) */ 320 /* ([1] = 1 rop enable) */ 321 /* ([2] = 1 fading_enable) */ 322 /* ([3] = 1 PD_enable) */ 323 /* ([4] = 1 alpha cal_mode_sel) */ 324 /* ([5] = 1 dither_enable) */ 325 /* ([6] = 1 gradient fill mode sel) */ 326 /* ([7] = 1 AA_enable) */ 327 /* ([8] = 1 nn_quantize) */ 328 /* ([9] = 1 Real color mode) */ 329 330 unsigned char scale_mode; /* 0 nearst / 1 bilnear / 2 bicubic */ 331 332 unsigned int color_key_max; /* color key max */ 333 unsigned int color_key_min; /* color key min */ 334 335 unsigned int fg_color; /* foreground color */ 336 unsigned int bg_color; /* background color */ 337 338 COLOR_FILL gr_color; /* color fill use gradient */ 339 340 line_draw_t line_draw_info; 341 342 FADING fading; 343 344 unsigned char PD_mode; /* porter duff alpha mode sel */ 345 346 unsigned char alpha_global_value; /* global alpha value */ 347 348 unsigned short rop_code; /* rop2/3/4 code scan from rop code table */ 349 350 unsigned char bsfilter_flag; /* [2] 0 blur 1 sharp / [1:0] filter_type */ 351 352 unsigned char palette_mode; /* (enum) color palatte 0/1bpp, 1/2bpp 2/4bpp 3/8bpp */ 353 354 unsigned char yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */ 355 356 unsigned char endian_mode; /* 0/big endian 1/little endian */ 357 358 unsigned char rotate_mode; /* (enum) rotate mode */ 359 /* 0x0, no rotate */ 360 /* 0x1, rotate */ 361 /* 0x2, x_mirror */ 362 /* 0x3, y_mirror */ 363 364 unsigned char color_fill_mode; /* 0 solid color / 1 patten color */ 365 366 MMU mmu_info; /* mmu information */ 367 368 unsigned char alpha_rop_mode; /* ([0~1] alpha mode) */ 369 /* ([2~3] rop mode) */ 370 /* ([4] zero mode en) */ 371 /* ([5] dst alpha mode) (RGA1) */ 372 373 unsigned char src_trans_mode; 374 375 unsigned char dither_mode; 376 377 full_csc_t full_csc; /* full color space convert */ 378 379 unsigned char CMD_fin_int_enable; 380 381 /* completion is reported through a callback */ 382 void (*complete)(int retval); 383 }; 384 385 int RGA_set_src_act_info( 386 struct rga_req *req, 387 unsigned int width, /* act width */ 388 unsigned int height, /* act height */ 389 unsigned int x_off, /* x_off */ 390 unsigned int y_off /* y_off */ 391 ); 392 393 #if defined(__arm64__) || defined(__aarch64__) 394 int RGA_set_src_vir_info( 395 struct rga_req *req, 396 unsigned long yrgb_addr, /* yrgb_addr */ 397 unsigned long uv_addr, /* uv_addr */ 398 unsigned long v_addr, /* v_addr */ 399 unsigned int vir_w, /* vir width */ 400 unsigned int vir_h, /* vir height */ 401 unsigned char format, /* format */ 402 unsigned char a_swap_en /* only for 32bit RGB888 format */ 403 ); 404 #else 405 int RGA_set_src_vir_info( 406 struct rga_req *req, 407 unsigned int yrgb_addr, /* yrgb_addr */ 408 unsigned int uv_addr, /* uv_addr */ 409 unsigned int v_addr, /* v_addr */ 410 unsigned int vir_w, /* vir width */ 411 unsigned int vir_h, /* vir height */ 412 unsigned char format, /* format */ 413 unsigned char a_swap_en /* only for 32bit RGB888 format */ 414 ); 415 #endif 416 417 int RGA_set_dst_act_info( 418 struct rga_req *req, 419 unsigned int width, /* act width */ 420 unsigned int height, /* act height */ 421 unsigned int x_off, /* x_off */ 422 unsigned int y_off /* y_off */ 423 ); 424 #if defined(__arm64__) || defined(__aarch64__) 425 int RGA_set_dst_vir_info( 426 struct rga_req *msg, 427 unsigned long yrgb_addr, /* yrgb_addr */ 428 unsigned long uv_addr, /* uv_addr */ 429 unsigned long v_addr, /* v_addr */ 430 unsigned int vir_w, /* vir width */ 431 unsigned int vir_h, /* vir height */ 432 RECT *clip, /* clip window */ 433 unsigned char format, /* format */ 434 unsigned char a_swap_en 435 ); 436 #else 437 int RGA_set_dst_vir_info( 438 struct rga_req *msg, 439 unsigned int yrgb_addr, /* yrgb_addr */ 440 unsigned int uv_addr, /* uv_addr */ 441 unsigned int v_addr, /* v_addr */ 442 unsigned int vir_w, /* vir width */ 443 unsigned int vir_h, /* vir height */ 444 RECT *clip, /* clip window */ 445 unsigned char format, /* format */ 446 unsigned char a_swap_en 447 ); 448 #endif 449 450 int RGA_set_pat_info( 451 struct rga_req *msg, 452 unsigned int width, 453 unsigned int height, 454 unsigned int x_off, 455 unsigned int y_off, 456 unsigned int pat_format 457 ); 458 459 #if defined(__arm64__) || defined(__aarch64__) 460 int RGA_set_rop_mask_info( 461 struct rga_req *msg, 462 unsigned long rop_mask_addr, 463 unsigned int rop_mask_endian_mode 464 ); 465 #else 466 int RGA_set_rop_mask_info( 467 struct rga_req *msg, 468 unsigned int rop_mask_addr, 469 unsigned int rop_mask_endian_mode 470 ); 471 #endif 472 473 int RGA_set_alpha_en_info( 474 struct rga_req *msg, 475 unsigned int alpha_cal_mode, /* 0:alpha' = alpha + (alpha>>7) | alpha' = alpha */ 476 unsigned int alpha_mode, /* 0 global alpha / 1 per pixel alpha / 2 mix mode */ 477 unsigned int global_a_value, 478 unsigned int PD_en, /* porter duff alpha mode en */ 479 unsigned int PD_mode, 480 unsigned int dst_alpha_en); /* use dst alpha */ 481 482 int RGA_set_rop_en_info( 483 struct rga_req *msg, 484 unsigned int ROP_mode, 485 unsigned int ROP_code, 486 unsigned int color_mode, 487 unsigned int solid_color 488 ); 489 490 int RGA_set_fading_en_info( 491 struct rga_req *msg, 492 unsigned char r, 493 unsigned char g, 494 unsigned char b 495 ); 496 497 int RGA_set_src_trans_mode_info( 498 struct rga_req *msg, 499 unsigned char trans_mode, 500 unsigned char a_en, 501 unsigned char b_en, 502 unsigned char g_en, 503 unsigned char r_en, 504 unsigned char color_key_min, 505 unsigned char color_key_max, 506 unsigned char zero_mode_en 507 ); 508 509 int RGA_set_bitblt_mode( 510 struct rga_req *msg, 511 unsigned char scale_mode, // 0/near 1/bilnear 2/bicubic 512 unsigned char rotate_mode, // 0/copy 1/rotate_scale 2/x_mirror 3/y_mirror 513 unsigned int angle, // rotate angle 514 unsigned int dither_en, // dither en flag 515 unsigned int AA_en, // AA flag 516 unsigned int yuv2rgb_mode 517 ); 518 519 int RGA_set_color_palette_mode( 520 struct rga_req *msg, 521 unsigned char palette_mode, /* 1bpp/2bpp/4bpp/8bpp */ 522 unsigned char endian_mode, /* src endian mode sel */ 523 unsigned int bpp1_0_color, /* BPP1 = 0 */ 524 unsigned int bpp1_1_color /* BPP1 = 1 */ 525 ); 526 527 int RGA_set_color_fill_mode( 528 struct rga_req *msg, 529 COLOR_FILL *gr_color, /* gradient color part */ 530 unsigned char gr_satur_mode, /* saturation mode */ 531 unsigned char cf_mode, /* patten fill or solid fill */ 532 unsigned int color, /* solid color */ 533 unsigned short pat_width, /* pattern width */ 534 unsigned short pat_height, /* pattern height */ 535 unsigned char pat_x_off, /* pattern x offset */ 536 unsigned char pat_y_off, /* pattern y offset */ 537 unsigned char aa_en /* alpha en */ 538 ); 539 540 int RGA_set_line_point_drawing_mode( 541 struct rga_req *msg, 542 POINT sp, /* start point */ 543 POINT ep, /* end point */ 544 unsigned int color, /* line point drawing color */ 545 unsigned int line_width, /* line width */ 546 unsigned char AA_en, /* AA en */ 547 unsigned char last_point_en /* last point en */ 548 ); 549 550 int RGA_set_blur_sharp_filter_mode( 551 struct rga_req *msg, 552 unsigned char filter_mode, /* blur/sharpness */ 553 unsigned char filter_type, /* filter intensity */ 554 unsigned char dither_en /* dither_en flag */ 555 ); 556 557 int RGA_set_pre_scaling_mode( 558 struct rga_req *msg, 559 unsigned char dither_en 560 ); 561 562 #if defined(__arm64__) || defined(__aarch64__) 563 int RGA_update_palette_table_mode( 564 struct rga_req *msg, 565 unsigned long LUT_addr, /* LUT table addr */ 566 unsigned int palette_mode /* 1bpp/2bpp/4bpp/8bpp */ 567 ); 568 #else 569 int RGA_update_palette_table_mode( 570 struct rga_req *msg, 571 unsigned int LUT_addr, /* LUT table addr */ 572 unsigned int palette_mode /* 1bpp/2bpp/4bpp/8bpp */ 573 ); 574 #endif 575 576 int RGA_set_update_patten_buff_mode( 577 struct rga_req *msg, 578 unsigned int pat_addr, /* patten addr */ 579 unsigned int w, /* patten width */ 580 unsigned int h, /* patten height */ 581 unsigned int format /* patten format */ 582 ); 583 584 #if defined(__arm64__) || defined(__aarch64__) 585 int RGA_set_mmu_info( 586 struct rga_req *msg, 587 unsigned char mmu_en, 588 unsigned char src_flush, 589 unsigned char dst_flush, 590 unsigned char cmd_flush, 591 unsigned long base_addr, 592 unsigned char page_size 593 ); 594 #else 595 int RGA_set_mmu_info( 596 struct rga_req *msg, 597 unsigned char mmu_en, 598 unsigned char src_flush, 599 unsigned char dst_flush, 600 unsigned char cmd_flush, 601 unsigned int base_addr, 602 unsigned char page_size 603 ); 604 #endif 605 606 void rga_set_fds_offsets( 607 struct rga_req *rga_request, 608 unsigned short src_fd, 609 unsigned short dst_fd, 610 unsigned int src_offset, 611 unsigned int dst_offset); 612 613 int RGA_set_src_fence_flag( 614 struct rga_req *msg, 615 int acq_fence, 616 int src_flag 617 ); 618 619 int RGA_set_dst_fence_flag( 620 struct rga_req *msg, 621 int dst_flag 622 ); 623 624 int RGA_get_dst_fence( 625 struct rga_req *msg 626 ); 627 #ifdef __cplusplus 628 } 629 #endif 630 631 #endif /* _RK29_IPP_DRIVER_H_ */ 632