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1 /*
2  * Copyright (c) 2022 ASR Microelectronics (Shanghai) Co., Ltd. All rights reserved.
3  * Licensed under the Apache License, Version 2.0 (the "License");
4  * you may not use this file except in compliance with the License.
5  * You may obtain a copy of the License at
6  *
7  *     http://www.apache.org/licenses/LICENSE-2.0
8  *
9  * Unless required by applicable law or agreed to in writing, software
10  * distributed under the License is distributed on an "AS IS" BASIS,
11  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12  * See the License for the specific language governing permissions and
13  * limitations under the License.
14  */
15 
16 #ifndef __DUET_DMA_H
17 #define __DUET_DMA_H
18 
19 #include "duet.h"
20 
21 #ifdef __cplusplus
22 extern "C" {
23 #endif
24 
25 #define DMA_SRC_DATA_WIDTH_BYTE       (0)
26 #define DMA_SRC_DATA_WIDTH_HALFWORD   (1)
27 #define DMA_SRC_DATA_WIDTH_WORD       (2)
28 #define DMA_DST_DATA_WIDTH_BYTE       (0)
29 #define DMA_DST_DATA_WIDTH_HALFWORD   (1)
30 #define DMA_DST_DATA_WIDTH_WORD       (2)
31 
32 #define DMA_SRC_ADDR_INC_BYTE         (0)
33 #define DMA_SRC_ADDR_INC_HALFWORD     (1)
34 #define DMA_SRC_ADDR_INC_WORD         (2)
35 #define DMA_SRC_ADDR_INC_FIX          (3)
36 
37 #define DMA_DST_ADDR_INC_BYTE         (0)
38 #define DMA_DST_ADDR_INC_HALFWORD     (1)
39 #define DMA_DST_ADDR_INC_WORD         (2)
40 #define DMA_DST_ADDR_INC_FIX          (3)
41 
42 #define DMA_OP_MODE_STOP                (0)
43 #define DMA_OP_MODE_BASIC               (1)
44 #define DMA_OP_MODE_AUTO_REQ            (2)
45 #define DMA_OP_MODE_PING_PONG           (3)
46 #define DMA_OP_MODE_MEM_SCT_GAT_PRI     (4)
47 #define DMA_OP_MODE_MEM_SCT_GAT_ALT     (5)
48 #define DMA_OP_MODE_PERI_SCT_GAT_PRI    (6)
49 #define DMA_OP_MODE_PERI_SCT_GAT_ALT    (7)
50 
51 #define DMA_R_POWER_1                   (0)   // every dma period   nums of transfer uinit
52 #define DMA_R_POWER_2                   (1)
53 #define DMA_R_POWER_4                   (2)
54 #define DMA_R_POWER_8                   (3)
55 #define DMA_R_POWER_16                 (4)
56 #define DMA_R_POWER_32                 (5)
57 #define DMA_R_POWER_64                 (6)
58 #define DMA_R_POWER_128               (7)
59 #define DMA_R_POWER_256               (8)
60 #define DMA_R_POWER_512               (9)
61 #define DMA_R_POWER_1024             (10)
62 
63 #define DMA_N_1_MAX                     (1024)
64 
65 #define DMA_MAX_CHAN_NUM                (32)  // nums of primary channels
66 typedef enum {
67     DMA_CH_UART0_TX = 0,
68     DMA_CH_UART0_RX,
69     DMA_CH_UART1_TX,
70     DMA_CH_UART1_RX,
71     DMA_CH_UART2_TX,
72     DMA_CH_UART2_RX,
73     DMA_CH_SPI0_TX,
74     DMA_CH_SPI0_RX,
75     DMA_CH_SPI1_TX,
76     DMA_CH_SPI1_RX,
77     DMA_CH_SPI2_TX,
78     DMA_CH_SPI2_RX,
79     DMA_CH_I2C0_RX,
80     DMA_CH_I2C0_TX,
81     DMA_CH_I2C1_RX,
82     DMA_CH_I2C1_TX,
83 } DMA_CHANNEL;
84 
85 typedef void (*duet_dma_callback_func)(uint32_t);
86 
87 typedef struct {
88     uint32_t cycle_ctl : 3;
89     uint32_t next_useburst : 1;
90     uint32_t n_minus_1 : 10;
91     uint32_t R_pow : 4;
92     uint32_t src_prot : 3;
93     uint32_t dest_prot : 3;
94     uint32_t src_size : 2;
95     uint32_t src_inc : 2;
96     uint32_t dst_size : 2;
97     uint32_t dst_inc : 2;
98 
99 } Chan_Ctl_Data_TypeDef;
100 
101 typedef struct {
102     uint32_t SrcEndPtr;
103     uint32_t DstEndPtr;
104     uint32_t n_minus1;
105     uint8_t chan_num;
106     uint8_t next_useburst;
107     uint32_t cycle;
108     uint32_t R_power;
109     uint32_t SrcDataWidth;
110     uint32_t DstDataWidth;
111     uint32_t SrcAddrInc;
112     uint32_t DstAddrInc;
113     uint8_t interrupt_en;
114     uint8_t use_pri_only;
115 } DMA_Init_Struct_Type;
116 
117 typedef struct {
118     uint32_t chan_src_end_ptr;
119     uint32_t chan_dst_end_ptr;
120     Chan_Ctl_Data_TypeDef chan_ctr;
121     uint32_t resv;
122 } Chan_Cfg_TypeDef;
123 
124 Chan_Cfg_TypeDef *duet_dma_ctrl_block_init(void);
125 void duet_dma_init(void);
126 void duet_dma_interrupt_clear(uint32_t chan_idx);
127 ITstatus duet_dma_get_interrupt_status(uint32_t chan_idx);
128 void duet_dma_interrupt_config(uint32_t chan_idx, uint8_t new_state);
129 void duet_dma_channel_cmd(uint32_t chan_idx, uint8_t new_state);
130 void duet_dma_generate_sw_req(uint32_t chan_idx);
131 void duet_dma_mem2mem(uint8_t chan_num, uint8_t *mem_src, uint8_t *mem_dst, uint16_t len);
132 void duet_dma_uart_rx(uint8_t uart_idx, uint8_t *data, uint16_t len);
133 void duet_dma_uart_tx(uint8_t uart_idx, uint8_t *data, uint16_t len);
134 void duet_dma_spi_rx(uint8_t ssp_idx, uint8_t *data, uint16_t len);
135 void duet_dma_spi_tx(uint8_t ssp_idx, uint8_t *data, uint16_t len);
136 void duet_dma_callback_register(uint8_t chn_idx, duet_dma_callback_func func);
137 
138 #endif // __DUET_DMA_H
139