1 // Copyright 2013-2016 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include <string.h>
16 #include "esp_system.h"
17 #include "esp_private/system_internal.h"
18 #include "esp_attr.h"
19 #include "esp_efuse.h"
20 #include "esp_log.h"
21 #include "sdkconfig.h"
22 #include "esp32/rom/cache.h"
23 #include "esp_rom_uart.h"
24 #include "soc/dport_reg.h"
25 #include "soc/gpio_periph.h"
26 #include "soc/efuse_periph.h"
27 #include "soc/rtc_periph.h"
28 #include "soc/timer_periph.h"
29 #include "soc/cpu.h"
30 #include "soc/rtc.h"
31 #include "hal/wdt_hal.h"
32 #include "hal/cpu_hal.h"
33 #include "esp_osal/xtensa_api.h"
34 #include "soc/soc_memory_layout.h"
35
36 #include "esp32/cache_err_int.h"
37
38 /* "inner" restart function for after RTOS, interrupts & anything else on this
39 * core are already stopped. Stalls other core, resets hardware,
40 * triggers restart.
41 */
esp_restart_noos(void)42 void IRAM_ATTR esp_restart_noos(void)
43 {
44 // Disable interrupts
45 xt_ints_off(0xFFFFFFFF);
46
47 // Enable RTC watchdog for 1 second
48 wdt_hal_context_t rtc_wdt_ctx;
49 wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false);
50 uint32_t stage_timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
51 wdt_hal_write_protect_disable(&rtc_wdt_ctx);
52 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM);
53 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE1, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
54 wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true);
55 wdt_hal_write_protect_enable(&rtc_wdt_ctx);
56
57 // Reset and stall the other CPU.
58 // CPU must be reset before stalling, in case it was running a s32c1i
59 // instruction. This would cause memory pool to be locked by arbiter
60 // to the stalled CPU, preventing current CPU from accessing this pool.
61 const uint32_t core_id = cpu_hal_get_core_id();
62 const uint32_t other_core_id = (core_id == 0) ? 1 : 0;
63 esp_cpu_reset(other_core_id);
64 esp_cpu_stall(other_core_id);
65
66 // Other core is now stalled, can access DPORT registers directly
67 esp_dport_access_int_abort();
68
69 //Todo: Refactor to use Interrupt or Task Watchdog API, and a system level WDT context
70 // Disable TG0/TG1 watchdogs
71 wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
72 wdt_hal_write_protect_disable(&wdt0_context);
73 wdt_hal_disable(&wdt0_context);
74 wdt_hal_write_protect_enable(&wdt0_context);
75
76 wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1};
77 wdt_hal_write_protect_disable(&wdt1_context);
78 wdt_hal_disable(&wdt1_context);
79 wdt_hal_write_protect_enable(&wdt1_context);
80
81 // Flush any data left in UART FIFOs
82 esp_rom_uart_tx_wait_idle(0);
83 esp_rom_uart_tx_wait_idle(1);
84 esp_rom_uart_tx_wait_idle(2);
85
86 #ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
87 if (esp_ptr_external_ram(get_sp())) {
88 // If stack_addr is from External Memory (CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY is used)
89 // then need to switch SP to Internal Memory otherwise
90 // we will get the "Cache disabled but cached memory region accessed" error after Cache_Read_Disable.
91 uint32_t new_sp = SOC_DRAM_LOW + (SOC_DRAM_HIGH - SOC_DRAM_LOW) / 2;
92 SET_STACK(new_sp);
93 }
94 #endif
95
96 // Disable cache
97 Cache_Read_Disable(0);
98 Cache_Read_Disable(1);
99
100 // 2nd stage bootloader reconfigures SPI flash signals.
101 // Reset them to the defaults expected by ROM.
102 WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);
103 WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30);
104 WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30);
105 WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30);
106 WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
107 WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
108
109 // Reset wifi/bluetooth/ethernet/sdio (bb/mac)
110 DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG,
111 DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST |
112 DPORT_BT_RST | DPORT_BTMAC_RST | DPORT_SDIO_RST |
113 DPORT_SDIO_HOST_RST | DPORT_EMAC_RST | DPORT_MACPWR_RST |
114 DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST);
115 DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0);
116
117 // Reset timer/spi/uart
118 DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,
119 //UART TX FIFO cannot be reset correctly on ESP32, so reset the UART memory by DPORT here.
120 DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_SPI2_RST | DPORT_SPI3_RST | DPORT_SPI_DMA_RST | DPORT_UART_RST | DPORT_UART1_RST | DPORT_UART2_RST | DPORT_UART_MEM_RST);
121 DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0);
122
123 // Set CPU back to XTAL source, no PLL, same as hard reset
124 rtc_clk_cpu_freq_set_xtal();
125
126 // Clear entry point for APP CPU
127 DPORT_REG_WRITE(DPORT_APPCPU_CTRL_D_REG, 0);
128
129 // Reset CPUs
130 if (core_id == 0) {
131 // Running on PRO CPU: APP CPU is stalled. Can reset both CPUs.
132 esp_cpu_reset(1);
133 esp_cpu_reset(0);
134 } else {
135 // Running on APP CPU: need to reset PRO CPU and unstall it,
136 // then reset APP CPU
137 esp_cpu_reset(0);
138 esp_cpu_unstall(0);
139 esp_cpu_reset(1);
140 }
141 while(true) {
142 ;
143 }
144 }
145
esp_chip_info(esp_chip_info_t * out_info)146 void esp_chip_info(esp_chip_info_t* out_info)
147 {
148 uint32_t efuse_rd3 = REG_READ(EFUSE_BLK0_RDATA3_REG);
149 memset(out_info, 0, sizeof(*out_info));
150
151 out_info->model = CHIP_ESP32;
152 out_info->revision = esp_efuse_get_chip_ver();
153
154 if ((efuse_rd3 & EFUSE_RD_CHIP_VER_DIS_APP_CPU_M) == 0) {
155 out_info->cores = 2;
156 } else {
157 out_info->cores = 1;
158 }
159 out_info->features = CHIP_FEATURE_WIFI_BGN;
160 if ((efuse_rd3 & EFUSE_RD_CHIP_VER_DIS_BT_M) == 0) {
161 out_info->features |= CHIP_FEATURE_BT | CHIP_FEATURE_BLE;
162 }
163 uint32_t package = esp_efuse_get_pkg_ver();
164 if (package == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 ||
165 package == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 ||
166 package == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 ||
167 package == EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302) {
168 out_info->features |= CHIP_FEATURE_EMB_FLASH;
169 }
170 }
171
172 #if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
soc_has_cache_lock_bug(void)173 inline bool soc_has_cache_lock_bug(void)
174 {
175 return (esp_efuse_get_chip_ver() == 3);
176 }
177 #endif
178