1// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD 2// 3// Licensed under the Apache License, Version 2.0 (the "License"); 4// you may not use this file except in compliance with the License. 5// You may obtain a copy of the License at 6// 7// http://www.apache.org/licenses/LICENSE-2.0 8// 9// Unless required by applicable law or agreed to in writing, software 10// distributed under the License is distributed on an "AS IS" BASIS, 11// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12// See the License for the specific language governing permissions and 13// limitations under the License. 14 15#include <stdlib.h> 16#include "hal/spi_flash_hal.h" 17#include "string.h" 18#include "hal/hal_defs.h" 19#include "soc/soc_caps.h" 20#include "sdkconfig.h" 21 22#define ADDRESS_MASK_24BIT 0xFFFFFF 23#define COMPUTE_DUMMY_CYCLELEN(host, base) ((base) + ((spi_flash_hal_context_t*)host)->extra_dummy) 24 25static inline spi_dev_t *get_spi_dev(spi_flash_host_inst_t *host) 26{ 27 return ((spi_flash_hal_context_t*)host)->spi; 28} 29 30static inline int get_host_id(spi_flash_host_inst_t* host) 31{ 32 spi_dev_t *dev = get_spi_dev(host); 33 return spi_flash_ll_hw_get_id(dev); 34} 35 36void spi_flash_hal_poll_cmd_done(spi_flash_host_inst_t *host) 37{ 38 while (!spi_flash_ll_cmd_is_done(get_spi_dev(host))) { 39 //nop 40 } 41} 42 43esp_err_t spi_flash_hal_device_config(spi_flash_host_inst_t *host) 44{ 45 spi_flash_hal_context_t* ctx = (spi_flash_hal_context_t*)host; 46 spi_dev_t *dev = get_spi_dev(host); 47 48 spi_flash_ll_reset(dev); 49 spi_flash_ll_set_cs_pin(dev, ctx->cs_num); 50 spi_flash_ll_set_clock(dev, &ctx->clock_conf); 51 int cs_hold = ctx->cs_hold; 52 spi_flash_ll_set_hold(dev, cs_hold); 53 spi_flash_ll_set_cs_setup(dev, ctx->cs_setup); 54 55#ifndef GPSPI_BUILD 56#if SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND 57 if ((ctx->flags & SPI_FLASH_HOST_CONTEXT_FLAG_AUTO_SUSPEND) != 0) { 58 spi_flash_hal_setup_auto_suspend_mode(host); 59 } else { 60 spi_flash_hal_disable_auto_suspend_mode(host); 61 } 62 if ((ctx->flags & SPI_FLASH_HOST_CONTEXT_FLAG_AUTO_RESUME) != 0) { 63 spi_flash_hal_setup_auto_resume_mode(host); 64 } else { 65 spi_flash_hal_disable_auto_resume_mode(host); 66 } 67#endif //SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND 68#endif //GPSPI_BUILD 69 return ESP_OK; 70} 71 72esp_err_t spi_flash_hal_configure_host_io_mode( 73 spi_flash_host_inst_t *host, 74 uint32_t command, 75 uint32_t addr_bitlen, 76 int dummy_cyclelen_base, 77 esp_flash_io_mode_t io_mode) 78{ 79 spi_dev_t *dev = get_spi_dev(host); 80 int host_id = spi_flash_ll_hw_get_id(dev); 81 82 uint32_t extra_bits = io_mode & 0xFFFF0000; 83 io_mode = io_mode & 0xFFFF; 84 85 /* 86 * Some flash chips, when working under some IO modes (DIO, QIO and OIO in the future), treat 87 * the first 8 bits of the dummy bits as the bits. When the bits meet some pattern, the chip 88 * will go into a "continuous (XIP)" mode, where the command field will be skipped in the next 89 * transaction. We have to output all ones in these cycles because we don't need this feature. 90 */ 91 bool conf_required = ((extra_bits & SPI_FLASH_CONFIG_CONF_BITS) != 0); 92 93 if (!SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) && io_mode > SPI_FLASH_FASTRD) { 94 return ESP_ERR_NOT_SUPPORTED; 95 } 96 97#if CONFIG_SPI_FLASH_ROM_IMPL && CONFIG_IDF_TARGET_ESP32S3 98 /* 99 * In S3 ROM, extra bits than 24-bit are used to indicate requirements of M7-M0: 100 * - 24: normal transactions 101 * - 28: 24bit DIO + conf bits (M7-M0 excluded from dummy_bitlen) 102 * - 32: 24bit QIO + conf bits (M7-M0 excluded from dummy_bitlen) 103 104 * Detect requirements for the conf bits by the address len, and modify the length to normal 105 * case (addr_bitlen = 24, dummy_bitlen includes M7-M0) as other chip versions use. 106 */ 107 int m70_bits = addr_bitlen - 24; 108 if (m70_bits) { 109 assert(io_mode == SPI_FLASH_DIO || io_mode == SPI_FLASH_QIO); 110 conf_required = true; 111 addr_bitlen -= m70_bits; 112 int line_width = (io_mode == SPI_FLASH_DIO? 2: 4); 113 dummy_cyclelen_base += m70_bits / line_width; 114 } 115#endif //CONFIG_SPI_FLASH_ROM_IMPL 116 117#if SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT 118 // The CONTROL_DUMMY_OUTPUT feature is used to control M7-M0 bits. 119 spi_flash_ll_set_dummy_out(dev, (conf_required? 1: 0), 1); 120#else 121 // On ESP32, dummy output is not supported. These dummy bits will be moved into the address 122 // phase (and appended as ones). 123 if (conf_required) { 124 int line_width = (io_mode == SPI_FLASH_DIO? 2: 4); 125 dummy_cyclelen_base -= 4 / line_width; 126 addr_bitlen += 4; //extra 4 bits indicate the conf bits is included 127 } 128#endif 129 130 if (command >= 0x100) { 131 spi_flash_ll_set_command(dev, command, 16); 132 } else { 133 spi_flash_ll_set_command(dev, command, 8); 134 } 135 spi_flash_ll_set_addr_bitlen(dev, addr_bitlen); 136 // Add dummy cycles to compensate for latency of GPIO matrix and external delay, if necessary... 137 spi_flash_ll_set_dummy(dev, COMPUTE_DUMMY_CYCLELEN(host, dummy_cyclelen_base)); 138 //disable all data phases, enable them later if needed 139 spi_flash_ll_set_miso_bitlen(dev, 0); 140 spi_flash_ll_set_mosi_bitlen(dev, 0); 141 spi_flash_ll_set_read_mode(dev, io_mode); 142 return ESP_OK; 143} 144 145esp_err_t spi_flash_hal_common_command(spi_flash_host_inst_t *host, spi_flash_trans_t *trans) 146{ 147 spi_dev_t *dev = get_spi_dev(host); 148 esp_flash_io_mode_t io_mode = ((spi_flash_hal_context_t*)host)->base_io_mode; 149 uint16_t command; 150 uint8_t dummy_bitlen; 151 if (trans->reserved != 0) { 152 // Back-compatible with caller functions of ESP32-S3 ROM 153 command = (uint8_t)trans->reserved; 154 dummy_bitlen = 0; 155 } else { 156 command = trans->command; 157 dummy_bitlen = trans->dummy_bitlen; 158 if ((trans->flags & SPI_FLASH_TRANS_FLAG_IGNORE_BASEIO) != 0) { 159 io_mode = ((spi_flash_hal_context_t*)host)->base_io_mode; 160 } 161 } 162 163 host->driver->configure_host_io_mode(host, command, trans->address_bitlen, dummy_bitlen, io_mode); 164 165 spi_flash_ll_set_usr_address(dev, trans->address, trans->address_bitlen); 166 //No extra dummy cycles for compensation if no input data 167 if (trans->miso_len == 0) { 168 spi_flash_ll_set_dummy(dev, dummy_bitlen); 169 } 170 171 spi_flash_ll_set_mosi_bitlen(dev, trans->mosi_len * 8); 172 spi_flash_ll_set_buffer_data(dev, trans->mosi_data, trans->mosi_len); 173 174 spi_flash_ll_set_miso_bitlen(dev, trans->miso_len * 8); 175 spi_flash_ll_user_start(dev); 176 host->driver->poll_cmd_done(host); 177 spi_flash_ll_get_buffer_data(dev, trans->miso_data, trans->miso_len); 178 return ESP_OK; 179} 180 181esp_err_t spi_flash_hal_read(spi_flash_host_inst_t *host, void *buffer, uint32_t address, uint32_t read_len) 182{ 183 spi_dev_t *dev = get_spi_dev(host); 184 int bitlen = spi_flash_ll_get_addr_bitlen(dev); 185 //Only 24-bit and 32-bit address are supported. The extra length are for M7-M0, which should be 186 //filled with ones by the function below 187 spi_flash_ll_set_usr_address(dev, address, bitlen & (~7)); 188 spi_flash_ll_set_miso_bitlen(dev, read_len * 8); 189 spi_flash_ll_user_start(dev); 190 host->driver->poll_cmd_done(host); 191 spi_flash_ll_get_buffer_data(dev, buffer, read_len); 192 return ESP_OK; 193} 194