1/* ESP32 Linker Script Memory Layout 2 3 This file describes the memory layout (memory blocks) as virtual 4 memory addresses. 5 6 esp32.project.ld contains output sections to link compiler output 7 into these memory blocks. 8 9 *** 10 11 This linker script is passed through the C preprocessor to include 12 configuration options. 13 14 Please use preprocessor features sparingly! Restrict 15 to simple macros with numeric values, and/or #if/#endif blocks. 16*/ 17/* 18 * Automatically generated file. DO NOT EDIT. 19 * Espressif IoT Development Framework (ESP-IDF) Configuration Header 20 */ 21 22/* List of deprecated options */ 23/* If BT is not built at all */ 24MEMORY 25{ 26 /* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length 27 of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but 28 are connected to the data port of the CPU and eg allow bytewise access. */ 29 /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */ 30 iram0_0_seg (RX) : org = 0x40080000, len = 0x20000 31 /* Even though the segment name is iram, it is actually mapped to flash 32 */ 33 iram0_2_seg (RX) : org = 0x400D0020, len = 0x330000-0x20 34 /* 35 (0x20 offset above is a convenience for the app binary image generation. 36 Flash cache has 64KB pages. The .bin file which is flashed to the chip 37 has a 0x18 byte file header, and each segment has a 0x08 byte segment 38 header. Setting this offset makes it simple to meet the flash cache MMU's 39 constraint that (paddr % 64KB == vaddr % 64KB).) 40 */ 41 /* Shared data RAM, excluding memory reserved for ROM bss/data/stack. 42 43 Enabling Bluetooth & Trace Memory features in menuconfig will decrease 44 the amount of RAM available. 45 46 Note: Length of this section *should* be 0x50000, and this extra DRAM is available 47 in heap at runtime. However due to static ROM memory usage at this 176KB mark, the 48 additional static memory temporarily cannot be used. 49 */ 50 dram0_0_seg (RW) : org = 0x3FFB0000 + 0xdb5c, 51 len = 0x2c200 - 0xdb5c 52 /* Flash mapped constant data */ 53 drom0_0_seg (R) : org = 0x3F400020, len = 0x400000-0x20 54 /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */ 55 /* RTC fast memory (executable). Persists over deep sleep. 56 */ 57 rtc_iram_seg(RWX) : org = 0x400C0000, len = 0x2000 58 /* RTC fast memory (same block as above), viewed from data bus */ 59 rtc_data_seg(RW) : org = 0x3ff80000, len = 0x2000 - 0 60 /* RTC slow memory (data accessible). Persists over deep sleep. 61 62 Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled. 63 */ 64 rtc_slow_seg(RW) : org = 0x50000000 + 0, 65 len = 0x2000 - 0 66 /* external memory ,including data and text */ 67 extern_ram_seg(RWX) : org = 0x3F800000, 68 len = 0x400000 69} 70_static_data_end = _bss_end; 71/* Heap ends at top of dram0_0_seg */ 72_heap_end = 0x40000000 - 0x0; 73_data_seg_org = ORIGIN(rtc_data_seg); 74/* The lines below define location alias for .rtc.data section based on Kconfig option. 75 When the option is not defined then use slow memory segment 76 else the data will be placed in fast memory segment */ 77REGION_ALIAS("rtc_data_location", rtc_slow_seg ); 78 REGION_ALIAS("default_code_seg", iram0_2_seg); 79 REGION_ALIAS("default_rodata_seg", drom0_0_seg); 80/** 81 * If rodata default segment is placed in `drom0_0_seg`, then flash's first rodata section must 82 * also be first in the segment. 83 */ 84 ASSERT(_rodata_start == ORIGIN(default_rodata_seg), 85 ".flash.appdesc section must be placed at the beginning of the rodata segment.") 86