1root { 2 platform { 3 spi_config { 4 template spi_controller { 5 serviceName = ""; 6 match_attr = ""; 7 transferMode = 0; 8 busNum = 0; 9 clkRate = 100000000; 10 bitsPerWord = 8; 11 mode = 19; 12 maxSpeedHz = 0; 13 minSpeedHz = 0; 14 speed = 2000000; 15 fifoSize = 256; 16 numCs = 1; 17 regBase = 0x120c0000; 18 irqNum = 100; 19 REG_CRG_SPI = 0x120100e4; /* CRG_REG_BASE(0x12010000) + 0x0e4 */ 20 CRG_SPI_CKEN = 0; 21 CRG_SPI_RST = 0; 22 REG_MISC_CTRL_SPI = 0x12030024; /* MISC_REG_BASE(0x12030000) + 0x24 */ 23 MISC_CTRL_SPI_CS = 0; 24 MISC_CTRL_SPI_CS_SHIFT = 0; 25 } 26 27 controller_0x120c0000 :: spi_controller { 28 busNum = 0; 29 CRG_SPI_CKEN = 0x10000; /* (0x1 << 16) 0:close clk, 1:open clk */ 30 CRG_SPI_RST = 0x1; /* (0x1 << 0) 0:cancel reset, 1:reset */ 31 match_attr = "hisilicon_hi35xx_spi_0"; 32 } 33 34 controller_0x120c1000 :: spi_controller { 35 busNum = 1; 36 CRG_SPI_CKEN = 0x20000; /* (0x1 << 17) 0:close clk, 1:open clk */ 37 CRG_SPI_RST = 0x2; /* (0x1 << 1) 0:cancel reset, 1:reset */ 38 match_attr = "hisilicon_hi35xx_spi_1"; 39 regBase = 0x120c1000; 40 irqNum = 101; 41 } 42 43 controller_0x120c2000 :: spi_controller { 44 busNum = 2; 45 numCs = 2; 46 CRG_SPI_CKEN = 0x40000; /* (0x1 << 18) 0:close clk, 1:open clk */ 47 CRG_SPI_RST = 0x4; /* (0x1 << 2) 0:cancel reset, 1:reset */ 48 MISC_CTRL_SPI_CS = 1; /* (0x1 << MISC_CTRL_SPI_CS_SHIFT) 00:cs0, 01:cs1 */ 49 MISC_CTRL_SPI_CS_SHIFT = 0; /* 0 */ 50 match_attr = "hisilicon_hi35xx_spi_2"; 51 regBase = 0x120c2000; 52 irqNum = 102; 53 } 54 } 55 } 56} 57