1 /* 2 * Copyright (c) 2022 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef __HI_COMM_VO_H__ 17 #define __HI_COMM_VO_H__ 18 19 #include "hi_type.h" 20 #include "hi_common.h" 21 #include "hi_errno.h" 22 #include "hi_comm_video.h" 23 24 #ifdef __cplusplus 25 #if __cplusplus 26 extern "C" { 27 #endif 28 #endif /* End of #ifdef __cplusplus */ 29 30 typedef enum hiEN_VOU_ERR_CODE_E { 31 EN_ERR_VO_DEV_NOT_CONFIG = 0x40, 32 EN_ERR_VO_DEV_NOT_ENABLE = 0x41, 33 EN_ERR_VO_DEV_HAS_ENABLED = 0x42, 34 EN_ERR_VO_DEV_HAS_BINDED = 0x43, 35 EN_ERR_VO_DEV_NOT_BINDED = 0x44, 36 37 ERR_VO_NOT_ENABLE = 0x45, 38 ERR_VO_NOT_DISABLE = 0x46, 39 ERR_VO_NOT_CONFIG = 0x47, 40 41 ERR_VO_CHN_NOT_DISABLE = 0x48, 42 ERR_VO_CHN_NOT_ENABLE = 0x49, 43 ERR_VO_CHN_NOT_CONFIG = 0x4a, 44 ERR_VO_CHN_NOT_ALLOC = 0x4b, 45 46 ERR_VO_CCD_INVALID_PAT = 0x4c, 47 ERR_VO_CCD_INVALID_POS = 0x4d, 48 49 ERR_VO_WAIT_TIMEOUT = 0x4e, 50 ERR_VO_INVALID_VFRAME = 0x4f, 51 ERR_VO_INVALID_RECT_PARA = 0x50, 52 ERR_VO_SETBEGIN_ALREADY = 0x51, 53 ERR_VO_SETBEGIN_NOTYET = 0x52, 54 ERR_VO_SETEND_ALREADY = 0x53, 55 ERR_VO_SETEND_NOTYET = 0x54, 56 57 ERR_VO_GRP_INVALID_ID = 0x55, 58 ERR_VO_GRP_NOT_CREATE = 0x56, 59 ERR_VO_GRP_HAS_CREATED = 0x57, 60 ERR_VO_GRP_NOT_DESTROY = 0x58, 61 ERR_VO_GRP_CHN_FULL = 0x59, 62 ERR_VO_GRP_CHN_EMPTY = 0x5a, 63 ERR_VO_GRP_CHN_NOT_EMPTY = 0x5b, 64 ERR_VO_GRP_INVALID_SYN_MODE = 0x5c, 65 ERR_VO_GRP_INVALID_BASE_PTS = 0x5d, 66 ERR_VO_GRP_NOT_START = 0x5e, 67 ERR_VO_GRP_NOT_STOP = 0x5f, 68 ERR_VO_GRP_INVALID_FRMRATE = 0x60, 69 ERR_VO_GRP_CHN_HAS_REG = 0x61, 70 ERR_VO_GRP_CHN_NOT_REG = 0x62, 71 ERR_VO_GRP_CHN_NOT_UNREG = 0x63, 72 ERR_VO_GRP_BASE_NOT_CFG = 0x64, 73 74 ERR_GFX_NOT_DISABLE = 0x65, 75 ERR_GFX_NOT_BIND = 0x66, 76 ERR_GFX_NOT_UNBIND = 0x67, 77 ERR_GFX_INVALID_ID = 0x68, 78 79 ERR_VO_WBC_NOT_DISABLE = 0x69, 80 ERR_VO_WBC_NOT_CONFIG = 0x6a, 81 82 ERR_VO_CHN_AREA_OVERLAP = 0x6b, 83 84 EN_ERR_INVALID_WBCID = 0x6c, 85 EN_ERR_INVALID_LAYERID = 0x6d, 86 EN_ERR_VO_VIDEO_HAS_BINDED = 0x6e, 87 EN_ERR_VO_VIDEO_NOT_BINDED = 0x6f, 88 ERR_VO_WBC_HAS_BIND = 0x70, 89 ERR_VO_WBC_HAS_CONFIG = 0x71, 90 ERR_VO_WBC_NOT_BIND = 0x72, 91 92 /* new added */ 93 ERR_VO_BUTT 94 } EN_VOU_ERR_CODE_E; 95 96 /* System define error code */ 97 #define HI_ERR_VO_BUSY HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_BUSY) 98 #define HI_ERR_VO_NO_MEM HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_NOMEM) 99 #define HI_ERR_VO_NULL_PTR HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_NULL_PTR) 100 #define HI_ERR_VO_SYS_NOTREADY HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_SYS_NOTREADY) 101 #define HI_ERR_VO_INVALID_DEVID HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_DEVID) 102 #define HI_ERR_VO_INVALID_CHNID HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_CHNID) 103 #define HI_ERR_VO_ILLEGAL_PARAM HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_ILLEGAL_PARAM) 104 #define HI_ERR_VO_NOT_SUPPORT HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_SUPPORT) 105 #define HI_ERR_VO_NOT_PERMIT HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_PERM) 106 #define HI_ERR_VO_INVALID_WBCID HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_WBCID) 107 #define HI_ERR_VO_INVALID_LAYERID HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_LAYERID) 108 109 /* Device relative error code */ 110 #define HI_ERR_VO_DEV_NOT_CONFIG HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_VO_DEV_NOT_CONFIG) 111 #define HI_ERR_VO_DEV_NOT_ENABLE HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_VO_DEV_NOT_ENABLE) 112 #define HI_ERR_VO_DEV_HAS_ENABLED HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_VO_DEV_HAS_ENABLED) 113 #define HI_ERR_VO_DEV_HAS_BINDED HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_VO_DEV_HAS_BINDED) 114 #define HI_ERR_VO_DEV_NOT_BINDED HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_VO_DEV_NOT_BINDED) 115 116 /* Video layer relative error code */ 117 #define HI_ERR_VO_VIDEO_NOT_ENABLE HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_VO_NOT_ENABLE) 118 #define HI_ERR_VO_VIDEO_NOT_DISABLE HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_VO_NOT_DISABLE) 119 #define HI_ERR_VO_VIDEO_NOT_CONFIG HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_VO_NOT_CONFIG) 120 #define HI_ERR_VO_VIDEO_HAS_BINDED HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_VO_VIDEO_HAS_BINDED) 121 #define HI_ERR_VO_VIDEO_NOT_BINDED HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, EN_ERR_VO_VIDEO_NOT_BINDED) 122 123 /* WBC Relative error code */ 124 #define HI_ERR_VO_WBC_NOT_DISABLE HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_VO_WBC_NOT_DISABLE) 125 #define HI_ERR_VO_WBC_NOT_CONFIG HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_VO_WBC_NOT_CONFIG) 126 #define HI_ERR_VO_WBC_HAS_CONFIG HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_VO_WBC_HAS_CONFIG) 127 #define HI_ERR_VO_WBC_NOT_BIND HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_VO_WBC_NOT_BIND) 128 #define HI_ERR_VO_WBC_HAS_BIND HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_VO_WBC_HAS_BIND) 129 130 /* Channel Relative error code */ 131 #define HI_ERR_VO_CHN_NOT_DISABLE HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_VO_CHN_NOT_DISABLE) 132 #define HI_ERR_VO_CHN_NOT_ENABLE HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_VO_CHN_NOT_ENABLE) 133 #define HI_ERR_VO_CHN_NOT_CONFIG HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_VO_CHN_NOT_CONFIG) 134 #define HI_ERR_VO_CHN_NOT_ALLOC HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_VO_CHN_NOT_ALLOC) 135 #define HI_ERR_VO_CHN_AREA_OVERLAP HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_VO_CHN_AREA_OVERLAP) 136 137 /* Cascade Relatvie error code */ 138 #define HI_ERR_VO_INVALID_PATTERN HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_VO_CCD_INVALID_PAT) 139 #define HI_ERR_VO_INVALID_POSITION HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_VO_CCD_INVALID_POS) 140 141 /* MISCellaneous error code */ 142 #define HI_ERR_VO_WAIT_TIMEOUT HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_VO_WAIT_TIMEOUT) 143 #define HI_ERR_VO_INVALID_VFRAME HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_VO_INVALID_VFRAME) 144 #define HI_ERR_VO_INVALID_RECT_PARA HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_VO_INVALID_RECT_PARA) 145 #define HI_ERR_VO_SETBEGIN_ALREADY HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_VO_SETBEGIN_ALREADY) 146 #define HI_ERR_VO_SETBEGIN_NOTYET HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_VO_SETBEGIN_NOTYET) 147 #define HI_ERR_VO_SETEND_ALREADY HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_VO_SETEND_ALREADY) 148 #define HI_ERR_VO_SETEND_NOTYET HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_VO_SETEND_NOTYET) 149 150 /* Synchronization group relative error code */ 151 #define HI_ERR_VO_GRP_INVALID_ID HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_INVALID_ID) 152 #define HI_ERR_VO_GRP_NOT_CREATE HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_NOT_CREATE) 153 #define HI_ERR_VO_GRP_HAS_CREATED HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_HAS_CREATED) 154 #define HI_ERR_VO_GRP_NOT_DESTROY HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_NOT_DESTROY) 155 #define HI_ERR_VO_GRP_CHN_FULL HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_CHN_FULL) 156 #define HI_ERR_VO_GRP_CHN_EMPTY HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_CHN_EMPTY) 157 #define HI_ERR_VO_GRP_CHN_NOT_EMPTY HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_CHN_NOT_EMPTY) 158 #define HI_ERR_VO_GRP_INVALID_SYN_MODE HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_INVALID_SYN_MODE) 159 #define HI_ERR_VO_GRP_INVALID_BASE_PTS HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_INVALID_BASE_PTS) 160 #define HI_ERR_VO_GRP_NOT_START HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_NOT_START) 161 #define HI_ERR_VO_GRP_NOT_STOP HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_NOT_STOP) 162 #define HI_ERR_VO_GRP_INVALID_FRMRATE HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_INVALID_FRMRATE) 163 #define HI_ERR_VO_GRP_CHN_HAS_REG HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_CHN_HAS_REG) 164 #define HI_ERR_VO_GRP_CHN_NOT_REG HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_CHN_NOT_REG) 165 #define HI_ERR_VO_GRP_CHN_NOT_UNREG HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_CHN_NOT_UNREG) 166 #define HI_ERR_VO_GRP_BASE_NOT_CFG HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_BASE_NOT_CFG) 167 168 /* Graphics layer relative error code */ 169 #define HI_ERR_VO_GFX_NOT_DISABLE HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_GFX_NOT_DISABLE) 170 #define HI_ERR_VO_GFX_NOT_BIND HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_GFX_NOT_BIND) 171 #define HI_ERR_VO_GFX_NOT_UNBIND HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_GFX_NOT_UNBIND) 172 #define HI_ERR_VO_GFX_INVALID_ID HI_DEF_ERR(HI_ID_VO, EN_ERR_LEVEL_ERROR, ERR_GFX_INVALID_ID) 173 174 /* VO video output interface type */ 175 #define VO_INTF_CVBS (0x01L << 0) 176 #define VO_INTF_YPBPR (0x01L << 1) 177 #define VO_INTF_VGA (0x01L << 2) 178 #define VO_INTF_BT656 (0x01L << 3) 179 #define VO_INTF_BT1120 (0x01L << 4) 180 #define VO_INTF_HDMI (0x01L << 5) 181 #define VO_INTF_LCD (0x01L << 6) 182 #define VO_INTF_BT656_H (0x01L << 7) 183 #define VO_INTF_BT656_L (0x01L << 8) 184 #define VO_INTF_LCD_6BIT (0x01L << 9) 185 #define VO_INTF_LCD_8BIT (0x01L << 10) 186 #define VO_INTF_LCD_16BIT (0x01L << 11) 187 #define VO_INTF_LCD_18BIT (0x01L << 12) 188 #define VO_INTF_LCD_24BIT (0x01L << 13) 189 #define VO_INTF_MIPI (0x01L << 14) 190 #define VO_INTF_MIPI_SLAVE (0x01L << 15) 191 192 typedef HI_U32 VO_INTF_TYPE_E; 193 194 typedef enum hiVO_INTF_SYNC_E { 195 VO_OUTPUT_PAL = 0, /* PAL standard */ 196 VO_OUTPUT_NTSC, /* NTSC standard */ 197 198 VO_OUTPUT_1080P24, /* 1920 x 1080 at 24 Hz. */ 199 VO_OUTPUT_1080P25, /* 1920 x 1080 at 25 Hz. */ 200 VO_OUTPUT_1080P30, /* 1920 x 1080 at 30 Hz. */ 201 202 VO_OUTPUT_720P50, /* 1280 x 720 at 50 Hz. */ 203 VO_OUTPUT_720P60, /* 1280 x 720 at 60 Hz. */ 204 VO_OUTPUT_1080I50, /* 1920 x 1080 at 50 Hz, interlace. */ 205 VO_OUTPUT_1080I60, /* 1920 x 1080 at 60 Hz, interlace. */ 206 VO_OUTPUT_1080P50, /* 1920 x 1080 at 50 Hz. */ 207 VO_OUTPUT_1080P60, /* 1920 x 1080 at 60 Hz. */ 208 209 VO_OUTPUT_576P50, /* 720 x 576 at 50 Hz. */ 210 VO_OUTPUT_480P60, /* 720 x 480 at 60 Hz. */ 211 212 VO_OUTPUT_800x600_60, /* VESA 800 x 600 at 60 Hz (non-interlaced) */ 213 VO_OUTPUT_1024x768_60, /* VESA 1024 x 768 at 60 Hz (non-interlaced) */ 214 VO_OUTPUT_1280x1024_60, /* VESA 1280 x 1024 at 60 Hz (non-interlaced) */ 215 VO_OUTPUT_1366x768_60, /* VESA 1366 x 768 at 60 Hz (non-interlaced) */ 216 VO_OUTPUT_1440x900_60, /* VESA 1440 x 900 at 60 Hz (non-interlaced) CVT Compliant */ 217 VO_OUTPUT_1280x800_60, /* 1280*800@60Hz VGA@60Hz */ 218 VO_OUTPUT_1600x1200_60, /* VESA 1600 x 1200 at 60 Hz (non-interlaced) */ 219 VO_OUTPUT_1680x1050_60, /* VESA 1680 x 1050 at 60 Hz (non-interlaced) */ 220 VO_OUTPUT_1920x1200_60, /* VESA 1920 x 1600 at 60 Hz (non-interlaced) CVT (Reduced Blanking) */ 221 VO_OUTPUT_640x480_60, /* VESA 640 x 480 at 60 Hz (non-interlaced) CVT */ 222 VO_OUTPUT_960H_PAL, /* ITU-R BT.1302 960 x 576 at 50 Hz (interlaced) */ 223 VO_OUTPUT_960H_NTSC, /* ITU-R BT.1302 960 x 480 at 60 Hz (interlaced) */ 224 VO_OUTPUT_1920x2160_30, /* 1920x2160_30 */ 225 VO_OUTPUT_2560x1440_30, /* 2560x1440_30 */ 226 VO_OUTPUT_2560x1440_60, /* 2560x1440_60 */ 227 VO_OUTPUT_2560x1600_60, /* 2560x1600_60 */ 228 VO_OUTPUT_3840x2160_24, /* 3840x2160_24 */ 229 VO_OUTPUT_3840x2160_25, /* 3840x2160_25 */ 230 VO_OUTPUT_3840x2160_30, /* 3840x2160_30 */ 231 VO_OUTPUT_3840x2160_50, /* 3840x2160_50 */ 232 VO_OUTPUT_3840x2160_60, /* 3840x2160_60 */ 233 VO_OUTPUT_4096x2160_24, /* 4096x2160_24 */ 234 VO_OUTPUT_4096x2160_25, /* 4096x2160_25 */ 235 VO_OUTPUT_4096x2160_30, /* 4096x2160_30 */ 236 VO_OUTPUT_4096x2160_50, /* 4096x2160_50 */ 237 VO_OUTPUT_4096x2160_60, /* 4096x2160_60 */ 238 VO_OUTPUT_320x240_60, /* For ota5182 at 60 Hz (8bit) */ 239 VO_OUTPUT_320x240_50, /* For ili9342 at 50 Hz (6bit) */ 240 VO_OUTPUT_240x320_50, /* Hi3559AV100: For ili9341 at 50 Hz (6bit) */ 241 /* Hi3556AV100/Hi3519AV100: For st7789 at 50Hz(6bit) */ 242 VO_OUTPUT_240x320_60, /* For ili9341 at 60 Hz (16bit) */ 243 VO_OUTPUT_800x600_50, /* For LCD at 50 Hz (24bit) */ 244 VO_OUTPUT_720x1280_60, /* For MIPI DSI Tx 720 x1280 at 60 Hz */ 245 VO_OUTPUT_1080x1920_60, /* For MIPI DSI Tx 1080x1920 at 60 Hz */ 246 VO_OUTPUT_7680x4320_30, /* For HDMI2.1 at 30 Hz */ 247 VO_OUTPUT_USER, /* User timing. */ 248 249 VO_OUTPUT_BUTT 250 } VO_INTF_SYNC_E; 251 252 typedef enum hiVO_ZOOM_IN_E { 253 VO_ZOOM_IN_RECT = 0, /* Zoom in by rect */ 254 VO_ZOOM_IN_RATIO, /* Zoom in by ratio */ 255 VO_ZOOM_IN_BUTT 256 } VO_ZOOM_IN_E; 257 258 typedef enum hiVO_CSC_MATRIX_E { 259 VO_CSC_MATRIX_IDENTITY = 0, /* Identity CSC matrix. */ 260 261 VO_CSC_MATRIX_BT601_TO_BT709, /* BT601 to BT709 */ 262 VO_CSC_MATRIX_BT709_TO_BT601, /* BT709 to BT601 */ 263 264 VO_CSC_MATRIX_BT601_TO_RGB_PC, /* BT601 to RGB */ 265 VO_CSC_MATRIX_BT709_TO_RGB_PC, /* BT709 to RGB */ 266 267 VO_CSC_MATRIX_RGB_TO_BT601_PC, /* RGB to BT601 FULL */ 268 VO_CSC_MATRIX_RGB_TO_BT709_PC, /* RGB to BT709 FULL */ 269 270 VO_CSC_MATRIX_RGB_TO_BT2020_PC, /* RGB to BT.2020 */ 271 VO_CSC_MATRIX_BT2020_TO_RGB_PC, /* BT.2020 to RGB */ 272 273 VO_CSC_MATRIX_RGB_TO_BT601_TV, /* RGB to BT601 LIMIT */ 274 VO_CSC_MATRIX_RGB_TO_BT709_TV, /* RGB to BT709 LIMIT */ 275 276 VO_CSC_MATRIX_BUTT 277 } VO_CSC_MATRIX_E; 278 279 typedef struct hiVO_CHN_ATTR_S { 280 HI_U32 u32Priority; /* Video out overlay pri sd */ 281 RECT_S stRect; /* Rectangle of video output channel */ 282 HI_BOOL bDeflicker; /* Deflicker or not sd */ 283 } VO_CHN_ATTR_S; 284 285 typedef struct hiVO_CHN_PARAM_S { 286 ASPECT_RATIO_S stAspectRatio; /* RW; aspect ratio */ 287 } VO_CHN_PARAM_S; 288 289 typedef struct hiVO_BORDER_S { 290 HI_BOOL bBorderEn; /* RW; Do frame or not */ 291 BORDER_S stBorder; /* RW; frame's top, bottom, left, right width and color */ 292 } VO_BORDER_S; 293 294 typedef struct hiVO_QUERY_STATUS_S { 295 HI_U32 u32ChnBufUsed; /* Channel buffer that been occupied */ 296 } VO_QUERY_STATUS_S; 297 298 typedef struct hiVO_SYNC_INFO_S { 299 HI_BOOL bSynm; /* RW; sync mode(0:timing,as BT.656; 1:signal,as LCD) */ 300 HI_BOOL bIop; /* RW; interlaced or progressive display(0:i; 1:p) */ 301 HI_U8 u8Intfb; /* RW; interlace bit width while output */ 302 303 HI_U16 u16Vact; /* RW; vertical active area */ 304 HI_U16 u16Vbb; /* RW; vertical back blank porch */ 305 HI_U16 u16Vfb; /* RW; vertical front blank porch */ 306 307 HI_U16 u16Hact; /* RW; horizontal active area */ 308 HI_U16 u16Hbb; /* RW; horizontal back blank porch */ 309 HI_U16 u16Hfb; /* RW; horizontal front blank porch */ 310 HI_U16 u16Hmid; /* RW; bottom horizontal active area */ 311 312 HI_U16 u16Bvact; /* RW; bottom vertical active area */ 313 HI_U16 u16Bvbb; /* RW; bottom vertical back blank porch */ 314 HI_U16 u16Bvfb; /* RW; bottom vertical front blank porch */ 315 316 HI_U16 u16Hpw; /* RW; horizontal pulse width */ 317 HI_U16 u16Vpw; /* RW; vertical pulse width */ 318 319 HI_BOOL bIdv; /* RW; inverse data valid of output */ 320 HI_BOOL bIhs; /* RW; inverse horizontal synch signal */ 321 HI_BOOL bIvs; /* RW; inverse vertical synch signal */ 322 } VO_SYNC_INFO_S; 323 324 typedef struct hiVO_PUB_ATTR_S { 325 HI_U32 u32BgColor; /* RW; Background color of a device, in RGB format. */ 326 VO_INTF_TYPE_E enIntfType; /* RW; Type of a VO interface */ 327 VO_INTF_SYNC_E enIntfSync; /* RW; Type of a VO interface timing */ 328 VO_SYNC_INFO_S stSyncInfo; /* RW; Information about VO interface timings */ 329 } VO_PUB_ATTR_S; 330 331 typedef struct hiVO_WBC_ATTR_S { 332 SIZE_S stTargetSize; /* RW; WBC Zoom target size */ 333 PIXEL_FORMAT_E enPixelFormat; /* RW; the pixel format of WBC output */ 334 HI_U32 u32FrameRate; /* RW; frame rate control */ 335 DYNAMIC_RANGE_E enDynamicRange; /* RW; Write back dynamic range type */ 336 COMPRESS_MODE_E enCompressMode; /* RW; Write back Compressing mode */ 337 } VO_WBC_ATTR_S; 338 339 typedef enum hiVO_WBC_MODE_E { 340 VO_WBC_MODE_NORMAL = 0, /* In this mode, wbc will capture frames according to dev frame rate 341 and wbc frame rate */ 342 VO_WBC_MODE_DROP_REPEAT, /* In this mode, wbc will drop dev repeat frame, and capture the real frame 343 according to video layer's display rate and wbc frame rate */ 344 VO_WBC_MODE_PROG_TO_INTL, /* In this mode, wbc will drop dev repeat frame which repeats more than 3 times, 345 and change two progressive frames to one interlace frame */ 346 VO_WBC_MODE_BUTT, 347 } VO_WBC_MODE_E; 348 349 typedef enum hiVO_WBC_SOURCE_TYPE_E { 350 VO_WBC_SOURCE_DEV = 0x0, /* WBC source is device */ 351 VO_WBC_SOURCE_VIDEO = 0x1, /* WBC source is video layer */ 352 VO_WBC_SOURCE_GRAPHIC = 0x2, /* WBC source is graphic layer. Warning: not supported */ 353 VO_WBC_SOURCE_BUTT 354 } VO_WBC_SOURCE_TYPE_E; 355 356 typedef struct hiVO_WBC_SOURCE_S { 357 VO_WBC_SOURCE_TYPE_E enSourceType; /* RW; WBC source's type */ 358 HI_U32 u32SourceId; /* RW; WBC source's ID */ 359 } VO_WBC_SOURCE_S; 360 361 typedef enum hiVO_PART_MODE_E { 362 VO_PART_MODE_SINGLE = 0, /* single partition, which use software to make multi-picture in one hardware cell */ 363 VO_PART_MODE_MULTI = 1, /* muliti partition, each partition is a hardware cell */ 364 VO_PART_MODE_BUTT 365 } VO_PART_MODE_E; 366 367 typedef struct hiVO_VIDEO_LAYER_ATTR_S { 368 RECT_S stDispRect; /* RW; Display resolution */ 369 SIZE_S stImageSize; /* RW; Canvas size of the video layer */ 370 HI_U32 u32DispFrmRt; /* RW; Display frame rate */ 371 PIXEL_FORMAT_E enPixFormat; /* RW; Pixel format of the video layer */ 372 HI_BOOL bDoubleFrame; /* RW; Whether to double frames */ 373 HI_BOOL bClusterMode; /* RW; Whether to take Cluster way to use memory */ 374 DYNAMIC_RANGE_E enDstDynamicRange; /* RW; Video Layer output dynamic range type */ 375 } VO_VIDEO_LAYER_ATTR_S; 376 377 typedef struct hiVO_LAYER_PARAM_S { 378 ASPECT_RATIO_S stAspectRatio; /* RW; aspect ratio */ 379 } VO_LAYER_PARAM_S; 380 381 typedef struct hiVO_ZOOM_RATIO_S { 382 HI_U32 u32XRatio; /* RW; Range: [0, 1000]; XRatio = x * 1000 / W, 383 x means the start point to be zoomed, W means displaying channel's width. */ 384 HI_U32 u32YRatio; /* RW; Range: [0, 1000]; YRatio = y * 1000 / H, 385 y means the start point to be zoomed, H means displaying channel's height. */ 386 HI_U32 u32WRatio; /* RW; Range: [0, 1000]; WRatio = w * 1000 / W, 387 w means the width to be zoomed, W means displaying channel's width. */ 388 HI_U32 u32HRatio; /* RW; Range: [0, 1000]; HRatio = h * 1000 / H, 389 h means the height to be zoomed, H means displaying channel's height. */ 390 } VO_ZOOM_RATIO_S; 391 392 typedef struct hiVO_ZOOM_ATTR_S { 393 VO_ZOOM_IN_E enZoomType; /* choose the type of zoom in */ 394 union { 395 RECT_S stZoomRect; /* zoom in by rect */ 396 VO_ZOOM_RATIO_S stZoomRatio; /* zoom in by ratio */ 397 }; 398 } VO_ZOOM_ATTR_S; 399 400 typedef struct hiVO_CSC_S { 401 VO_CSC_MATRIX_E enCscMatrix; /* CSC matrix */ 402 HI_U32 u32Luma; /* RW; Range: [0, 100]; luminance, default: 50 */ 403 HI_U32 u32Contrast; /* RW; Range: [0, 100]; contrast, default: 50 */ 404 HI_U32 u32Hue; /* RW; Range: [0, 100]; hue, default: 50 */ 405 HI_U32 u32Satuature; /* RW; Range: [0, 100]; satuature, default: 50 */ 406 } VO_CSC_S; 407 408 typedef struct hiVO_REGION_INFO_S { 409 HI_U32 u32RegionNum; /* count of the region */ 410 RECT_S *ATTRIBUTE pstRegion; /* region attribute */ 411 } VO_REGION_INFO_S; 412 413 typedef struct hiVO_LAYER_BOUNDARY_S { 414 HI_U32 u32Width; 415 HI_U32 u32Color[2]; /* RW; 2 color indexes */ 416 } VO_LAYER_BOUNDARY_S; 417 418 typedef struct hiVO_CHN_BOUNDARY_S { 419 HI_BOOL bBoundaryEn; /* RW; do Frame or not */ 420 HI_U32 u32ColorIndex; /* RW; the index of Frame color,{0,1} */ 421 } VO_CHN_BOUNDARY_S; 422 423 typedef struct hiVO_MOD_PARAM_S { 424 HI_BOOL bTransparentTransmit; /* RW, Range: [0, 1]; YC(Luminance and Chrominance) changes or not 425 when passing through VO */ 426 HI_BOOL bExitDev; 427 HI_BOOL bWbcBgBlackEn; 428 HI_BOOL bDevClkExtEn; 429 HI_BOOL bSaveBufMode[VO_MAX_PHY_DEV_NUM]; /* save buff mode */ 430 } VO_MOD_PARAM_S; 431 432 typedef enum hiVO_CLK_SOURCE_E { 433 VO_CLK_SOURCE_PLL, 434 VO_CLK_SOURCE_LCDMCLK, 435 436 VO_CLK_SOURCE_BUTT 437 } VO_CLK_SOURCE_E; 438 439 typedef struct hiVO_USER_INTFSYNC_PLL_S { 440 HI_U32 u32Fbdiv; 441 HI_U32 u32Frac; 442 HI_U32 u32Refdiv; 443 HI_U32 u32Postdiv1; 444 HI_U32 u32Postdiv2; 445 } VO_USER_INTFSYNC_PLL_S; 446 447 typedef struct hiVO_USER_INTFSYNC_ATTR_S { 448 VO_CLK_SOURCE_E enClkSource; 449 450 union { 451 VO_USER_INTFSYNC_PLL_S stUserSyncPll; 452 HI_U32 u32LcdMClkDiv; 453 }; 454 } VO_USER_INTFSYNC_ATTR_S; 455 456 typedef struct hiVO_USER_INTFSYNC_INFO_S { 457 VO_USER_INTFSYNC_ATTR_S stUserIntfSyncAttr; 458 HI_U32 u32PreDiv; 459 HI_U32 u32DevDiv; 460 HI_BOOL bClkReverse; 461 } VO_USER_INTFSYNC_INFO_S; 462 463 typedef enum hiVO_MIRROR_MODE_E { 464 VO_MIRROR_NONE = 0, /* Mirror mode is none */ 465 VO_MIRROR_HOR, /* Mirror mode is horizontal mirror */ 466 VO_MIRROR_BUTT 467 } VO_MIRROR_MODE_E; 468 469 #ifdef __cplusplus 470 #if __cplusplus 471 } 472 #endif 473 #endif /* End of #ifdef __cplusplus */ 474 475 #endif /* End of #ifndef __HI_COMM_VO_H__ */ 476