1 /* 2 * Copyright (c) 2022 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef __HI_MIPI_H__ 17 #define __HI_MIPI_H__ 18 19 typedef unsigned int combo_dev_t; 20 typedef unsigned int sns_rst_source_t; 21 typedef unsigned int sns_clk_source_t; 22 23 #define MIPI_LANE_NUM 4 24 #define LVDS_LANE_NUM 4 25 26 #define WDR_VC_NUM 4 27 #define SYNC_CODE_NUM 4 28 29 #define MIPI_RX_MAX_DEV_NUM 2 30 #define CMOS_MAX_DEV_NUM 1 31 32 #define SNS_MAX_CLK_SOURCE_NUM 2 33 #define SNS_MAX_RST_SOURCE_NUM 2 34 #define MAX_EXT_DATA_TYPE_NUM 3 35 36 #define HI_ERR(x...) \ 37 do { \ 38 osal_printk("%s(%d): ", __FUNCTION__, __LINE__); \ 39 osal_printk(x); \ 40 } while (0) 41 42 typedef enum { 43 LANE_DIVIDE_MODE_0 = 0, 44 LANE_DIVIDE_MODE_1 = 1, 45 LANE_DIVIDE_MODE_BUTT 46 } lane_divide_mode_t; 47 48 typedef enum { 49 WORK_MODE_LVDS = 0x0, 50 WORK_MODE_MIPI = 0x1, 51 WORK_MODE_CMOS = 0x2, 52 WORK_MODE_BT1120 = 0x3, 53 WORK_MODE_SLVS = 0x4, 54 WORK_MODE_BUTT 55 } work_mode_t; 56 57 typedef enum { 58 INPUT_MODE_MIPI = 0x0, /* mipi */ 59 INPUT_MODE_SUBLVDS = 0x1, /* SUB_LVDS */ 60 INPUT_MODE_LVDS = 0x2, /* LVDS */ 61 INPUT_MODE_HISPI = 0x3, /* HISPI */ 62 INPUT_MODE_CMOS = 0x4, /* CMOS */ 63 INPUT_MODE_BT601 = 0x5, /* BT601 */ 64 INPUT_MODE_BT656 = 0x6, /* BT656 */ 65 INPUT_MODE_BT1120 = 0x7, /* BT1120 */ 66 INPUT_MODE_BYPASS = 0x8, /* MIPI Bypass */ 67 68 INPUT_MODE_BUTT 69 } input_mode_t; 70 71 typedef enum { 72 MIPI_DATA_RATE_X1 = 0, /* output 1 pixel per clock */ 73 MIPI_DATA_RATE_X2 = 1, /* output 2 pixel per clock */ 74 75 MIPI_DATA_RATE_BUTT 76 } mipi_data_rate_t; 77 78 typedef struct { 79 int x; 80 int y; 81 unsigned int width; 82 unsigned int height; 83 } img_rect_t; 84 85 typedef struct { 86 unsigned int width; 87 unsigned int height; 88 } img_size_t; 89 90 typedef enum { 91 DATA_TYPE_RAW_8BIT = 0, 92 DATA_TYPE_RAW_10BIT, 93 DATA_TYPE_RAW_12BIT, 94 DATA_TYPE_RAW_14BIT, 95 DATA_TYPE_RAW_16BIT, 96 DATA_TYPE_YUV420_8BIT_NORMAL, 97 DATA_TYPE_YUV420_8BIT_LEGACY, 98 DATA_TYPE_YUV422_8BIT, 99 DATA_TYPE_YUV422_PACKED, /* yuv422 8bit transform user define 16bit raw */ 100 DATA_TYPE_BUTT 101 } data_type_t; 102 103 typedef struct { 104 combo_dev_t devno; 105 unsigned int num; 106 unsigned int ext_data_bit_width[MAX_EXT_DATA_TYPE_NUM]; 107 unsigned int ext_data_type[MAX_EXT_DATA_TYPE_NUM]; 108 } ext_data_type_t; 109 110 /* MIPI D_PHY WDR MODE defines */ 111 typedef enum { 112 HI_MIPI_WDR_MODE_NONE = 0x0, 113 HI_MIPI_WDR_MODE_VC = 0x1, /* Virtual Channel */ 114 HI_MIPI_WDR_MODE_DT = 0x2, /* Data Type */ 115 HI_MIPI_WDR_MODE_DOL = 0x3, /* DOL Mode */ 116 HI_MIPI_WDR_MODE_BUTT 117 } mipi_wdr_mode_t; 118 119 typedef struct { 120 data_type_t input_data_type; /* data type: 8/10/12/14/16 bit */ 121 mipi_wdr_mode_t wdr_mode; /* MIPI WDR mode */ 122 short lane_id[MIPI_LANE_NUM]; /* lane_id: -1 - disable */ 123 124 union { 125 short data_type[WDR_VC_NUM]; /* used by the HI_MIPI_WDR_MODE_DT */ 126 }; 127 } mipi_dev_attr_t; 128 129 typedef enum { 130 HI_WDR_MODE_NONE = 0x0, 131 HI_WDR_MODE_2F = 0x1, 132 HI_WDR_MODE_3F = 0x2, 133 HI_WDR_MODE_4F = 0x3, 134 HI_WDR_MODE_DOL_2F = 0x4, 135 HI_WDR_MODE_DOL_3F = 0x5, 136 HI_WDR_MODE_DOL_4F = 0x6, 137 HI_WDR_MODE_BUTT 138 } wdr_mode_t; 139 140 typedef enum { 141 LVDS_SYNC_MODE_SOF = 0, /* sensor SOL, EOL, SOF, EOF */ 142 LVDS_SYNC_MODE_SAV, /* SAV, EAV */ 143 LVDS_SYNC_MODE_BUTT 144 } lvds_sync_mode_t; 145 146 typedef enum { 147 LVDS_VSYNC_NORMAL = 0x00, 148 LVDS_VSYNC_SHARE = 0x01, 149 LVDS_VSYNC_HCONNECT = 0x02, 150 LVDS_VSYNC_BUTT 151 } lvds_vsync_type_t; 152 153 typedef struct { 154 lvds_vsync_type_t sync_type; 155 156 /* hconnect vsync blanking len, valid when the sync_type is LVDS_VSYNC_HCONNECT */ 157 unsigned short hblank1; 158 unsigned short hblank2; 159 } lvds_vsync_attr_t; 160 161 typedef enum { 162 LVDS_FID_NONE = 0x00, 163 LVDS_FID_IN_SAV = 0x01, /* frame identification id in SAV 4th */ 164 LVDS_FID_IN_DATA = 0x02, /* frame identification id in first data */ 165 LVDS_FID_BUTT 166 } lvds_fid_type_t; 167 168 typedef struct { 169 lvds_fid_type_t fid_type; 170 171 /* 172 * Sony DOL has the Frame Information Line, in DOL H-Connection mode, 173 * should configure this flag as false to disable output the Frame Information Line 174 */ 175 unsigned char output_fil; 176 } lvds_fid_attr_t; 177 178 typedef enum { 179 LVDS_ENDIAN_LITTLE = 0x0, 180 LVDS_ENDIAN_BIG = 0x1, 181 LVDS_ENDIAN_BUTT 182 } lvds_bit_endian_t; 183 184 typedef struct { 185 data_type_t input_data_type; /* data type: 8/10/12/14 bit */ 186 wdr_mode_t wdr_mode; /* WDR mode */ 187 188 lvds_sync_mode_t sync_mode; /* sync mode: SOF, SAV */ 189 lvds_vsync_attr_t vsync_attr; /* normal, share, hconnect */ 190 lvds_fid_attr_t fid_attr; /* frame identification code */ 191 192 lvds_bit_endian_t data_endian; /* data endian: little/big */ 193 lvds_bit_endian_t sync_code_endian; /* sync code endian: little/big */ 194 short lane_id[LVDS_LANE_NUM]; /* lane_id: -1 - disable */ 195 196 /* 197 * each vc has 4 params, sync_code[i]: 198 * sync_mode is SYNC_MODE_SOF: SOF, EOF, SOL, EOL 199 * sync_mode is SYNC_MODE_SAV: invalid sav, invalid eav, valid sav, valid eav 200 */ 201 unsigned short sync_code[LVDS_LANE_NUM][WDR_VC_NUM][SYNC_CODE_NUM]; 202 } lvds_dev_attr_t; 203 204 typedef struct { 205 combo_dev_t devno; /* device number */ 206 input_mode_t input_mode; /* input mode: MIPI/LVDS/SUBLVDS/HISPI/DC */ 207 mipi_data_rate_t data_rate; 208 img_rect_t img_rect; /* MIPI Rx device crop area (corresponding to the oringnal sensor input image size) */ 209 210 union { 211 mipi_dev_attr_t mipi_attr; 212 lvds_dev_attr_t lvds_attr; 213 }; 214 } combo_dev_attr_t; 215 216 typedef enum { 217 PHY_CMV_GE1200MV = 0x00, 218 PHY_CMV_LT1200MV = 0x01, 219 PHY_CMV_BUTT 220 } phy_cmv_mode_t; 221 222 typedef struct { 223 combo_dev_t devno; 224 phy_cmv_mode_t cmv_mode; 225 } phy_cmv_t; 226 227 #define HI_MIPI_IOC_MAGIC 'm' 228 229 /* init data lane, input mode, data type */ 230 #define HI_MIPI_SET_DEV_ATTR _IOW(HI_MIPI_IOC_MAGIC, 0x01, combo_dev_attr_t) 231 232 /* set phy common mode voltage mode */ 233 #define HI_MIPI_SET_PHY_CMVMODE _IOW(HI_MIPI_IOC_MAGIC, 0x04, phy_cmv_t) 234 235 /* reset sensor */ 236 #define HI_MIPI_RESET_SENSOR _IOW(HI_MIPI_IOC_MAGIC, 0x05, sns_rst_source_t) 237 238 /* unreset sensor */ 239 #define HI_MIPI_UNRESET_SENSOR _IOW(HI_MIPI_IOC_MAGIC, 0x06, sns_rst_source_t) 240 241 /* reset mipi */ 242 #define HI_MIPI_RESET_MIPI _IOW(HI_MIPI_IOC_MAGIC, 0x07, combo_dev_t) 243 244 /* unreset mipi */ 245 #define HI_MIPI_UNRESET_MIPI _IOW(HI_MIPI_IOC_MAGIC, 0x08, combo_dev_t) 246 247 /* reset slvs */ 248 #define HI_MIPI_RESET_SLVS _IOW(HI_MIPI_IOC_MAGIC, 0x09, combo_dev_t) 249 250 /* unreset slvs */ 251 #define HI_MIPI_UNRESET_SLVS _IOW(HI_MIPI_IOC_MAGIC, 0x0a, combo_dev_t) 252 253 /* set mipi hs_mode */ 254 #define HI_MIPI_SET_HS_MODE _IOW(HI_MIPI_IOC_MAGIC, 0x0b, lane_divide_mode_t) 255 256 /* enable mipi clock */ 257 #define HI_MIPI_ENABLE_MIPI_CLOCK _IOW(HI_MIPI_IOC_MAGIC, 0x0c, combo_dev_t) 258 259 /* disable mipi clock */ 260 #define HI_MIPI_DISABLE_MIPI_CLOCK _IOW(HI_MIPI_IOC_MAGIC, 0x0d, combo_dev_t) 261 262 /* enable slvs clock */ 263 #define HI_MIPI_ENABLE_SLVS_CLOCK _IOW(HI_MIPI_IOC_MAGIC, 0x0e, combo_dev_t) 264 265 /* disable slvs clock */ 266 #define HI_MIPI_DISABLE_SLVS_CLOCK _IOW(HI_MIPI_IOC_MAGIC, 0x0f, combo_dev_t) 267 268 /* enable sensor clock */ 269 #define HI_MIPI_ENABLE_SENSOR_CLOCK _IOW(HI_MIPI_IOC_MAGIC, 0x10, sns_clk_source_t) 270 271 /* disable sensor clock */ 272 #define HI_MIPI_DISABLE_SENSOR_CLOCK _IOW(HI_MIPI_IOC_MAGIC, 0x11, sns_clk_source_t) 273 274 #define HI_MIPI_SET_EXT_DATA_TYPE _IOW(HI_MIPI_IOC_MAGIC, 0x12, ext_data_type_t) 275 276 #endif /* __HI_MIPI_RX_H__ */ 277