1 /*
2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15
16 #include <app_demo_spi.h>
17
18 hi_u8 g_spi_send_buf[BUF_LENGTH];
19 hi_u8 g_spi_rcv_buf[BUF_LENGTH];
20 hi_spi_idx g_spi_id = HI_SPI_ID_0;
21 hi_u32 g_transfer_lenth = 0;
22 hi_u32 g_test_loop = 0;
23 hi_u32 g_lb_loop = 0;
24 hi_u32 g_delay_us_spi = 0;
25 hi_spi_cfg_data_width g_data_width = HI_SPI_CFG_DATA_WIDTH_E_7BIT;
26
prepare_func(hi_void)27 hi_void prepare_func(hi_void)
28 {
29 test_spi_printf("prepare");
30 }
31
restore_func(hi_void)32 hi_void restore_func(hi_void)
33 {
34 test_spi_printf("restore");
35 }
36
app_demo_spi_print_reg(hi_spi_idx spi_id)37 hi_void app_demo_spi_print_reg(hi_spi_idx spi_id)
38 {
39 hi_u16 reg_val;
40 hi_u32 reg_base;
41 if (spi_id == HI_SPI_ID_0) {
42 reg_base = HI_SSP0_REG_BASE;
43 } else {
44 reg_base = HI_SSP1_REG_BASE;
45 }
46 test_spi_printf("BASE_ADDR=%x", reg_base);
47 reg_val = hi_reg_read_val16(reg_base + 0x00);
48 test_spi_printf("REG_SPI_CR0=%x", reg_val);
49 reg_val = hi_reg_read_val16(reg_base + 0x04);
50 test_spi_printf("REG_SPI_CR1=%x", reg_val);
51 reg_val = hi_reg_read_val16(reg_base + 0x0c);
52 test_spi_printf("REG_SPI_SR=%x", reg_val);
53 reg_val = hi_reg_read_val16(reg_base + 0x10);
54 test_spi_printf("REG_SPI_CPSR=%x", reg_val);
55 reg_val = hi_reg_read_val16(reg_base + 0x14);
56 test_spi_printf("REG_SPI_IMSC=%x", reg_val);
57 reg_val = hi_reg_read_val16(reg_base + 0x18);
58 test_spi_printf("REG_SPI_RIS=%x", reg_val);
59 reg_val = hi_reg_read_val16(reg_base + 0x1c);
60 test_spi_printf("REG_SPI_MIS=%x", reg_val);
61 reg_val = hi_reg_read_val16(reg_base + 0x24);
62 test_spi_printf("REG_SPI_DMACR=%x", reg_val);
63 reg_val = hi_reg_read_val16(reg_base + 0x28);
64 test_spi_printf("REG_SPI_TXFIFOCR=%x", reg_val);
65 reg_val = hi_reg_read_val16(reg_base + 0x2c);
66 test_spi_printf("REG_SPI_RXFIFOCR=%x", reg_val);
67 }
68
app_demo_spi_print_test_para(const test_spi_para * spi_para)69 hi_void app_demo_spi_print_test_para(const test_spi_para *spi_para)
70 {
71 if (spi_para == HI_NULL) {
72 test_spi_printf("spi para is null\n");
73 return;
74 }
75 test_spi_printf("cpol:%d", spi_para->cfg_info.cpol);
76 test_spi_printf("cpha:%d", spi_para->cfg_info.cpha);
77 test_spi_printf("fram_mode:%d", spi_para->cfg_info.fram_mode);
78 test_spi_printf("data_width:%d", spi_para->cfg_info.data_width);
79 test_spi_printf("freq:%d", spi_para->cfg_info.freq);
80 test_spi_printf("spi id:%d", spi_para->spi_id);
81 test_spi_printf("loop:%d", spi_para->loop);
82 test_spi_printf("length:%d", spi_para->length);
83 test_spi_printf("irq:%d", spi_para->irq);
84 test_spi_printf("slave:%d", spi_para->slave);
85 test_spi_printf("lb:%d", spi_para->lb);
86 test_spi_printf("dma en:%d", spi_para->dma_en);
87 test_spi_printf("delay:%d", g_delay_us_spi);
88 }
89
print_err_send_buf_u8(const hi_u8 * buf,hi_u32 len)90 hi_void print_err_send_buf_u8(const hi_u8 *buf, hi_u32 len)
91 {
92 hi_u32 i;
93 for (i = 0; i < len; i++) {
94 test_spi_printf("%d", buf[i]);
95 }
96 }
97
print_err_send_buf_u16(const hi_u16 * buf,hi_u32 len)98 hi_void print_err_send_buf_u16(const hi_u16 *buf, hi_u32 len)
99 {
100 hi_u32 i;
101 for (i = 0; i < len; i++) {
102 test_spi_printf("%d", buf[i]);
103 }
104 }
105
print_err_rev_buf_u16(const hi_u16 * buf,const hi_u16 * cmp,hi_u32 len)106 hi_void print_err_rev_buf_u16(const hi_u16 *buf, const hi_u16 *cmp, hi_u32 len)
107 {
108 hi_u32 i;
109 for (i = 0; i < len; i++) {
110 test_spi_printf("%d, %d", cmp[i], buf[i]);
111 }
112 }
print_err_rev_buf_u8(const hi_u8 * buf,const hi_u8 * cmp,hi_u32 len)113 hi_void print_err_rev_buf_u8(const hi_u8 *buf, const hi_u8 *cmp, hi_u32 len)
114 {
115 hi_u32 i;
116 for (i = 0; i < len; i++) {
117 test_spi_printf("%d, %d", cmp[i], buf[i]);
118 }
119 }
120
121
app_demo_spi_init(hi_spi_idx id,const hi_spi_cfg_basic_info * spi_cfg_basic_info,hi_bool slave)122 hi_u32 app_demo_spi_init(hi_spi_idx id, const hi_spi_cfg_basic_info *spi_cfg_basic_info, hi_bool slave)
123 {
124 hi_u32 ret;
125 hi_spi_cfg_init_param init_param;
126 init_param.is_slave = slave;
127 ret = hi_spi_init(id, init_param, spi_cfg_basic_info);
128
129 test_spi_printf("app_demo_spi_init ret=%x", ret);
130 return ret;
131 }
132
app_demo_spi_config_gpio(hi_spi_idx id)133 hi_void app_demo_spi_config_gpio(hi_spi_idx id)
134 {
135 if (id == HI_SPI_ID_0) {
136 hi_io_set_func(HI_IO_NAME_GPIO_5, HI_IO_FUNC_GPIO_5_SPI0_CSN);
137 hi_io_set_func(HI_IO_NAME_GPIO_6, HI_IO_FUNC_GPIO_6_SPI0_CK);
138 hi_io_set_func(HI_IO_NAME_GPIO_7, HI_IO_FUNC_GPIO_7_SPI0_RXD);
139 hi_io_set_func(HI_IO_NAME_GPIO_8, HI_IO_FUNC_GPIO_8_SPI0_TXD);
140 hi_io_set_driver_strength(HI_IO_NAME_GPIO_6, HI_IO_DRIVER_STRENGTH_2);
141 } else {
142 hi_io_set_func(HI_IO_NAME_GPIO_0, HI_IO_FUNC_GPIO_0_SPI1_CK);
143 hi_io_set_func(HI_IO_NAME_GPIO_1, HI_IO_FUNC_GPIO_1_SPI1_RXD);
144 hi_io_set_func(HI_IO_NAME_GPIO_2, HI_IO_FUNC_GPIO_2_SPI1_TXD);
145 hi_io_set_func(HI_IO_NAME_GPIO_3, HI_IO_FUNC_GPIO_3_SPI1_CSN);
146 hi_io_set_driver_strength(HI_IO_NAME_GPIO_0, HI_IO_DRIVER_STRENGTH_2);
147 }
148 }
149
app_demo_spi_slave_send_8bits(hi_spi_idx spi_id)150 hi_u32 app_demo_spi_slave_send_8bits(hi_spi_idx spi_id)
151 {
152 hi_u32 i;
153 hi_u32 j;
154 hi_u32 while_times = 0;
155 hi_u32 ret;
156 hi_u32 err_times = 0;
157 if (g_transfer_lenth > BUF_LENGTH) {
158 return HI_ERR_FAILURE;
159 }
160 i = 0;
161 for (j = 0; j < g_transfer_lenth; j++) {
162 g_spi_send_buf[j] = (hi_u8)i;
163 i++;
164 }
165 do {
166 ret = hi_spi_slave_write(spi_id, g_spi_send_buf, g_transfer_lenth, 10000); /* time out 10000 ms */
167 if (ret != HI_ERR_SUCCESS) {
168 err_times += 1;
169 break;
170 }
171 hi_watchdog_feed();
172 while_times++;
173 } while (while_times < g_test_loop || g_test_loop == 0);
174 test_spi_printf("demo_spi_slave_send err_send: %d,while_times:%d, ret:%x", err_times, while_times, ret);
175 return ret;
176 }
177
app_demo_spi_slave_send_16bits(hi_spi_idx spi_id)178 hi_u32 app_demo_spi_slave_send_16bits(hi_spi_idx spi_id)
179 {
180 hi_u32 i;
181 hi_u32 j;
182 hi_u32 while_times = 0;
183 hi_u32 ret = HI_ERR_SUCCESS;
184 hi_u32 index;
185 hi_u32 err_times = 0;
186 hi_u32 send_len;
187 do {
188 i = 0;
189 index = 0;
190 while (index < g_transfer_lenth) {
191 send_len = min(g_transfer_lenth - index, BUF_LENGTH_HALF);
192 for (j = 0; j < send_len; j++) { /* loops 256 */
193 *((hi_u16 *)g_spi_send_buf + j) = (hi_u16)i;
194 i++;
195 }
196 ret = hi_spi_slave_write(spi_id, g_spi_send_buf, send_len * 2, 10000); /* 2:doubule the length 10000:ms */
197 if (ret != HI_ERR_SUCCESS) {
198 err_times++;
199 print_err_send_buf_u16((hi_u16 *)g_spi_send_buf, send_len);
200 break;
201 }
202 hi_watchdog_feed();
203 index += send_len; /* add 256 */
204 }
205 while_times++;
206 } while (while_times < g_test_loop || g_test_loop == 0);
207 test_spi_printf("demo_spi_slave_send err_send: %d,while_times:%d, ret:%x", err_times, while_times, ret);
208 return ret;
209 }
210
app_demo_spi_slave_send_task(hi_void * param)211 hi_void *app_demo_spi_slave_send_task(hi_void *param)
212 {
213 hi_spi_idx spi_id = *(hi_spi_idx*)param;
214 hi_u32 ret;
215 hi_u32 time_old;
216 hi_u32 time_new;
217 time_old = hi_get_milli_seconds();
218 if (g_data_width < HI_SPI_CFG_DATA_WIDTH_E_9BIT) {
219 ret = app_demo_spi_slave_send_8bits(spi_id);
220 } else {
221 ret = app_demo_spi_slave_send_16bits(spi_id);
222 }
223 if (ret != HI_ERR_SUCCESS) {
224 printf("app_demo_spi_slave_send fail: %x\n", ret);
225 }
226
227 time_new = hi_get_milli_seconds();
228 app_demo_spi_print_reg(spi_id);
229 test_spi_printf("demo_spi_slave_send time_old: %d,time_new %d, delt:%d", time_old, time_new, time_new - time_old);
230 ret = hi_spi_deinit(spi_id);
231 if (ret != HI_ERR_SUCCESS) {
232 printf("hi_spi_deinit fail: %x\n", ret);
233 }
234 return HI_NULL;
235 }
236
app_demo_spi_slave_receive_8bits(hi_spi_idx spi_id)237 hi_u32 app_demo_spi_slave_receive_8bits(hi_spi_idx spi_id)
238 {
239 hi_u8 cmp_buf[BUF_LENGTH];
240 hi_u32 while_times = 0;
241 hi_u32 i;
242 hi_u32 j;
243 hi_u32 ret;
244 hi_u32 err_times = 0;
245 i = 0;
246 if (g_transfer_lenth > BUF_LENGTH) {
247 return HI_ERR_FAILURE;
248 }
249 for (j = 0; j < g_transfer_lenth; j++) {
250 cmp_buf[j] = (hi_u8)i;
251 i++;
252 }
253 do {
254 while_times++;
255 memset_s(g_spi_rcv_buf, sizeof(g_spi_rcv_buf), 0x0, sizeof(g_spi_rcv_buf));
256 ret = hi_spi_slave_read(spi_id, g_spi_rcv_buf, g_transfer_lenth, 10000); /* time out 10000 ms */
257 if ((memcmp(g_spi_rcv_buf, cmp_buf, g_transfer_lenth) != 0) || (ret != HI_ERR_SUCCESS)) {
258 err_times++;
259 print_err_rev_buf_u8(g_spi_rcv_buf, cmp_buf, g_transfer_lenth);
260 break;
261 }
262 } while (while_times < g_test_loop || g_test_loop == 0);
263 test_spi_printf("demo_spi_rev err_rev: %d,while_times:%d, ret:%x", err_times, while_times, ret);
264 return ret;
265 }
266
app_demo_spi_slave_receive_16bits(hi_spi_idx spi_id)267 hi_u32 app_demo_spi_slave_receive_16bits(hi_spi_idx spi_id)
268 {
269 hi_u8 cmp_buf[BUF_LENGTH];
270 hi_u32 while_times = 0;
271 hi_u32 i;
272 hi_u32 j;
273 hi_u32 k;
274 hi_u32 ret = HI_ERR_SUCCESS;
275 hi_u32 err_times = 0;
276 hi_u32 rcv_len;
277 do {
278 k = 0;
279 while_times++;
280 i = 0;
281 while (k < g_transfer_lenth) {
282 rcv_len = min(g_transfer_lenth - k, BUF_LENGTH_HALF);
283 for (j = 0; j < rcv_len; j++) {
284 *((hi_u16 *)cmp_buf + j) = (hi_u16)i;
285 i++;
286 }
287 memset_s(g_spi_rcv_buf, sizeof(g_spi_rcv_buf), 0x0, sizeof(g_spi_rcv_buf));
288 ret = hi_spi_slave_read(spi_id, g_spi_rcv_buf, rcv_len * 2, 10000); /* 2:doubule the length 10000:ms */
289 if ((memcmp(g_spi_rcv_buf, cmp_buf, rcv_len) != 0) || (ret != HI_ERR_SUCCESS)) {
290 err_times++;
291 print_err_rev_buf_u16((hi_u16 *)g_spi_rcv_buf, (hi_u16 *)cmp_buf, rcv_len);
292 break;
293 }
294 hi_watchdog_feed();
295 k += rcv_len;
296 }
297 } while (while_times < g_test_loop || g_test_loop == 0);
298 test_spi_printf("demo_spi_slave_rev err_rev: %d,while_times:%d, ret:%x", err_times, while_times, ret);
299 return ret;
300 }
301
app_demo_spi_slave_receive_task(hi_void * param)302 hi_void *app_demo_spi_slave_receive_task(hi_void *param)
303 {
304 hi_spi_idx spi_id = *(hi_spi_idx*)param;
305 hi_u32 ret;
306 hi_u32 time_old;
307 hi_u32 time_new;
308 time_old = hi_get_milli_seconds();
309 if (g_data_width < HI_SPI_CFG_DATA_WIDTH_E_9BIT) {
310 ret = app_demo_spi_slave_receive_8bits(spi_id);
311 } else {
312 ret = app_demo_spi_slave_receive_16bits(spi_id);
313 }
314 if (ret != HI_ERR_SUCCESS) {
315 printf("app_demo_spi_slave_receive fail: %x\n", ret);
316 }
317
318 time_new = hi_get_milli_seconds();
319 test_spi_printf("time_old: %d,time_new %d, delt:%d", time_old, time_new, time_new - time_old);
320 app_demo_spi_print_reg(spi_id);
321 ret = hi_spi_deinit(spi_id);
322 if (ret != HI_ERR_SUCCESS) {
323 printf("hi_spi_deinit fail: %x\n", ret);
324 }
325 return HI_NULL;
326 }
327
app_demo_spi_host_write_read_task(hi_void * param)328 hi_void *app_demo_spi_host_write_read_task(hi_void *param)
329 {
330 hi_spi_idx spi_id = *(hi_spi_idx*)param;
331 hi_u32 ret;
332 hi_u32 i;
333 hi_u8 send_buf[g_transfer_lenth];
334 hi_u8 recv_buf[g_transfer_lenth + 1];
335 hi_u32 while_times = 0;
336 hi_u32 err_times = 0;
337 hi_u32 time_old;
338 hi_u32 time_new;
339 for (i = 0; i < g_transfer_lenth; i++) {
340 send_buf[i] = (hi_u8)i;
341 }
342 time_old = hi_get_milli_seconds();
343 do {
344 memset_s(recv_buf, sizeof(recv_buf), 0x0, sizeof(recv_buf));
345 ret = hi_spi_host_writeread(spi_id, send_buf, recv_buf, g_transfer_lenth);
346 if (memcmp(recv_buf, send_buf, g_transfer_lenth) != 0 || ret != HI_ERR_SUCCESS) {
347 err_times++;
348 }
349 while_times++;
350 } while (while_times < g_test_loop || g_test_loop == 0);
351 time_new = hi_get_milli_seconds();
352 test_spi_printf("while_times:%d ,err_times:%d", while_times, err_times);
353 test_spi_printf("time_old: %d,time_new %d, delt:%d", time_old, time_new, time_new - time_old);
354 app_demo_spi_print_reg(spi_id);
355 return HI_NULL;
356 }
357
app_demo_spi_host_send_8bits(hi_spi_idx spi_id)358 hi_u32 app_demo_spi_host_send_8bits(hi_spi_idx spi_id)
359 {
360 hi_u32 i;
361 hi_u32 j;
362 hi_u32 while_times = 0;
363 hi_u32 err_times = 0;
364 hi_u32 ret;
365 if (g_transfer_lenth > BUF_LENGTH) {
366 return HI_ERR_FAILURE;
367 }
368 i = 0;
369 for (j = 0; j < g_transfer_lenth; j++) {
370 g_spi_send_buf[j] = (hi_u8)i;
371 i++;
372 }
373 do {
374 ret = hi_spi_host_write(spi_id, g_spi_send_buf, g_transfer_lenth);
375 hi_udelay(g_delay_us_spi);
376 if (ret != HI_ERR_SUCCESS) {
377 err_times++;
378 break;
379 }
380 while_times++;
381 } while (while_times < g_test_loop || g_test_loop == 0);
382 test_spi_printf("demo_spi_host_send err_send: %d,while_times:%d, ret:%x", err_times, while_times, ret);
383 return ret;
384 }
385
app_demo_spi_host_send_16bits(hi_spi_idx spi_id)386 hi_u32 app_demo_spi_host_send_16bits(hi_spi_idx spi_id)
387 {
388 hi_u32 i;
389 hi_u32 j;
390 hi_u32 while_times = 0;
391 hi_u32 ret = HI_ERR_SUCCESS;
392 hi_u32 index;
393 hi_u32 err_times = 0;
394 hi_u32 send_len;
395 do {
396 i = 0;
397 index = 0;
398 while (index < g_transfer_lenth) {
399 send_len = min(g_transfer_lenth - index, BUF_LENGTH_HALF);
400 for (j = 0; j < send_len; j++) {
401 *((hi_u16 *)g_spi_send_buf + j) = (hi_u16)i;
402 i++;
403 }
404 ret = hi_spi_host_write(spi_id, g_spi_send_buf, send_len * 2); /* 2:doubule the length */
405 hi_udelay(g_delay_us_spi);
406 if (ret != HI_ERR_SUCCESS) {
407 err_times++;
408 print_err_send_buf_u16((hi_u16 *)g_spi_send_buf, send_len);
409 }
410 hi_watchdog_feed();
411 index += send_len;
412 }
413 while_times++;
414 } while (while_times < g_test_loop || g_test_loop == 0);
415 test_spi_printf("demo_spi_slave_send err_send: %d,while_times:%d, ret:%x", err_times, while_times, ret);
416 return ret;
417 }
418 /*
419 * spi host device write data task
420 */
app_demo_spi_host_write_task(hi_void * param)421 hi_void *app_demo_spi_host_write_task(hi_void *param)
422 {
423 hi_spi_idx spi_id = *(hi_spi_idx*)param;
424 hi_u32 ret;
425 hi_u32 time_old;
426 hi_u32 time_new;
427 time_old = hi_get_milli_seconds();
428 if (g_data_width < HI_SPI_CFG_DATA_WIDTH_E_9BIT) {
429 ret = app_demo_spi_host_send_8bits(spi_id);
430 } else {
431 ret = app_demo_spi_host_send_16bits(spi_id);
432 }
433 if (ret != HI_ERR_SUCCESS) {
434 printf("app_demo_spi_host_send fail: %x\n", ret);
435 }
436 time_new = hi_get_milli_seconds();
437 test_spi_printf("time_old: %d,time_new %d, delt:%d", time_old, time_new, time_new - time_old);
438 app_demo_spi_print_reg(spi_id);
439 ret = hi_spi_deinit(spi_id);
440 if (ret != HI_ERR_SUCCESS) {
441 printf("hi_spi_deinit fail: %x\n", ret);
442 return HI_NULL;
443 }
444 return HI_NULL;
445 }
446
app_demo_spi_host_receive_8bits(hi_spi_idx spi_id)447 hi_u32 app_demo_spi_host_receive_8bits(hi_spi_idx spi_id)
448 {
449 hi_u8 cmp_buf[BUF_LENGTH];
450 hi_u32 while_times = 0;
451 hi_u32 i;
452 hi_u32 j;
453 hi_u32 err_times = 0;
454 hi_u32 ret;
455 i = 0;
456 if (g_transfer_lenth > BUF_LENGTH) {
457 return HI_ERR_FAILURE;
458 }
459 for (j = 0; j < g_transfer_lenth; j++) {
460 cmp_buf[j] = (hi_u8)i;
461 i++;
462 }
463 do {
464 while_times++;
465 if (memset_s(g_spi_rcv_buf, sizeof(g_spi_rcv_buf), 0x0, sizeof(g_spi_rcv_buf)) != EOK) {
466 ret = HI_ERR_MEMSET_S;
467 break;
468 }
469 ret = hi_spi_host_read(spi_id, g_spi_rcv_buf, g_transfer_lenth);
470 hi_udelay(g_delay_us_spi);
471 if (memcmp(g_spi_rcv_buf, cmp_buf, g_transfer_lenth) != 0) {
472 err_times++;
473 print_err_rev_buf_u8(g_spi_rcv_buf, cmp_buf, g_transfer_lenth);
474 break;
475 }
476 } while (while_times < g_test_loop || g_test_loop == 0);
477 test_spi_printf("demo_spi_host_rev err_rev: %d,while_times:%d, ret:%x", err_times, while_times, ret);
478 return ret;
479 }
480
app_demo_spi_host_receive_16bits(hi_spi_idx spi_id)481 hi_u32 app_demo_spi_host_receive_16bits(hi_spi_idx spi_id)
482 {
483 hi_u8 cmp_buf[BUF_LENGTH];
484 hi_u32 while_times = 0;
485 hi_u32 err_times = 0;
486 hi_u32 i;
487 hi_u32 j;
488 hi_u32 k;
489 hi_u32 ret = HI_ERR_SUCCESS;
490 hi_u32 recv_len;
491 do {
492 k = 0;
493 while_times++;
494 i = 0;
495 while (k < g_transfer_lenth) {
496 recv_len = min(g_transfer_lenth - k, BUF_LENGTH_HALF);
497 for (j = 0; j < recv_len; j++) {
498 *((hi_u16 *)cmp_buf + j) = (hi_u16)i;
499 i++;
500 }
501 memset_s(g_spi_rcv_buf, sizeof(g_spi_rcv_buf), 0x0, sizeof(g_spi_rcv_buf));
502 ret = hi_spi_host_read(spi_id, g_spi_rcv_buf, recv_len * 2); /* 2:doubule the length */
503 hi_udelay(g_delay_us_spi);
504 if (memcmp(g_spi_rcv_buf, cmp_buf, recv_len * 2) != 0) { /* 2:doubule the length */
505 err_times++;
506 print_err_rev_buf_u16((hi_u16 *)g_spi_rcv_buf, (hi_u16 *)cmp_buf, recv_len);
507 break;
508 }
509 hi_watchdog_feed();
510 k += recv_len;
511 }
512 } while (while_times < g_test_loop || g_test_loop == 0);
513 test_spi_printf("demo_spi_host_rev err_rev: %d,while_times:%d, ret:%x", err_times, while_times, ret);
514 return ret;
515 }
516
517 /*
518 * spi host device read data task
519 */
app_demo_spi_host_read_task(hi_void * param)520 hi_void *app_demo_spi_host_read_task(hi_void *param)
521 {
522 hi_spi_idx spi_id = *(hi_spi_idx*)param;
523 printf("spi_id:%d\n", spi_id);
524 hi_u32 ret;
525 hi_u32 time_old;
526 hi_u32 time_new;
527 time_old = hi_get_milli_seconds();
528 if (g_data_width < HI_SPI_CFG_DATA_WIDTH_E_9BIT) {
529 ret = app_demo_spi_host_receive_8bits(spi_id);
530 } else {
531 ret = app_demo_spi_host_receive_16bits(spi_id);
532 }
533 if (ret != HI_ERR_SUCCESS) {
534 printf("app_demo_spi_host_receive fail: %x\n", ret);
535 }
536 time_new = hi_get_milli_seconds();
537 test_spi_printf("time_old: %d,time_new %d, delt:%d", time_old, time_new, time_new - time_old);
538 app_demo_spi_print_reg(spi_id);
539 ret = hi_spi_deinit(spi_id);
540 if (ret != HI_ERR_SUCCESS) {
541 printf("hi_spi_deinit fail: %x\n", ret);
542 }
543 return HI_NULL;
544 }
545
546 /*
547 * host device write data and slave device read data
548 */
app_demo_spi_test_cmd_mw_sr(const test_spi_para * spi_para)549 hi_void app_demo_spi_test_cmd_mw_sr(const test_spi_para *spi_para)
550 {
551 hi_u32 ret;
552 hi_u32 taskid1;
553 hi_task_attr attr;
554
555 test_spi_printf("app_demo_spi_test_cmd_mw_sr Start");
556 ret = app_demo_spi_init(spi_para->spi_id, &(spi_para->cfg_info), spi_para->slave);
557
558 g_transfer_lenth = spi_para->length;
559 g_spi_id = spi_para->spi_id;
560 if (ret == HI_ERR_SUCCESS) {
561 test_spi_printf("SPI init succ!");
562 } else {
563 test_spi_printf("SPI init fail! %x ", ret);
564 return;
565 }
566 hi_spi_set_loop_back_mode(spi_para->spi_id, spi_para->lb);
567 app_demo_spi_config_gpio(spi_para->spi_id);
568 g_test_loop = spi_para->loop;
569 g_data_width = (hi_spi_cfg_data_width)spi_para->cfg_info.data_width;
570 hi_sleep(1000); /* 1000 */
571 hi_spi_set_irq_mode(spi_para->spi_id, spi_para->irq);
572 hi_spi_set_dma_mode(spi_para->spi_id, spi_para->dma_en);
573 if (spi_para->slave == 0) {
574 attr.task_prio = 5; /* priority 5 */
575 attr.stack_size = 0x2000;
576 attr.task_name = (hi_char *)"spi_host";
577 ret = hi_task_create(&taskid1, &attr, app_demo_spi_host_write_task, (hi_void *)&spi_para->spi_id);
578 } else {
579 attr.task_prio = 5; /* priority 5 */
580 attr.stack_size = 0x2000;
581 attr.task_name = (hi_char *)"r_spi_slave";
582 ret = hi_task_create(&taskid1, &attr, app_demo_spi_slave_receive_task, (hi_void *)&spi_para->spi_id);
583 }
584 test_spi_printf("SPI Test End!");
585 }
586
587 /*
588 * host device read data and slave device write data
589 */
app_demo_spi_test_cmd_mr_sw(const test_spi_para * spi_para)590 hi_void app_demo_spi_test_cmd_mr_sw(const test_spi_para *spi_para)
591 {
592 hi_u32 ret;
593 hi_u32 taskid1;
594 hi_task_attr attr;
595
596 test_spi_printf("app_demo_spi_test_cmd_mr_sw Start");
597 ret = app_demo_spi_init(spi_para->spi_id, &(spi_para->cfg_info), spi_para->slave);
598 app_demo_spi_config_gpio(spi_para->spi_id);
599 g_transfer_lenth = spi_para->length;
600 g_spi_id = spi_para->spi_id;
601 g_data_width = (hi_spi_cfg_data_width)spi_para->cfg_info.data_width;
602 if (ret == HI_ERR_SUCCESS) {
603 test_spi_printf("SPI init succ!");
604 } else {
605 test_spi_printf("SPI init fail! %x ", ret);
606 return;
607 }
608 hi_spi_set_loop_back_mode(spi_para->spi_id, spi_para->lb);
609 g_test_loop = spi_para->loop;
610 hi_sleep(1000); /* 1000 */
611 hi_spi_set_irq_mode(spi_para->spi_id, spi_para->irq);
612 ret = hi_spi_set_dma_mode(spi_para->spi_id, spi_para->dma_en);
613 printf("hi_spi_set_dma_mode :%x\n", ret);
614 if (spi_para->slave == 0) {
615 attr.task_prio = 25; /* priority 25 */
616 attr.stack_size = 0x2000;
617 attr.task_name = (hi_char *)"spi_host";
618 ret = hi_task_create(&taskid1, &attr, app_demo_spi_host_read_task, (hi_void *)&spi_para->spi_id);
619 } else {
620 attr.task_prio = 25; /* priority 25 */
621 attr.stack_size = 0x2000;
622 attr.task_name = (hi_char *)"w_spi_slave";
623 ret = hi_task_create(&taskid1, &attr, app_demo_spi_slave_send_task, (hi_void *)&spi_para->spi_id);
624 }
625 test_spi_printf("SPI Test End!");
626 }
627
app_demo_spi_single_loopback(hi_spi_idx spi_id,hi_u8 data_width)628 hi_u32 app_demo_spi_single_loopback(hi_spi_idx spi_id, hi_u8 data_width)
629 {
630 hi_u32 ret;
631 hi_u32 i;
632 hi_u8 send_buf[512] = { 0 }; /* 512 */
633 hi_u8 recv_buf[512] = { 0 }; /* 512 */
634 hi_u32 test_length = 243; /* 243: test length */
635 hi_u32 while_times = 0;
636 do {
637 if (data_width < HI_SPI_CFG_DATA_WIDTH_E_8BIT) {
638 test_length = (0x1 << data_width) - 1;
639 }
640 while_times++;
641 printf("while_times:%d \n", while_times);
642 memset_s(recv_buf, sizeof(recv_buf), 0x0, sizeof(recv_buf));
643 if (data_width >= HI_SPI_CFG_DATA_WIDTH_E_9BIT) {
644 for (i = 0; i < 256; i++) { /* loop 256 times */
645 *((hi_u16 *)send_buf + i) = (hi_u16)i;
646 }
647 ret = hi_spi_host_writeread(spi_id, (hi_pvoid)send_buf, (hi_pvoid)recv_buf, test_length * 2); /* 2 */
648 if (ret != HI_ERR_SUCCESS) {
649 return ret;
650 }
651 if (memcmp(recv_buf, send_buf, test_length * 2) != 0) { /* 2 double buf length */
652 print_err_rev_buf_u16((hi_u16 *)send_buf, (hi_u16 *)recv_buf, test_length);
653 return HI_ERR_FAILURE;
654 }
655 continue;
656 }
657 for (i = 0; i < 512; i++) { /* 512 */
658 send_buf[i] = (hi_u8)i;
659 }
660 ret = hi_spi_host_writeread(spi_id, (hi_pvoid)send_buf, (hi_pvoid)recv_buf, test_length);
661 if (ret != HI_ERR_SUCCESS) {
662 return ret;
663 }
664 if (memcmp(recv_buf, send_buf, test_length) != 0) {
665 for (i = 0; i < test_length; i++) {
666 test_spi_printf("b[%d]i[%d]s[%d]r[%d]", data_width + 1, i, send_buf[i], recv_buf[i]);
667 }
668 return HI_ERR_FAILURE;
669 }
670 } while (while_times <= g_lb_loop);
671 return ret;
672 }
673
app_demo_spi_para_test(hi_spi_cfg_basic_info * spi_para)674 hi_u32 app_demo_spi_para_test(hi_spi_cfg_basic_info *spi_para)
675 {
676 hi_u32 ret;
677 spi_para->data_width = 2; /* data width 2 */
678 ret = hi_spi_set_basic_info(g_spi_id, spi_para);
679 if (ret != HI_ERR_SPI_PARAMETER_WRONG) {
680 return HI_ERR_FAILURE;
681 }
682 spi_para->data_width = HI_SPI_CFG_DATA_WIDTH_E_8BIT;
683 spi_para->fram_mode = 3; /* data protocol 3 */
684 ret = hi_spi_set_basic_info(g_spi_id, spi_para);
685 if (ret != HI_ERR_SPI_PARAMETER_WRONG) {
686 return HI_ERR_FAILURE;
687 }
688 spi_para->fram_mode = HI_SPI_CFG_FRAM_MODE_MOTOROLA;
689 spi_para->freq = 80000000; /* Clock rate 13 80000000 */
690 ret = hi_spi_set_basic_info(g_spi_id, spi_para);
691 if (ret != HI_ERR_SPI_PARAMETER_WRONG) {
692 return HI_ERR_FAILURE;
693 }
694 spi_para->freq = 1000; /* Clock rate 256 1000 */
695 ret = hi_spi_set_basic_info(g_spi_id, spi_para);
696 if (ret != HI_ERR_SPI_PARAMETER_WRONG) {
697 return HI_ERR_FAILURE;
698 }
699 spi_para->freq = 2000000; /* Clock rate 24 2000000 */
700 return HI_ERR_SUCCESS;
701 }
702
app_demo_spi_test_case_part1(hi_spi_cfg_basic_info * spi_para,hi_u8 test_case)703 hi_void app_demo_spi_test_case_part1(hi_spi_cfg_basic_info *spi_para, hi_u8 test_case)
704 {
705 switch (test_case) {
706 case TEST_CASE_POL0_PHA0:
707 spi_para->cpol = HI_SPI_CFG_CLOCK_CPOL_0;
708 spi_para->cpha = HI_SPI_CFG_CLOCK_CPHA_0;
709 break;
710 case TEST_CASE_POL0_PHA1:
711 spi_para->cpol = HI_SPI_CFG_CLOCK_CPOL_0;
712 spi_para->cpha = HI_SPI_CFG_CLOCK_CPHA_1;
713 break;
714 case TEST_CASE_POL1_PHA0:
715 spi_para->cpol = HI_SPI_CFG_CLOCK_CPOL_1;
716 spi_para->cpha = HI_SPI_CFG_CLOCK_CPHA_0;
717 break;
718 case TEST_CASE_POL1_PHA1:
719 spi_para->cpol = HI_SPI_CFG_CLOCK_CPOL_1;
720 spi_para->cpha = HI_SPI_CFG_CLOCK_CPHA_1;
721 break;
722 case TEST_CASE_MOTOROLA:
723 spi_para->fram_mode = HI_SPI_CFG_FRAM_MODE_MOTOROLA;
724 break;
725 case TEST_CASE_TI:
726 spi_para->fram_mode = HI_SPI_CFG_FRAM_MODE_TI;
727 break;
728 /* Microware does not support self-loopback tests. Two devices must be connected for tests. */
729 case TEST_CASE_BIT4:
730 spi_para->data_width = HI_SPI_CFG_DATA_WIDTH_E_4BIT;
731 break;
732 case TEST_CASE_BIT7:
733 spi_para->data_width = HI_SPI_CFG_DATA_WIDTH_E_7BIT;
734 break;
735 case TEST_CASE_BIT8:
736 spi_para->data_width = HI_SPI_CFG_DATA_WIDTH_E_8BIT;
737 break;
738 case TEST_CASE_BIT9:
739 spi_para->data_width = HI_SPI_CFG_DATA_WIDTH_E_9BIT;
740 break;
741 case TEST_CASE_BIT15:
742 spi_para->data_width = HI_SPI_CFG_DATA_WIDTH_E_15BIT;
743 break;
744 case TEST_CASE_BIT16:
745 spi_para->data_width = HI_SPI_CFG_DATA_WIDTH_E_16BIT;
746 break;
747 default:
748 break;
749 }
750 }
751
app_demo_spi_test_case_part2(hi_spi_cfg_basic_info * spi_para,hi_u8 test_case,hi_u8 * flag)752 hi_u32 app_demo_spi_test_case_part2(hi_spi_cfg_basic_info *spi_para, hi_u8 test_case, hi_u8 *flag)
753 {
754 switch (test_case) {
755 case TEST_CASE_CLK_MIN:
756 spi_para->freq = 20000000; /* Clock rate 4 20000000 */
757 break;
758 case TEST_CASE_CLK_16:
759 spi_para->freq = 5000000; /* Clock rate 16 5000000 */
760 break;
761 case TEST_CASE_CLK_50:
762 spi_para->freq = 1600000; /* Clock rate 50 1600000 */
763 break;
764 case TEST_CASE_CLK_100:
765 spi_para->freq = 800000; /* Clock rate 100 800000 */
766 break;
767 case TEST_CASE_CLK_200:
768 spi_para->freq = 400000; /* Clock rate 200 400000 */
769 break;
770 case TEST_CASE_PARAMETER_WRONG:
771 *flag = 1;
772 return app_demo_spi_para_test(spi_para);
773 default:
774 break;
775 }
776 return HI_ERR_SUCCESS;
777 }
778
app_demo_spi_test_case(hi_u8 test_case)779 hi_u32 app_demo_spi_test_case(hi_u8 test_case)
780 {
781 hi_u32 ret;
782 hi_u8 flag = 0;
783 hi_spi_cfg_basic_info spi_para = {
784 .data_width = HI_SPI_CFG_DATA_WIDTH_E_8BIT,
785 .fram_mode = HI_SPI_CFG_FRAM_MODE_MOTOROLA,
786 .cpol = HI_SPI_CFG_CLOCK_CPOL_0,
787 .cpha = HI_SPI_CFG_CLOCK_CPHA_0,
788 .endian = HI_SPI_CFG_ENDIAN_LITTLE,
789 .pad = 0,
790 .freq = 2000000, /* Clock rate 24 2000000 */
791 };
792 app_demo_spi_test_case_part1(&spi_para, test_case);
793 ret = app_demo_spi_test_case_part2(&spi_para, test_case, &flag);
794 if (flag) {
795 return ret;
796 }
797 ret = hi_spi_set_basic_info(g_spi_id, &spi_para);
798 if (ret != HI_ERR_SUCCESS) {
799 return ret;
800 }
801 return app_demo_spi_single_loopback(g_spi_id, spi_para.data_width);
802 }
803
804 /*
805 * Test SPI unit parameters and loop back mode
806 */
app_demo_spi_test(hi_spi_idx spi_id,hi_u32 irq_en,hi_u32 test_case,hi_u32 loop)807 hi_void app_demo_spi_test(hi_spi_idx spi_id, hi_u32 irq_en, hi_u32 test_case, hi_u32 loop)
808 {
809 test_spi_printf("SPI%d TEST START", spi_id);
810 hi_spi_cfg_basic_info spi_cfg_basic_info;
811 spi_cfg_basic_info.cpha = 1;
812 spi_cfg_basic_info.cpol = 1;
813 spi_cfg_basic_info.data_width = HI_SPI_CFG_DATA_WIDTH_E_7BIT;
814 spi_cfg_basic_info.endian = 0;
815 spi_cfg_basic_info.fram_mode = 0;
816 spi_cfg_basic_info.freq = 2000000; /* set frequency 2000000 */
817 app_demo_spi_init(spi_id, &spi_cfg_basic_info, HI_FALSE);
818 hi_spi_set_loop_back_mode(spi_id, HI_TRUE);
819 hi_spi_set_irq_mode(spi_id, (hi_bool)irq_en);
820 g_spi_id = spi_id;
821 g_lb_loop = loop;
822 if (test_case == TEST_CASE_ALL) {
823 /* The last three test case need connect Peripherals */
824 for (int i = TEST_CASE_POL0_PHA0; i < TEST_CASE_SLAVE; i++) {
825 hi_u32 ret = app_demo_spi_test_case((hi_u8)i);
826 test_spi_printf("===spi[%d]====TEST_CASE %d %s!=====", spi_id, i,
827 ret == HI_ERR_SUCCESS ? "SUCCESS!" : "FAILURE!");
828 }
829 } else {
830 if (test_case >= TEST_CASE_MAX) {
831 test_spi_printf("INVALID TEST CASE!");
832 return;
833 }
834 hi_u32 ret = app_demo_spi_test_case((hi_u8)test_case);
835 test_spi_printf("===spi[%d]====TEST_CASE %d %s!=====", spi_id, test_case,
836 ret == HI_ERR_SUCCESS ? "SUCCESS!" : "FAILURE!");
837 }
838 app_demo_spi_print_reg(g_spi_id);
839 test_spi_printf("SPI%d TEST END", spi_id);
840 }
841
842 /*
843 * The host device sets the SPI unit and read data
844 */
app_demo_spi_cmd_host_read(hi_spi_idx spi_id,hi_u32 length,hi_u32 loop)845 hi_void app_demo_spi_cmd_host_read(hi_spi_idx spi_id, hi_u32 length, hi_u32 loop)
846 {
847 test_spi_para spi_para;
848 spi_para.spi_id = spi_id;
849 spi_para.irq = HI_FALSE;
850 spi_para.length = length;
851 spi_para.loop = loop;
852 spi_para.cfg_info.data_width = HI_SPI_CFG_DATA_WIDTH_E_8BIT;
853 spi_para.cfg_info.cpha = HI_SPI_CFG_CLOCK_CPHA_0;
854 spi_para.cfg_info.cpol = HI_SPI_CFG_CLOCK_CPOL_0;
855 spi_para.cfg_info.fram_mode = HI_SPI_CFG_FRAM_MODE_MOTOROLA;
856 spi_para.cfg_info.endian = HI_SPI_CFG_ENDIAN_LITTLE;
857 spi_para.slave = HI_FALSE;
858 spi_para.lb = HI_FALSE;
859 spi_para.dma_en = HI_FALSE;
860 g_delay_us_spi = 200; /* 200us */
861 spi_para.cfg_info.freq = 8000000; /* defaul freq 8000000 Hz */
862 app_demo_spi_print_test_para(&spi_para);
863 app_demo_spi_test_cmd_mr_sw(&spi_para);
864 }
865
866 /*
867 * The slave device sets the SPI unit and write data
868 */
app_demo_spi_cmd_slave_write(hi_spi_idx spi_id,hi_u32 length,hi_u32 loop)869 hi_void app_demo_spi_cmd_slave_write(hi_spi_idx spi_id, hi_u32 length, hi_u32 loop)
870 {
871 test_spi_para spi_para;
872 spi_para.spi_id = spi_id;
873 spi_para.irq = HI_FALSE;
874 spi_para.length = length;
875 spi_para.loop = loop;
876 spi_para.cfg_info.data_width = HI_SPI_CFG_DATA_WIDTH_E_8BIT;
877 spi_para.cfg_info.cpha = HI_SPI_CFG_CLOCK_CPHA_0;
878 spi_para.cfg_info.cpol = HI_SPI_CFG_CLOCK_CPOL_0;
879 spi_para.cfg_info.fram_mode = HI_SPI_CFG_FRAM_MODE_MOTOROLA;
880 spi_para.cfg_info.endian = HI_SPI_CFG_ENDIAN_LITTLE;
881 spi_para.slave = HI_TRUE;
882 spi_para.lb = HI_FALSE;
883 spi_para.dma_en = HI_TRUE;
884 g_delay_us_spi = 0;
885 spi_para.cfg_info.freq = 8000000; /* defaul freq 8000000 Hz */
886 app_demo_spi_print_test_para(&spi_para);
887 app_demo_spi_test_cmd_mr_sw(&spi_para);
888 }
889
890 /*
891 * The host device sets the SPI unit and write data
892 */
app_demo_spi_cmd_host_write(hi_spi_idx spi_id,hi_u32 length,hi_u32 loop)893 hi_void app_demo_spi_cmd_host_write(hi_spi_idx spi_id, hi_u32 length, hi_u32 loop)
894 {
895 test_spi_para spi_para;
896 spi_para.spi_id = spi_id;
897 spi_para.irq = HI_FALSE;
898 spi_para.length = length;
899 spi_para.loop = loop;
900 spi_para.cfg_info.data_width = HI_SPI_CFG_DATA_WIDTH_E_8BIT;
901 spi_para.cfg_info.cpha = HI_SPI_CFG_CLOCK_CPHA_0;
902 spi_para.cfg_info.cpol = HI_SPI_CFG_CLOCK_CPOL_0;
903 spi_para.cfg_info.fram_mode = HI_SPI_CFG_FRAM_MODE_MOTOROLA;
904 spi_para.cfg_info.endian = HI_SPI_CFG_ENDIAN_LITTLE;
905 spi_para.slave = HI_FALSE;
906 spi_para.lb = HI_FALSE;
907 spi_para.dma_en = HI_FALSE;
908 g_delay_us_spi = 100; /* 100 us */
909 spi_para.cfg_info.freq = 8000000; /* defaul freq 8000000 Hz */
910 app_demo_spi_print_test_para(&spi_para);
911 app_demo_spi_test_cmd_mw_sr(&spi_para);
912 }
913
914 /*
915 * The slave device sets the SPI unit and read data
916 */
app_demo_spi_cmd_slave_read(hi_spi_idx spi_id,hi_u32 length,hi_u32 loop)917 hi_void app_demo_spi_cmd_slave_read(hi_spi_idx spi_id, hi_u32 length, hi_u32 loop)
918 {
919 test_spi_para spi_para;
920 spi_para.spi_id = spi_id;
921 spi_para.irq = HI_FALSE;
922 spi_para.length = length;
923 spi_para.loop = loop;
924 spi_para.cfg_info.data_width = HI_SPI_CFG_DATA_WIDTH_E_8BIT;
925 spi_para.cfg_info.cpha = HI_SPI_CFG_CLOCK_CPHA_0;
926 spi_para.cfg_info.cpol = HI_SPI_CFG_CLOCK_CPOL_0;
927 spi_para.cfg_info.fram_mode = HI_SPI_CFG_FRAM_MODE_MOTOROLA;
928 spi_para.cfg_info.endian = HI_SPI_CFG_ENDIAN_LITTLE;
929 spi_para.slave = HI_TRUE;
930 spi_para.lb = HI_FALSE;
931 spi_para.dma_en = HI_TRUE;
932 g_delay_us_spi = 0;
933 spi_para.cfg_info.freq = 8000000; /* defaul freq 8000000 Hz */
934 app_demo_spi_print_test_para(&spi_para);
935 app_demo_spi_test_cmd_mw_sr(&spi_para);
936 }
937
938