GCC: (Heterogeneous Compiler&Codesign V100R003C00SPC210B006) 7.3.0 GCC: (Heterogeneous Compiler&Codesign V100R003C00SPC210B006) 7.3.0 GCC: (Heterogeneous Compiler&Codesign V100R003C00SPC210B006) 7.3.0 GCC: (Heterogeneous Compiler&Codesign V100R003C00SPC210B006) 7.3.0 GCC: (Heterogeneous Compiler&Codesign V100R003C00SPC210B006) 7.3.0 GCC: (Heterogeneous Compiler&Codesign V100R003C00SPC210B006) 7.3.0 GCC: (Heterogeneous Compiler&Codesign V100R003C00SPC210B006) 7.3.0 GCC: (Heterogeneous Compiler&Codesign V100R003C00SPC210B006) 7.3.0 GCC: (Heterogeneous Compiler&Codesign V100R003C00SPC210B006) 7.3.0 GCC: (Heterogeneous Compiler&Codesign V100R003C00SPC210B006) 7.3.0 GCC: (Heterogeneous Compiler&Codesign V100R003C00SPC210B006) 7.3.0 GCC: (Heterogeneous Compiler&Codesign V100R003C00SPC210B006) 7.3.0 GCC: (Heterogeneous Compiler&Codesign V100R003C00SPC210B006) 7.3.0 GCC: (Heterogeneous Compiler&Codesign V100R003C00SPC210B006) 7.3.0 GCC: (Heterogeneous Compiler&Codesign V100R003C00SPC210B006) 7.3.0
debug.c .L1 .L3 err.c MASK .L3 1 .L6 1 .L5 1 .L2 1 .L7 1 .L1 2 .L2 efuse_rom.c .LC0 .LC1 .LC2 .L4 1 .L1 1 .L13 .L17 .L18 .L5 .L4 .L7 .L8 .L9 .L11 .L12 gpio.c flash_chip_tbl.c .LC3 .LC4 .LC5 .LC6 .LC7 flash_hw_process.c .L6 .L10 .L15 .L20 .L22 .L26 .L25 .LANCHOR0 .L32 .L34 .L37 .L40 .L39 .L46 .L52 .L67 .L65 .L58 .L61 .L62 .L63 .L64 .L60 .L79 .L78 .L82 .L80 .L84 flash_soft_process.c .L16 .L19 .L24 .L21 .L30 .L28 .L31 .L27 .L35 .L33 .L42 .L50 .L49 .L45 .L47 .L41 .L44 .L48 .L54 .L55 .L53 .L59 .L77 serial_dw.c CSWTCH.46 .L14 .LANCHOR1 .LANCHOR2 .L23 .L29 .L36 .L43 .L56 .L51 .L68 .L69 .L70 .L71 .L72 .L73 .L76 .L81 .L85 .L87 .L86 .L88 .L89 .L91 .L92 .LANCHOR3 .L97 .L99 .L98 .LANCHOR4 .L105 .L106 .L107 .L108 .L120 .L112 .L110 .L124 .L122 systick.c watchdog.c crc16.c .L2 2 .L4 2 malloc.c .L2 3 .L4 3 .L1 3 .L2 4 .L4 4 .L1 4 .L3 5 .L2 5 .L2 6 .L4 5 .L1 6 .L38 .L9 1 .L8 1 .Ltable .Ltable_misaligned .Ltiny .Lmisaligned .Lwordify .Lwordified .Laligned time.c brain_pool_p256r1.c uart_auth.c .L3 3 .L1 5 .L3 6 .L6 2 .L5 2 .L7 2 .L2 7 .L1 7 .L2 8 .L4 6 .L1 8 .L2 9 .L4 7 .L1 9 .L3 10 .L6 3 .L5 3 .L2 10 .L7 3 .L2 11 .L4 8 .L1 11 .L2 12 .L4 9 .L1 12 .L74 hi_watchdog_enable set_tx_fifo_line mdelay spi_flash_read_ram_align g_spi_opt_chip_erase1 g_uart_print_err set_flow_ctr g_flash_drv_option g_spi_opt_32kblk_erase g_utm_offset spi_flash_get_size hi_register_malloc uart_frame_data_rx spif_map_chipsize spif_reg_erase spi_search_ids crc16_ccitt serial_put_buf memcpy g_uart_mute g_encrypt_flag set_databit_stopbit_parity flash_write_prv uart_wait_usr_interrupt efuse_usr_read serial_set_mute g_crc16_tab g_spi_opt_fast_quad_eb_out_read g_flash_default_info_tbl flash_erase_prv uart_process g_ecc_brain_pool_p256r1_p g_spi_opt_standard_read hi_io_set_func g_spi_opt_fast_quad_out_read flash_write_with_check spi_flash_write_ram_align boot_put_errno g_spi_opt_fast_read uart_frame_head_rx g_spi_opt_chip_erase2 g_ecc_brain_pool_p256r1_gx uart_frame_rx hi_get_malloc_struct spif_dma_transfer spif_dma_read reset_uart_module g_spi_opt_fast_dual_out_read set_uart_param memcpy_s serial_tstc memset_s g_uart_brd_cfg set_start_status uart_init g_spi_opt_page_program_write sfc_check_para g_ecc_brain_pool_p256r1_gy spif_dma_write boot_msg4 serial_putc g_spi_opt_64kblk_erase boot_puthex udelay dw_getc boot_msg0 memcmp rom_boot_free spi_flash_read_chip_id verify_error memset spi_flash_read_reg set_fifo_line systick_enable serial_cancel_mute rom_boot_malloc_init rom_boot_malloc_init_check spif_wait_ready serial_init g_spi_opt_sector_erase g_ecc_brain_pool_p256r1_n set_rts_fifo_line serial_puts serial_puthex set_rx_fifo_line g_ecc_brain_pool_p256r1_a dw_tstc g_uart_param uart_usr_interrupt_verify systick_get boot_msg2 g_uart_int_type flash_read_prv g_uart_baseaddr uart_deinit hi_watchdog_disable hi_crc16 check_uart_mute serial_getc spif_write_enable g_ecc_brain_pool_p256r1_b hi_watchdog_feed hi_io_set_pull spif_reg_erase_one_block spif_config uart_ack g_uart_ctx rom_boot_malloc dw_putc serial_getc_timeout spif_read_ids spif_wait_config_start boot_mem_fresh spi_config_op_attribute boot_msg1 spi_flash_write_reg change_uart set_baudrate spi_flash_basic_info_probe g_brain_pool_p256r1_verify
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