1 /* 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 #ifndef __HI3861_PLATFORM_ROM_H 16 #define __HI3861_PLATFORM_ROM_H 17 18 #include <hi_types_base.h> 19 #include <hi3861.h> 20 21 HI_EXTERN hi_u32 g_cfg_apb_clock; 22 HI_EXTERN hi_u32 g_cfg_arm_clock; 23 HI_EXTERN hi_u32 g_cfg_uart_clock; 24 25 #define HI_XTAL_CLOCK_BASE 24 26 #define HI_XTAL_CLOCK (HI_XTAL_CLOCK_BASE * 1000000) 27 #define HI_XTAL_CYCLE_PER_MS (HI_XTAL_CLOCK_BASE * 1000) 28 #define CLK32K_DELAY_US 63 /* Wait for 1 / 32K seconds. Reserve 2 / 32K seconds. */ 29 30 #ifdef HI_BOARD_FPGA 31 /* #error */ 32 #define CONFIG_CPU_CLOCK 53000000 33 #define CONFIG_UART_CLOCK 160000000 34 #else 35 #define CONFIG_CPU_CLOCK 160000000 36 #define CONFIG_UART_CLOCK 80000000 37 #endif 38 #define CONFIG_WDT_CLOCK 80000000 39 40 #define HI_FLASH_BASE 0x00400000 41 #define HI_FLASH_SIZE 0x00200000 42 #define HI_SFC_REG_BASE 0x40800000 43 44 #define HI_SYSCTRL_REG_BASE 0x40030000 45 #define HI_WDG_REG_BASE 0x40000000 46 #define HI_TIMER_REG_BASE 0x40032000 47 #define HI_GPIO_REG_BASE 0x50006000 48 #define HI_IOCFG_REG_BASE 0x5000A000 49 #define HI_BUCK_REG_BASE 0x40034000 50 #define HI_SSP0_REG_BASE 0x40058000 51 #define HI_I2C0_REG_BASE 0x40018000 52 #define HI_I2C1_REG_BASE 0x40019000 53 #define HI_SPACC_REG_BASE 0x40038000 54 #define HI_RSA_REG_BASE 0x40038c00 55 #define HI_EFUSE_REG_BASE 0x40078000 56 #define HI_RNG_REG_BASE 0x40038f00 57 #define HI_LED_REG_BASE 0x40039000 58 #define HI_TIMECNT_REG_BASE 0x4003A000 59 #define HI_CRG_REG_BASE 0x4003B000 60 #define HI_UART0_REG_BASE 0x40008000 61 #define HI_UART1_REG_BASE 0x40009000 62 #define HI_UART2_REG_BASE 0x4000a000 63 64 #define HI_TSENSOR_REG_BASE 0x4003D100 65 #define HI_PWM_REG_BASE 0x40040000 66 #define HI_OSC_REG_BASE 0x4003D300 67 #define HI_TIMECNT1_REG_BASE 0x4003D500 68 #define HI_SSP1_REG_BASE 0x40059000 69 #define HI_HPM_REG_BASE 0x4003F000 70 #define HI_AFE_REG_BASE 0x40040000 71 #define HI_MMU_REG_BASE 0x40041000 72 73 #define W_CTL_BASE_ADDR 0x40028000 74 #define W_CTL_MAC_WDT_RST_SEL_REG (W_CTL_BASE_ADDR + 0x34) 75 #define W_CTL_PHY_WDT_RST_SEL_REG (W_CTL_BASE_ADDR + 0x38) 76 #define W_CTL_WDT_RST_SEL_REG (W_CTL_BASE_ADDR + 0x3C) 77 #define W_CTL_UART_MAC80M_CLKEN_REG (W_CTL_BASE_ADDR + 0x40) 78 #define W_CTL_WLPHY_CLKEN_CLKEN_REG (W_CTL_BASE_ADDR + 0x4C) 79 #define W_CTL_CPU_MAC_CLK_DIV_REG (W_CTL_BASE_ADDR + 0x70) 80 #define W_CTL_UART01_CKDIV_OFFSET (W_CTL_BASE_ADDR + 0x74) 81 #define W_CTL_WLPHY_CLK_DIV_0_REG (W_CTL_BASE_ADDR + 0x78) 82 #define W_CTL_WLPHY_CLK_DIV_1_REG (W_CTL_BASE_ADDR + 0x7C) 83 #define W_CTL_WLPHY_CLK_DIV_2_REG (W_CTL_BASE_ADDR + 0x80) 84 #define W_CTL_TSENSOR_DIV_REG (W_CTL_BASE_ADDR + 0x88) 85 #define W_CTL_UART2_CKDIV_OFFSET (W_CTL_BASE_ADDR + 0x90) 86 #define W_CTL_W_TCXO_SEL_REG (W_CTL_BASE_ADDR + 0x0118) 87 #define W_CTL_CLKMUX_STS_DIV_STS_REG (W_CTL_BASE_ADDR + 0x0130) 88 #define W_CTL_TSENSOR_CTRL_REG (W_CTL_BASE_ADDR + 0x0504) 89 90 91 #define GLB_CTL_RB_BASE_ADDR 0x50000000 92 #define CLDO_CTL_RB_BASE_ADDR 0x40010000 93 #define CLDO_CTL_GEN_REG0 (CLDO_CTL_RB_BASE_ADDR + 0x10) /* used for romboot */ 94 #define CLDO_CTL_GEN_REG1 (CLDO_CTL_RB_BASE_ADDR + 0x14) /* used for romboot */ 95 #define CLDO_CTL_GEN_REG2 (CLDO_CTL_RB_BASE_ADDR + 0x18) /* used for romboot */ 96 #define CLDO_CTL_GEN_REG3 (CLDO_CTL_RB_BASE_ADDR + 0x1C) /* used for romboot */ 97 #define CLDO_CTL_SOFT_RESET_REG (CLDO_CTL_RB_BASE_ADDR + 0x20) 98 #define CLDO_CTL_WDG_RST_SEL_REG (CLDO_CTL_RB_BASE_ADDR + 0x28) 99 #define CLDO_CTL_CLKEN_REG (CLDO_CTL_RB_BASE_ADDR + 0x30) 100 #define CLDO_CTL_CLKEN1_REG (CLDO_CTL_RB_BASE_ADDR + 0x34) 101 #define CLDO_CTL_CLK_SEL_REG (CLDO_CTL_RB_BASE_ADDR + 0x38) 102 #define CLDO_CTL_CLKEN2_REG (CLDO_CTL_RB_BASE_ADDR + 0x48) 103 #define CLDO_CTL_WDG_RST_SEL1_REG (CLDO_CTL_RB_BASE_ADDR + 0x4C) 104 #define CLDO_CTL_CLKMUX_STS_REG (CLDO_CTL_RB_BASE_ADDR + 0x64) 105 #define CLDO_CTL_CLK_DIV1_REG (CLDO_CTL_RB_BASE_ADDR + 0x78) 106 #define CLDO_CTL_PKT_CPU_MEM_SEL (CLDO_CTL_RB_BASE_ADDR + 0x100) 107 108 /*************************Timer**********************/ 109 #define HI_TIMER_CLOCK_BASE 24 /* 24Mhz timer */ 110 #define TIMER_BASE_ADDR 0x40050000 111 #define TIMER_0_BASE_ADDR (TIMER_BASE_ADDR + 0x00) 112 #define TIMER_1_BASE_ADDR (TIMER_BASE_ADDR + 0x14) 113 #define TIMER_2_BASE_ADDR (TIMER_BASE_ADDR + 0x28) 114 #define TIMER_3_BASE_ADDR (TIMER_BASE_ADDR + 0x3C) 115 116 #define TIMER_LOAD_COUNT 0x00 117 #define TIMER_LOAD_COUNT_L 0x00 118 #define TIMER_LOAD_COUNT_H 0x02 119 #define TIMER_CURRENT_VALUE 0x04 120 #define TIMER_CONTROL_REG 0x08 121 #define TIMER_EOI 0x0C 122 #define TIMER_INT_STATUS 0x10 123 124 #define TIMER_CTL_CFG_DISABLE 0x0 125 #define TIMER_CTL_CFG_FREERUN 0x01 126 #define TIMER_CTL_CFG_USERDEF 0x03 127 /*************************RTC**********************/ 128 #define HI_RTC_CLOCK_BASE 32 /* 32kHZ */ 129 #define RTC_TIMER_BASE_ADDR 0x50007000 130 #define RTC_TIMER_0_BASE_ADDR (RTC_TIMER_BASE_ADDR + 0x00) 131 #define RTC_TIMER_1_BASE_ADDR (RTC_TIMER_BASE_ADDR + 0x14) 132 #define RTC_TIMER_2_BASE_ADDR (RTC_TIMER_BASE_ADDR + 0x28) 133 #define RTC_TIMER_3_BASE_ADDR (RTC_TIMER_BASE_ADDR + 0x3C) 134 /*****************************************************/ 135 #define CACHE_ALIGNED_SIZE 32 136 137 138 #define GLB_CTL_BASE 0x50000000 139 #define GLB_CTL_SYS_CTL_ID_REG (GLB_CTL_BASE + 0x0) 140 #define GLB_CTL_GP_REG0_REG (GLB_CTL_BASE + 0x10) 141 #define GLB_CTL_GP_REG1_REG (GLB_CTL_BASE + 0x14) 142 #define GLB_CTL_GP_REG2_REG (GLB_CTL_BASE + 0x18) 143 #define GLB_CTL_GP_REG3_REG (GLB_CTL_BASE + 0x1C) 144 #define GLB_CTL_AON_SOFT_RST_W_REG (GLB_CTL_BASE + 0x20) 145 #define GLB_CTL_SOFT_RST_WCPU_REG (GLB_CTL_BASE + 0x24) 146 #define GLB_CTL_SOFT_GLB_RST_REG (GLB_CTL_BASE + 0x28) 147 #define GLB_CTL_GLB_WDT_RST_SEL_REG (GLB_CTL_BASE + 0x30) 148 #define GLB_CTL_WDT_RST_SEL_REG (GLB_CTL_BASE + 0x34) 149 #define GLB_CTL_AON_CKEN_REG (GLB_CTL_BASE + 0x40) 150 #define GLB_CTL_GLB_AON_32K_CLKEN_REG (GLB_CTL_BASE + 0x50) 151 #define GLB_CTL_USB_RST_STS_REG (GLB_CTL_BASE + 0x60) 152 #define GLB_CTL_A32K_DIV_REG (GLB_CTL_BASE + 0x70) 153 #define GLB_CTL_TCXO_DIV_REG (GLB_CTL_BASE + 0x74) /* 24M/40M div reg */ 154 #define GLB_CTL_AON_PERP_CLKSEL_W_REG (GLB_CTL_BASE + 0x90) 155 #define GLB_CTL_RC_32K_TCXO_SEL_REG (GLB_CTL_BASE + 0x94) 156 #define GLB_CTL_AON_32K_SEL_REG (GLB_CTL_BASE + 0x98) 157 #define GLB_CTL_USB_BUS_CLK_SEL_REG (GLB_CTL_BASE + 0x9C) 158 #define GLB_CTL_SYS_TICK_CFG_REG (GLB_CTL_BASE + 0xC0) /* systick */ 159 #define GLB_CTL_SYS_TICK_VALUE_0_REG (GLB_CTL_BASE + 0xD0) 160 #define GLB_CTL_SYS_TICK_VALUE_1_REG (GLB_CTL_BASE + 0xD4) 161 #define GLB_CTL_SYS_TICK_VALUE_2_REG (GLB_CTL_BASE + 0xD8) 162 #define GLB_CTL_SYS_TICK_VALUE_3_REG (GLB_CTL_BASE + 0xDC) 163 #define GLB_CTL_CLKMUX_STS_REG (GLB_CTL_BASE + 0x110) 164 #define GLB_CTL_DEBUG_CLKEN_REG (GLB_CTL_BASE + 0x170) 165 #define GLB_CTL_SOFT_INT_EN_REG (GLB_CTL_BASE + 0x280) 166 #define GLB_CTL_SOFT_INT_SET_REG (GLB_CTL_BASE + 0x284) 167 #define GLB_CTL_SOFT_INT_CLR_REG (GLB_CTL_BASE + 0x288) 168 #define GLB_CTL_SOFT_INT_STS_REG (GLB_CTL_BASE + 0x28C) 169 #define GLB_CTL_INT_SEL_REG (GLB_CTL_BASE + 0x290) 170 #define GLB_CTL_PAD_IO_SDIO_SR_CFG_REG (GLB_CTL_BASE + 0x2FC) 171 #define GLB_CTL_PAD_SDIO_CFG0_REG (GLB_CTL_BASE + 0x300) 172 #define GLB_CTL_PAD_SDIO_CFG1_REG (GLB_CTL_BASE + 0x304) 173 #define GLB_CTL_PAD_IO_SYSLDO_CFG0_REG (GLB_CTL_BASE + 0x310) 174 #define GLB_CTL_PAD_IO_SYSLDO_CFG1_REG (GLB_CTL_BASE + 0x314) 175 #define GLB_CTL_PAD_IO_SYSLDO_CFG2_REG (GLB_CTL_BASE + 0x31C) 176 #define GLB_CTL_PAD_MAN_CFG_0_REG (GLB_CTL_BASE + 0x320) 177 #define GLB_CTL_PAD_MAN_CFG_1_REG (GLB_CTL_BASE + 0x324) 178 #define GLB_CTL_PAD_OEN_CFG_0_REG (GLB_CTL_BASE + 0x328) 179 #define GLB_CTL_PAD_OEN_CFG_1_REG (GLB_CTL_BASE + 0x32C) 180 #define GLB_CTL_PAD_VALUE_CFG_0_REG (GLB_CTL_BASE + 0x330) 181 #define GLB_CTL_PAD_VALUE_CFG_1_REG (GLB_CTL_BASE + 0x334) 182 #define GLB_CTL_PAD_VALUE_0_REG (GLB_CTL_BASE + 0x338) 183 #define GLB_CTL_PAD_VALUE_1_REG (GLB_CTL_BASE + 0x33C) 184 #define GLB_CTL_PAD_PINMUX_CFG0_REG (GLB_CTL_BASE + 0x350) 185 #define GLB_CTL_PAD_PINMUX_CFG1_REG (GLB_CTL_BASE + 0x354) 186 #define GLB_CTL_REFCLK_FEQ_STATUS_REG (GLB_CTL_BASE + 0x358) 187 #define GLB_CTL_EXT_TSF_CLK_PERIOD_H_REG (GLB_CTL_BASE + 0x414) 188 #define GLB_CTL_EXT_TSF_CLK_PERIOD_L_REG (GLB_CTL_BASE + 0x418) 189 #define GLB_CTL_EFUSE_WR_DATA0_REG (GLB_CTL_BASE + 0x700) 190 #define GLB_CTL_EFUSE_WR_DATA1_REG (GLB_CTL_BASE + 0x704) 191 #define GLB_CTL_EFUSE_WR_DATA2_REG (GLB_CTL_BASE + 0x708) 192 #define GLB_CTL_EFUSE_WR_DATA3_REG (GLB_CTL_BASE + 0x70C) 193 #define GLB_CTL_EFUSE_WR_DATA4_REG (GLB_CTL_BASE + 0x710) 194 #define GLB_CTL_EFUSE_WR_DATA5_REG (GLB_CTL_BASE + 0x714) 195 #define GLB_CTL_EFUSE_WR_DATA6_REG (GLB_CTL_BASE + 0x718) 196 #define GLB_CTL_EFUSE_WR_DATA7_REG (GLB_CTL_BASE + 0x71C) 197 #define GLB_CTL_EFUSE_WR_DATA8_REG (GLB_CTL_BASE + 0x720) 198 #define GLB_CTL_EFUSE_WR_DATA9_REG (GLB_CTL_BASE + 0x724) 199 #define GLB_CTL_EFUSE_WR_DATA10_REG (GLB_CTL_BASE + 0x728) 200 #define GLB_CTL_EFUSE_WR_DATA11_REG (GLB_CTL_BASE + 0x72C) 201 #define GLB_CTL_EFUSE_WR_DATA12_REG (GLB_CTL_BASE + 0x730) 202 #define GLB_CTL_EFUSE_WR_DATA13_REG (GLB_CTL_BASE + 0x734) 203 #define GLB_CTL_EFUSE_WR_DATA14_REG (GLB_CTL_BASE + 0x738) 204 #define GLB_CTL_EFUSE_WR_DATA15_REG (GLB_CTL_BASE + 0x73C) 205 #define GLB_CTL_EFUSE_RD_DATA0_REG (GLB_CTL_BASE + 0x740) 206 #define GLB_CTL_EFUSE_RD_DATA1_REG (GLB_CTL_BASE + 0x744) 207 #define GLB_CTL_EFUSE_RD_DATA2_REG (GLB_CTL_BASE + 0x748) 208 #define GLB_CTL_EFUSE_RD_DATA3_REG (GLB_CTL_BASE + 0x74C) 209 #define GLB_CTL_EFUSE_RD_DATA4_REG (GLB_CTL_BASE + 0x750) 210 #define GLB_CTL_EFUSE_RD_DATA5_REG (GLB_CTL_BASE + 0x754) 211 #define GLB_CTL_EFUSE_RD_DATA6_REG (GLB_CTL_BASE + 0x758) 212 #define GLB_CTL_EFUSE_RD_DATA7_REG (GLB_CTL_BASE + 0x75C) 213 #define GLB_CTL_EFUSE_RD_DATA8_REG (GLB_CTL_BASE + 0x760) 214 #define GLB_CTL_EFUSE_RD_DATA9_REG (GLB_CTL_BASE + 0x764) 215 #define GLB_CTL_EFUSE_RD_DATA10_REG (GLB_CTL_BASE + 0x768) 216 #define GLB_CTL_EFUSE_RD_DATA11_REG (GLB_CTL_BASE + 0x76C) 217 #define GLB_CTL_EFUSE_RD_DATA12_REG (GLB_CTL_BASE + 0x770) 218 #define GLB_CTL_EFUSE_RD_DATA13_REG (GLB_CTL_BASE + 0x774) 219 #define GLB_CTL_EFUSE_RD_DATA14_REG (GLB_CTL_BASE + 0x778) 220 #define GLB_CTL_EFUSE_RD_DATA15_REG (GLB_CTL_BASE + 0x77C) 221 #define GLB_CTL_EFUSE_CLK_SEL_REG (GLB_CTL_BASE + 0x780) 222 #define GLB_CTL_EFUSE_CTL_REG (GLB_CTL_BASE + 0x784) 223 #define GLB_CTL_EFUSE_SOFT_RST_REG (GLB_CTL_BASE + 0x788) 224 #define GLB_CTL_CALI_32K_TCXO_CTL_REG (GLB_CTL_BASE + 0x800) 225 #define GLB_CTL_CALI_32K_TCXO_CNT_L_REG (GLB_CTL_BASE + 0x810) 226 #define GLB_CTL_CALI_32K_TCXO_CNT_H_REG (GLB_CTL_BASE + 0x814) 227 #define GLB_CTL_CALI_32K_TCXO_RESULT_L_REG (GLB_CTL_BASE + 0x818) 228 #define GLB_CTL_CALI_32K_TCXO_RESULT_H_REG (GLB_CTL_BASE + 0x81C) 229 #define GLB_CTL_AON_ICM_PRIORITY_REG (GLB_CTL_BASE + 0xF30) 230 #define GLB_CTL_MEM_CLK_FORCE_ON_REG (GLB_CTL_BASE + 0xF50) 231 #define GLB_CTL_MARGIN_ADJ_REG (GLB_CTL_BASE + 0xF54) 232 #define GLB_CTL_POR_RESET_REG (GLB_CTL_BASE + 0xF70) 233 #define GLB_CTL_UTMI_RESET_REG (GLB_CTL_BASE + 0xF74) 234 #define GLB_CTL_PHY_BIST_CTL_REG (GLB_CTL_BASE + 0xF78) 235 #define GLB_CTL_PHY_BIST_STS_REG (GLB_CTL_BASE + 0xF7C) 236 #define GLB_CTL_USB_REFCLK_CFG_REG (GLB_CTL_BASE + 0xF80) 237 #define GLB_CTL_DEFAULT_SLV_EN_REG (GLB_CTL_BASE + 0xF84) 238 #define GLB_CTL_DEFAULT_SLV_HIT_STATUS_REG (GLB_CTL_BASE + 0xF88) 239 #define GLB_CTL_DEFAULT_SLV_HIT_CLR_REG (GLB_CTL_BASE + 0xF8C) 240 #define GLB_CTL_REFCLK_FEQ_START_BIT 0 241 #define GLB_CTL_REFCLK_FEQ_BITS 1 242 243 /* PMU CMU */ 244 #define PMU_CMU_CTL_BASE 0x50002000 245 #define PMU_CMU_CTL_GP_REG0_REG (PMU_CMU_CTL_BASE + 0x010) 246 #define PMU_CMU_CTL_GP_REG1_REG (PMU_CMU_CTL_BASE + 0x014) 247 #define PMU_CMU_CTL_GP_REG2_REG (PMU_CMU_CTL_BASE + 0x018) 248 #define PMU_CMU_CTL_GP_REG3_REG (PMU_CMU_CTL_BASE + 0x01C) 249 #define PMU_CMU_CTL_UDSLEEP_BUTTON_CTRL_REG (PMU_CMU_CTL_BASE + 0x020) 250 #define PMU_CMU_CTL_UDSLEEP_BUTTON_RPT_REG (PMU_CMU_CTL_BASE + 0x024) 251 #define PMU_CMU_CTL_UDSLEEP_BUTTON_INT_EN_REG (PMU_CMU_CTL_BASE + 0x028) 252 #define PMU_CMU_CTL_FUSE_L_REG (PMU_CMU_CTL_BASE + 0x040) 253 #define PMU_CMU_CTL_FUSE_H_REG (PMU_CMU_CTL_BASE + 0x044) 254 #define PMU_CMU_CTL_FUSE_L_MAN_REG (PMU_CMU_CTL_BASE + 0x050) 255 #define PMU_CMU_CTL_FUSE_H_MAN_REG (PMU_CMU_CTL_BASE + 0x054) 256 #define PMU_CMU_CTL_FUSE_L_SEL_REG (PMU_CMU_CTL_BASE + 0x058) 257 #define PMU_CMU_CTL_FUSE_H_SEL_REG (PMU_CMU_CTL_BASE + 0x05C) 258 #define PMU_CMU_CTL_AON_PERP_CLKSEL_W_REG (PMU_CMU_CTL_BASE + 0x090) 259 #define PMU_CMU_CTL_PMU_MAN_CLR_0_REG (PMU_CMU_CTL_BASE + 0x104) 260 #define PMU_CMU_CTL_PMU_DBG_1_REG (PMU_CMU_CTL_BASE + 0x130) 261 #define PMU_CMU_CTL_PMU_DBG_SEL_1_REG (PMU_CMU_CTL_BASE + 0x134) 262 #define PMU_CMU_CTL_PMU_MAN_SEL_2 (PMU_CMU_CTL_BASE + 0x14C) 263 #define PMU_CMU_CTL_SYSLDO_CFG_0_REG (PMU_CMU_CTL_BASE + 0x200) 264 #define PMU_CMU_CTL_CLDO_CFG_0_REG (PMU_CMU_CTL_BASE + 0x208) 265 #define PMU_CMU_CTL_CLDO_CFG_1_REG (PMU_CMU_CTL_BASE + 0x20C) 266 #define PMU_CMU_CTL_VSET_AUTO_REG (PMU_CMU_CTL_BASE + 0x210) 267 #define PMU_CMU_CTL_VBATD_CFG_REG (PMU_CMU_CTL_BASE + 0x214) 268 #define PMU_CMU_CTL_PHYLDO_CFG_0_REG (PMU_CMU_CTL_BASE + 0x218) 269 #define PMU_CMU_CTL_PHYLDO_CFG_1_REG (PMU_CMU_CTL_BASE + 0x21C) 270 #define PMU_CMU_CTL_RFLDO1_CFG_0_REG (PMU_CMU_CTL_BASE + 0x220) 271 #define PMU_CMU_CTL_RFLDO1_CFG_1_REG (PMU_CMU_CTL_BASE + 0x224) 272 #define PMU_CMU_CTL_RFLDO2_CFG_0_REG (PMU_CMU_CTL_BASE + 0x228) 273 #define PMU_CMU_CTL_RFLDO2_CFG_1_REG (PMU_CMU_CTL_BASE + 0x22C) 274 #define PMU_CMU_CTL_RFLDO3_CFG_0_REG (PMU_CMU_CTL_BASE + 0x230) 275 #define PMU_CMU_CTL_RFLDO3_CFG_1_REG (PMU_CMU_CTL_BASE + 0x234) 276 #define PMU_CMU_CTL_RFLDO4_CFG_0_REG (PMU_CMU_CTL_BASE + 0x238) 277 #define PMU_CMU_CTL_RFLDO4_CFG_1_REG (PMU_CMU_CTL_BASE + 0x23c) 278 #define PMU_CMU_CTL_RFLDO5_CFG_0_REG (PMU_CMU_CTL_BASE + 0x240) 279 #define PMU_CMU_CTL_RFLDO5_CFG_1_REG (PMU_CMU_CTL_BASE + 0x244) 280 #define PMU_CMU_CTL_RFLDO6_CFG_0_REG (PMU_CMU_CTL_BASE + 0x248) 281 #define PMU_CMU_CTL_RFLDO6_CFG_1_REG (PMU_CMU_CTL_BASE + 0x24c) 282 #define PMU_CMU_CTL_EN_XLDO_CFG_0_REG (PMU_CMU_CTL_BASE + 0x250) 283 #define PMU_CMU_CTL_EN_XLDO_CFG_1_REG (PMU_CMU_CTL_BASE + 0x254) 284 #define PMU_CMU_CTL_EN_XLDO_CFG_2_REG (PMU_CMU_CTL_BASE + 0x258) 285 #define PMU_CMU_CTL_FLASHLDO_CFG_0_REG (PMU_CMU_CTL_BASE + 0x25c) 286 #define PMU_CMU_CTL_FLASHLDO_CFG_1_REG (PMU_CMU_CTL_BASE + 0x260) 287 #define PMU_CMU_CTL_PMU_MISC_CFG_0_REG (PMU_CMU_CTL_BASE + 0x270) 288 #define PMU_CMU_CTL_PMU_MISC_CFG_1_REG (PMU_CMU_CTL_BASE + 0x274) 289 #define PMU_CMU_CTL_PMU_MISC_CFG_2_REG (PMU_CMU_CTL_BASE + 0x278) 290 #define PMU_CMU_CTL_PMU_MISC_CFG_3_REG (PMU_CMU_CTL_BASE + 0x27c) 291 #define PMU_CMU_CTL_BUCK_VSET_REG (PMU_CMU_CTL_BASE + 0x280) 292 #define PMU_CMU_CTL_BUCK_CFG_0_REG (PMU_CMU_CTL_BASE + 0x284) 293 #define PMU_CMU_CTL_BUCK_CFG_1_REG (PMU_CMU_CTL_BASE + 0x288) 294 #define PMU_CMU_CTL_BUCK_CFG_2_REG (PMU_CMU_CTL_BASE + 0x28c) 295 #define PMU_CMU_CTL_BUCK_CFG_3_REG (PMU_CMU_CTL_BASE + 0x290) 296 #define PMU_CMU_CTL_VBAT_TH_CFG_REG (PMU_CMU_CTL_BASE + 0x294) 297 298 #define PMU_CMU_CTL_PMU_STATUS_RAW_REG (PMU_CMU_CTL_BASE + 0x300) 299 #define PMU_CMU_CTL_PMU_STATUS_GRM_STICK_CLR_REG (PMU_CMU_CTL_BASE + 0x328) 300 #define PMU_CMU_CTL_PMU_STATUS_GRM_TIME_REG (PMU_CMU_CTL_BASE + 0x330) 301 #define PMU_CMU_CTL_PMU_STATUS_GRM_TIME1_REG (PMU_CMU_CTL_BASE + 0x334) 302 #define PMU_CMU_CTL_PMU_STATUS_GRM_INT_EN_REG (PMU_CMU_CTL_BASE + 0x344) 303 #define PMU_CMU_CTL_GATE_TSENSOR_VDDIO_REG (PMU_CMU_CTL_BASE + 0x350) 304 #define PMU_CMU_CTL_BUCK_SLEEP3_REG (PMU_CMU_CTL_BASE + 0x364) 305 #define PMU_CMU_CTL_CMU_DBG_SEL_REG (PMU_CMU_CTL_BASE + 0x414) 306 #define PMU_CMU_CTL_CLK_480M_GT_REG (PMU_CMU_CTL_BASE + 0x420) 307 #define PMU_CMU_CTL_CLK_192M_GT_REG (PMU_CMU_CTL_BASE + 0x42C) 308 #define PMU_CMU_CTL_CLK_960M_GT_REG (PMU_CMU_CTL_BASE + 0x430) 309 #define PMU_CMU_CTL_REFDIV_REG (PMU_CMU_CTL_BASE + 0x500) 310 #define PMU_CMU_CTL_FBDIV_REG (PMU_CMU_CTL_BASE + 0x504) 311 #define PMU_CMU_CTL_FRAC_L_REG (PMU_CMU_CTL_BASE + 0x508) 312 #define PMU_CMU_CTL_FRAC_H_REG (PMU_CMU_CTL_BASE + 0x50C) 313 #define PMU_CMU_CTL_CMU_MISC_PD_REG (PMU_CMU_CTL_BASE + 0x514) 314 #define PMU_CMU_CTL_CMU_CLK_SEL_REG (PMU_CMU_CTL_BASE + 0x518) 315 #define PMU_CMU_CTL_CMU_STATUS_RAW_REG (PMU_CMU_CTL_BASE + 0x600) 316 #define PMU_CMU_CTL_SYS_STATUS_REG (PMU_CMU_CTL_BASE + 0x804) 317 #define PMU_CMU_CTL_WKUP_TIME_WLAN_EN_FLASH_REG (PMU_CMU_CTL_BASE + 0x810) 318 #define PMU_CMU_CTL_WKUP_TIME_WLAN_EN_PMU_REF2_REG (PMU_CMU_CTL_BASE + 0x814) 319 #define PMU_CMU_CTL_WKUP_TIME_WLAN_EN_PMU_REG (PMU_CMU_CTL_BASE + 0x818) 320 #define PMU_CMU_CTL_WKUP_TIME_WLAN_CMU_XLDO_EN_REG (PMU_CMU_CTL_BASE + 0x81C) 321 #define PMU_CMU_CTL_WKUP_TIME_WLAN_BUCK_EN_REG (PMU_CMU_CTL_BASE + 0x820) 322 #define PMU_CMU_CTL_WKUP_TIME_WLAN_EN_CLDO_REG (PMU_CMU_CTL_BASE + 0x824) 323 #define PMU_CMU_CTL_WKUP_TIME_WLAN_EN_RFLDO4_REG (PMU_CMU_CTL_BASE + 0x828) 324 #define PMU_CMU_CTL_WKUP_TIME_WLAN_SDIO_SUB_PWR_EN_REG (PMU_CMU_CTL_BASE + 0x838) 325 #define PMU_CMU_CTL_WKUP_TIME_WLAN_XO2PLL_BUF_PD_REG (PMU_CMU_CTL_BASE + 0x83C) 326 #define PMU_CMU_CTL_WKUP_TIME_WLAN_CMU_ISO_EN_REG (PMU_CMU_CTL_BASE + 0x840) 327 #define PMU_CMU_CTL_WKUP_TIME_WLAN_XLDO_VCO_GT_REG (PMU_CMU_CTL_BASE + 0x844) 328 #define PMU_CMU_CTL_WKUP_TIME_WLAN_TCXO2DBB_GT_REG (PMU_CMU_CTL_BASE + 0x848) 329 #define PMU_CMU_CTL_WKUP_TIME_WLAN_CLK_TCXO_EN_REG (PMU_CMU_CTL_BASE + 0x84C) 330 #define PMU_CMU_CTL_WKUP_TIME_WLAN_PD_REG (PMU_CMU_CTL_BASE + 0x854) 331 #define PMU_CMU_CTL_WKUP_TIME_WLAN_CLK_FON_REG (PMU_CMU_CTL_BASE + 0x858) 332 #define PMU_CMU_CTL_WKUP_TIME_WLAN_RST_RELEASE_REG (PMU_CMU_CTL_BASE + 0x85C) 333 #define PMU_CMU_CTL_WLAN_STA0_ALLOW_TO_SLEEP_REG (PMU_CMU_CTL_BASE + 0x900) 334 #define PMU_CMU_CTL_WLAN_STA1_ALLOW_TO_SLEEP_REG (PMU_CMU_CTL_BASE + 0x904) 335 #define PMU_CMU_CTL_WLAN_AP0_ALLOW_TO_SLEEP_REG (PMU_CMU_CTL_BASE + 0x908) 336 #define PMU_CMU_CTL_WLAN_PF_ALLOW_TO_SLEEP_REG (PMU_CMU_CTL_BASE + 0x90C) 337 #define PMU_CMU_CTL_WLAN_HOST_ALLOW_TO_SLEEP_REG (PMU_CMU_CTL_BASE + 0x910) 338 #define PMU_CMU_CTL_WLAN_SLP_EVT_EN_REG (PMU_CMU_CTL_BASE + 0x920) 339 #define PMU_CMU_CTL_WLAN_SLP_EVT_CLR_REG (PMU_CMU_CTL_BASE + 0x924) 340 #define PMU_CMU_CTL_WLAN_SLP_INT_CLR_REG (PMU_CMU_CTL_BASE + 0x934) 341 #define PMU_CMU_CTL_WLAN_WKUP_EVT_EN_REG (PMU_CMU_CTL_BASE + 0x940) 342 #define PMU_CMU_CTL_WLAN_WKUP_EVT_CLR_REG (PMU_CMU_CTL_BASE + 0x944) 343 #define PMU_CMU_CTL_WLAN_WKUP_EVT_STS_REG (PMU_CMU_CTL_BASE + 0x948) 344 #define PMU_CMU_CTL_WLAN_WKUP_INT_EN_REG (PMU_CMU_CTL_BASE + 0x950) 345 #define PMU_CMU_CTL_WLAN_WKUP_INT_CLR_REG (PMU_CMU_CTL_BASE + 0x954) 346 #define PMU_CMU_CTL_WLAN_WKUP_INT_STS_REG (PMU_CMU_CTL_BASE + 0x958) 347 #define PMU_CMU_CTL_DEBUG_GLB_SIGNAL_SEL_2_REG (PMU_CMU_CTL_BASE + 0xF24) 348 349 #define CRG_REG_SC_PLLLOCK_STAT_REG (HI_CRG_REG_BASE + 0x0) 350 #define CRG_REG_SC_APLL_CTRL0_REG (HI_CRG_REG_BASE + 0x4) 351 #define CRG_REG_SC_APLL_CTRL1_REG (HI_CRG_REG_BASE + 0x8) 352 #define CRG_REG_SC_PERI_CLKEN0_REG (HI_CRG_REG_BASE + 0x14) 353 #define CRG_REG_SC_PERI_CLKEN1_REG (HI_CRG_REG_BASE + 0x18) 354 #define CRG_REG_SC_PERI_CLKSTAT0_REG (HI_CRG_REG_BASE + 0x1C) 355 #define CRG_REG_SC_PERI_CLKSTAT1_REG (HI_CRG_REG_BASE + 0x20) 356 #define CRG_REG_SC_PERI_CLKSEL_REG (HI_CRG_REG_BASE + 0x24) 357 #define CRG_REG_SC_PERI_SRST_REG (HI_CRG_REG_BASE + 0x28) 358 #define CRG_REG_SC_SLEEP0_CTRL_REG (HI_CRG_REG_BASE + 0x2C) 359 360 #define CRG_REG_SC_PHY_CLK_EN_REG (HI_CRG_REG_BASE + 0x30) 361 #define CRG_REG_SC_PHY_SRST_REG (HI_CRG_REG_BASE + 0x34) 362 #define CRG_REG_SC_PHY_RST_MASK_REG (HI_CRG_REG_BASE + 0x38) 363 #define CRG_REG_MEM_TOP_GATE_EN_REG (HI_CRG_REG_BASE + 0x3C) 364 #define CRG_REG_BOOT_ROM_GATE_EN_REG (HI_CRG_REG_BASE + 0x40) 365 #define CRG_REG_SC_PHY_RST1_MASK_REG (HI_CRG_REG_BASE + 0x44) 366 #define CRG_REG_SC_SLEEP1_CTRL_REG (HI_CRG_REG_BASE + 0x48) 367 368 #define CRG_REG_SC_DEEP_SLEEP0_CTRL_REG (HI_CRG_REG_BASE + 0x4C) 369 370 #define CRG_REG_SC_DEEP_SLEEP1_CTRL_REG (HI_CRG_REG_BASE + 0x50) 371 372 #define CRG_REG_SC_PERI_SRST1_REG (HI_CRG_REG_BASE + 0x54) 373 #define CRG_REG_SC_PHY1_SRST1_REG (HI_CRG_REG_BASE + 0x58) 374 #define CRG_REG_XTAL_IO_CTRL_REG (HI_CRG_REG_BASE + 0x5C) 375 376 #define CRG_REG_SSP_SRST_REQ_LEN 1 377 #define CRG_REG_SSP_SRST_REQ_OFFSET 7 378 #define CRG_REG_SSP2_SRST_REQ_LEN 1 379 #define CRG_REG_SSP2_SRST_REQ_OFFSET 5 380 #define CRG_REG_I2C_SRST_REQ_LEN 1 381 #define CRG_REG_I2C_SRST_REQ_OFFSET 12 382 #define CRG_REG_SFC_SRST_REQ_LEN 1 383 #define CRG_REG_SFC_SRST_REQ_OFFSET 2 384 #define CRG_REG_SFC_BUS_CLK_EN_LEN 1 385 #define CRG_REG_SFC_BUS_CLK_EN_OFFSET 17 386 #define CRG_REG_SFC_CLK_EN_LEN 1 387 #define CRG_REG_SFC_CLK_EN_OFFSET 16 388 389 #define SYSCTRL_SC_CTRL_REG (HI_SYSCTRL_REG_BASE + 0x0) 390 #define SYSCTRL_SC_SYSRES_REG (HI_SYSCTRL_REG_BASE + 0x4) 391 #define SYSCTRL_SC_IMCTRL_REG (HI_SYSCTRL_REG_BASE + 0x8) 392 #define SYSCTRL_SC_IMSTAT_REG (HI_SYSCTRL_REG_BASE + 0xC) 393 #define SYSCTRL_SC_XTALCTRL_REG (HI_SYSCTRL_REG_BASE + 0x10) 394 #define SYSCTRL_SC_PLLCTRL_REG (HI_SYSCTRL_REG_BASE + 0x14) 395 #define SYSCTRL_SC_AFE_CTRL_REG (HI_SYSCTRL_REG_BASE + 0x20) 396 #define SYSCTRL_SC_VERSION_ID_REG (HI_SYSCTRL_REG_BASE + 0x24) 397 #define SYSCTRL_SC_HW_ID_REG (HI_SYSCTRL_REG_BASE + 0x28) 398 #define SYSCTRL_SC_PERI_CTRL_REG (HI_SYSCTRL_REG_BASE + 0x2C) 399 #define SYSCTRL_SC_LOCKEN_REG (HI_SYSCTRL_REG_BASE + 0x38) 400 #define SYSCTRL_SC_PAD_CONFIG_REG (HI_SYSCTRL_REG_BASE + 0x3C) 401 #define SYSCTRL_SC_GEN_REG0_REG (HI_SYSCTRL_REG_BASE + 0x40) 402 #define SYSCTRL_SC_GEN_REG1_REG (HI_SYSCTRL_REG_BASE + 0x44) 403 #define SYSCTRL_SC_GEN_REG2_REG (HI_SYSCTRL_REG_BASE + 0x48) 404 #define SYSCTRL_SC_GEN_REG3_REG (HI_SYSCTRL_REG_BASE + 0x4C) 405 #define SYSCTRL_SC_GEN_REG4_REG (HI_SYSCTRL_REG_BASE + 0x50) 406 #define SYSCTRL_SC_GEN_REG5_REG (HI_SYSCTRL_REG_BASE + 0x54) 407 #define SYSCTRL_SC_GEN_REG6_REG (HI_SYSCTRL_REG_BASE + 0x58) 408 #define SYSCTRL_SC_GEN_REG7_REG (HI_SYSCTRL_REG_BASE + 0x5C) 409 410 #define PKTB_MODE_NOT_CHANGE 0 411 #define PKTB_MODE_32K 1 412 #define PKTB_MODE_48K 2 413 #define PKTB_MODE_64K 3 414 #define PKTB_MODE_80K 4 415 #define PKTB_MODE_96K 5 416 #define PKTB_MODE_112K 6 417 #define PKTB_MODE_128K 7 418 #define PKTB_MODE_144K 8 419 #define PKTB_MODE_160K 9 420 #define PKTB_MODE_176K 10 421 #define PKTB_MODE_192K 11 422 #define PKTB_MODE_DEFAULT PKTB_MODE_64K 423 424 /* DIAG CTL REG */ 425 #define DIAG_CTL_BASE 0x40060000 426 #define DIAG_CTL_GP_REG0_REG (DIAG_CTL_BASE + 0x010) /* used to save rsa key */ 427 #define DIAG_CTL_GP_REG1_REG (DIAG_CTL_BASE + 0x014) /* used to save rsa key */ 428 #define DIAG_CTL_GP_REG2_REG (DIAG_CTL_BASE + 0x018) /* used to save ecc key */ 429 #define DIAG_CTL_GP_REG3_REG (DIAG_CTL_BASE + 0x01C) /* used to save ecc key */ 430 #define DIAG_CTL_DIAG_MUX (DIAG_CTL_BASE + 0x0BC) /* diag mux */ 431 #define DIAG_CTL_CLOCK_TEST_SEL (DIAG_CTL_BASE + 0x0D0) /* clock test div */ 432 #define DIAG_CTL_CLOCK_TEST_DIV (DIAG_CTL_BASE + 0x0D4) /* clock test div */ 433 #define DIAG_CTL_CLOCK_TEST_EN (DIAG_CTL_BASE + 0x0D8) /* clock test en */ 434 435 436 #endif /* __HI3861_PLATFORM_BASE_H */ 437