1 /* 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef __UART_H__ 17 #define __UART_H__ 18 19 #include <hi3861_platform.h> 20 21 #include "uart_drv.h" 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 #define UART_NUM 3 28 #define UART0 0 29 #define UART1 1 30 #define UART2 2 31 32 #define UART0_BASE (HI_UART0_REG_BASE) 33 #define UART1_BASE (HI_UART1_REG_BASE) 34 #define UART2_BASE (HI_UART2_REG_BASE) 35 36 #define UART_CIRC_BUF_ENABLE 37 #define UART_DEFAULT_TX_FIFO_LINE 2 /* tx FIFO<=1/2full */ 38 #define UART_DEFAULT_RX_FIFO_LINE 1 /* rx FIFO>=1/4full */ 39 #define UART_DEFAULT_FLOW_FIFO_LINE 3 /* rx FIFO>=3/4full */ 40 #define UART_DEFAULT_TX_BUFFER_SIZE 0x0200 41 #define UART_DEFAULT_RX_BUFFER_SIZE 0x0200 42 #define UART_DEFAULT_TX_USE_DMA 1 /* not use dma */ 43 #define UART_DEFAULT_RX_USE_DMA 1 /* not use dma */ 44 #define UART_DEFAULT_TX_BLOCK 2 /* block */ 45 #define UART_DEFAULT_RX_BLOCK 2 /* block */ 46 47 #define UART_DEFAULT_FLOW_CONTROL 0 /* 0: disable flow ctrl; 1: enable rts and cts; 2: enable rts only; 48 3: enable cts only. notice: uart0 not support flow ctrl. */ 49 50 #define UART_ATTR_DEFAULT {115200, 8, 1, 0, UART_DEFAULT_TX_FIFO_LINE, UART_DEFAULT_RX_FIFO_LINE, \ 51 UART_DEFAULT_FLOW_FIFO_LINE, UART_DEFAULT_FLOW_CONTROL, HI_FALSE} 52 #define UART_ACT_DEFAULT {UART_DEFAULT_TX_BUFFER_SIZE, UART_DEFAULT_RX_BUFFER_SIZE, UART_DEFAULT_TX_USE_DMA, \ 53 UART_DEFAULT_RX_USE_DMA, UART_DEFAULT_TX_BLOCK, UART_DEFAULT_RX_BLOCK} 54 55 56 uart_driver_data_t *uart_open(hi_u32 uart_index, uart_mode uart_mode); 57 hi_s32 uart_read(uart_driver_data_t *udd, hi_char *buf, hi_u32 count); 58 hi_s32 uart_write(uart_driver_data_t *udd, const hi_char *buf, hi_u32 count); 59 hi_s32 uart_write_immediately(uart_driver_data_t *udd, const hi_char *buf, hi_u32 count); 60 hi_u32 uart_ioctl(uart_driver_data_t *udd, hi_u32 cmd, uintptr_t arg); 61 hi_u32 uart_close(uart_driver_data_t *udd); 62 63 extern uart_driver_data_t *g_udd_g[UART_NUM]; 64 extern uart_ops g_uart_driver_uops; 65 66 #ifdef __cplusplus 67 } 68 #endif 69 #endif 70 71