1 /* 2 * Copyright (c) 2021 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef _HPM_DRAM_DRV_H 9 #define _HPM_DRAM_DRV_H 10 #include "hpm_dram_regs.h" 11 12 /** 13 * @brief DRAM driver APIs 14 * @defgroup dram_interface DRAM driver APIs 15 * @ingroup io_interfaces 16 * @{ 17 * 18 */ 19 20 #define DRAM_SDRAM_MAX_BURST_LENGTH_IN_BYTE (8UL) 21 /* @brief dram sdram column address bit width */ 22 #define DRAM_SDRAM_COLUMN_ADDR_12_BITS (0U) 23 #define DRAM_SDRAM_COLUMN_ADDR_11_BITS (1U) 24 #define DRAM_SDRAM_COLUMN_ADDR_10_BITS (2U) 25 #define DRAM_SDRAM_COLUMN_ADDR_9_BITS (3U) 26 #define DRAM_SDRAM_COLUMN_ADDR_8_BITS (4U) 27 /* @brief cas latency */ 28 #define DRAM_SDRAM_CAS_LATENCY_1 (1U) 29 #define DRAM_SDRAM_CAS_LATENCY_2 (2U) 30 #define DRAM_SDRAM_CAS_LATENCY_3 (3U) 31 /* @brief iomux options */ 32 #define DRAM_IO_MUX_NOT_USED (0U) 33 #define DRAM_IO_MUX_CSX0 (1U) 34 #define DRAM_IO_MUX_CSX1 (2U) 35 #define DRAM_IO_MUX_CSX2 (3U) 36 #define DRAM_IO_MUX_CSX3 (4U) 37 #define DRAM_IO_MUX_RDY (5U) 38 /* @brief sdram bank number */ 39 #define DRAM_SDRAM_BANK_NUM_4 (0U) 40 #define DRAM_SDRAM_BANK_NUM_2 (1U) 41 /* @brief chip select */ 42 #define DRAM_SDRAM_CS0 (0U) 43 #define DRAM_SDRAM_CS1 (1U) 44 /* @brief sdram port size */ 45 #define DRAM_SDRAM_PORT_SIZE_8_BITS (0U) 46 #define DRAM_SDRAM_PORT_SIZE_16_BITS (1U) 47 #define DRAM_SDRAM_PORT_SIZE_32_BITS (2U) 48 49 #define DRAM_AXI_Q_COUNT (2U) 50 #define DRAM_AXI_Q_A (0U) 51 #define DRAM_AXI_Q_B (1U) 52 /* @brief DQS option */ 53 #define DRAM_DQS_INTERNAL (0U) 54 #define DRAM_DQS_FROM_PAD (1U) 55 56 #define DRAM_BR_COUNT (2U) 57 58 #define DRAM_CMD_KEY DRAM_IPCMD_KEY_SET(0xA55A) 59 #define DRAM_CMD_WRITE_FLAG (1UL << 31) 60 #define DRAM_CMD_SDRAM_READ (0x8U) 61 #define DRAM_CMD_SDRAM_WRITE (DRAM_CMD_WRITE_FLAG | 0x9U) 62 #define DRAM_CMD_SDRAM_MODE_SET (DRAM_CMD_WRITE_FLAG | 0xAU) 63 #define DRAM_CMD_SDRAM_ACTIVE (0xBU) 64 #define DRAM_CMD_SDRAM_AUTO_REFRESH (0xCU) 65 #define DRAM_CMD_SDRAM_SELF_REFRESH (0xDU) 66 #define DRAM_CMD_SDRAM_PRECHARGE (0xEU) 67 #define DRAM_CMD_SDRAM_PRECHARGE_ALL (0xFU) 68 69 /** 70 * @brief Structure for specifying the configuration of AXI queue weight 71 */ 72 typedef struct { 73 bool enable; /**< Enable AXI weight setting flag */ 74 uint8_t qos; 75 uint8_t age; 76 uint8_t slave_hit_wo_rw; 77 uint8_t slave_hit; /**< only available for queue A */ 78 uint8_t page_hit; /**< only available for queue B */ 79 uint8_t bank_rotation; /**< only available for queue B */ 80 } dram_axi_q_weight_t; 81 82 /** 83 * @brief Structure for specifying the configuration of SDRAM 84 */ 85 typedef struct { 86 uint32_t base_address; /**< external SDRAM base address */ 87 uint32_t size_in_byte; /**< external SDRAM size in byte */ 88 uint32_t refresh_count; /**< referesh count */ 89 uint8_t col_addr_bits; /**< column address bit count */ 90 uint8_t cas_latency; /**< CAS latency */ 91 uint8_t cs; /**< chip select */ 92 uint8_t cs_mux_pin; /**< chip select mux */ 93 uint8_t bank_num; /**< bank number */ 94 uint8_t prescaler; /**< presecaler */ 95 uint8_t port_size; /**< SDRAM port size */ 96 uint8_t burst_len_in_byte; /**< 1/2/4/8 bytes */ 97 uint8_t cke_off_in_ns; /**< Tcks */ 98 uint8_t act_to_precharge_in_ns; /**< Tras */ 99 uint8_t precharge_to_act_in_ns; /**< Trp */ 100 uint8_t act_to_rw_in_ns; /**< Trcd */ 101 uint8_t act_to_act_in_ns; /**< Trrd */ 102 uint8_t refresh_to_refresh_in_ns; /**< Trc */ 103 uint8_t write_recover_in_ns; /**< Tdpl */ 104 uint8_t self_refresh_recover_in_ns; /**< Txsr */ 105 uint8_t refresh_recover_in_ns; /**< Txsr */ 106 uint8_t refresh_in_ms; /**< Tref */ 107 uint8_t idle_timeout_in_ns; 108 uint8_t data_width_in_byte; 109 uint8_t auto_refresh_count_in_one_burst; 110 uint8_t delay_cell_value; /**< Delay cell value */ 111 } dram_sdram_config_t; 112 113 /** 114 * @brief Structure for specifying the configuration of DRAM 115 */ 116 typedef struct { 117 uint8_t dqs; /**< DQS setting */ 118 uint8_t cmd_timeout; /**< command timeout */ 119 uint8_t bus_timeout; /**< bus timeout */ 120 dram_axi_q_weight_t axi_q_weight[DRAM_AXI_Q_COUNT]; 121 } dram_config_t; 122 123 /** 124 * @brief Structure for DRAM command 125 */ 126 typedef struct { 127 uint32_t opcode; 128 uint32_t data; 129 } dram_cmd_t; 130 131 /* 132 * @brief DRAM specific status 133 */ 134 enum { 135 status_dram_cmd_err = MAKE_STATUS(status_group_dram, 1), 136 }; 137 138 #ifdef __cplusplus 139 extern "C" { 140 #endif 141 142 /** 143 * @brief dram enable 144 * 145 * Enable DRAM 146 * 147 * @param[in] ptr DRAM base address 148 */ dram_enable(DRAM_Type * ptr)149static inline void dram_enable(DRAM_Type *ptr) 150 { 151 ptr->CTRL &= ~DRAM_CTRL_DIS_MASK; 152 } 153 154 /** 155 * @brief dram disable 156 * 157 * Disable DRAM 158 * 159 * @param[in] ptr DRAM base address 160 */ dram_disable(DRAM_Type * ptr)161static inline void dram_disable(DRAM_Type *ptr) 162 { 163 while ((ptr->STAT0 & (uint32_t) DRAM_STAT0_IDLE_MASK) == 0) { 164 } 165 ptr->CTRL |= DRAM_CTRL_DIS_MASK; 166 } 167 168 /** 169 * @brief dram software reset 170 * 171 * Perform software reset 172 * 173 * @param[in] ptr DRAM base address 174 */ dram_sw_reset(DRAM_Type * ptr)175static inline void dram_sw_reset(DRAM_Type *ptr) 176 { 177 ptr->CTRL = DRAM_CTRL_RST_MASK; 178 while ((ptr->CTRL & (uint32_t) DRAM_CTRL_RST_MASK) != 0) { 179 } 180 } 181 182 /** 183 * @brief dram get default config 184 * 185 * Get DRAM default parameters 186 * 187 * @param[in] ptr DRAM base address 188 * @param[out] config dram_config_t address 189 */ 190 void dram_default_config(DRAM_Type *ptr, dram_config_t *config); 191 192 /** 193 * @brief dram init controller 194 * 195 * Initialize DRAM with give dram_config_t 196 * 197 * @param[in] ptr DRAM base address 198 * @param[in] config dram_config_t to initialize dram 199 */ 200 void dram_init(DRAM_Type *ptr, dram_config_t *config); 201 202 /** 203 * @brief dram get typical sdram config 204 * 205 * Fill out the structure of dram_sdram_config_t with typical SDRAM parameters which should work 206 * with most SDRAMs. 207 * 208 * @param[in] ptr DRAM base address 209 * @param[out] config dram_sdram_config_t sdram configuration struction to config dram 210 */ 211 void dram_get_typical_sdram_config(DRAM_Type *ptr, dram_sdram_config_t *config); 212 213 /** 214 * @brief dram config sdram 215 * 216 * Configure DRAM controlling external SDRAM using parameters specified in dram_sdram_config 217 * 218 * @param[in] ptr DRAM base address 219 * @param[in] clk_in_hz dram source clock frequency in Hz 220 * @param[in] config dram_sdram_config_t sdram configuration struction to config dram 221 */ 222 hpm_stat_t dram_config_sdram(DRAM_Type *ptr, uint32_t clk_in_hz, dram_sdram_config_t *config); 223 224 #ifdef __cplusplus 225 } 226 #endif 227 /** 228 * @} 229 */ 230 #endif /* _HPM_DRAM_DRV_H */ 231 232