1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Pinctrl driver for Rockchip SoCs
4 *
5 * Copyright (c) 2013 MundoReader S.L.
6 * Author: Heiko Stuebner <heiko@sntech.de>
7 *
8 * With some ideas taken from pinctrl-samsung:
9 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
10 * http://www.samsung.com
11 * Copyright (c) 2012 Linaro Ltd
12 * https://www.linaro.org
13 *
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
16 */
17
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/io.h>
22 #include <linux/bitops.h>
23 #include <linux/gpio.h>
24 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
26 #include <linux/of_device.h>
27 #include <linux/pinctrl/machine.h>
28 #include <linux/pinctrl/pinconf.h>
29 #include <linux/pinctrl/pinctrl.h>
30 #include <linux/pinctrl/pinmux.h>
31 #include <linux/pinctrl/pinconf-generic.h>
32 #include <linux/irqchip/chained_irq.h>
33 #include <linux/clk.h>
34 #include <linux/regmap.h>
35 #include <linux/mfd/syscon.h>
36 #include <linux/rockchip/cpu.h>
37 #include <dt-bindings/pinctrl/rockchip.h>
38
39 #include "core.h"
40 #include "pinconf.h"
41 #include "pinctrl-rockchip.h"
42
43 #define PINCTRL_ROCKCHIP_ZERO 0
44 #define PINCTRL_ROCKCHIP_ONE 1
45 #define PINCTRL_ROCKCHIP_TWO 2
46 #define PINCTRL_ROCKCHIP_THREE 3
47 #define PINCTRL_ROCKCHIP_FOUR 4
48 #define PINCTRL_ROCKCHIP_FIVE 5
49 #define PINCTRL_ROCKCHIP_SIX 6
50 #define PINCTRL_ROCKCHIP_SEVEN 7
51 #define PINCTRL_ROCKCHIP_EIGHT 8
52 #define PINCTRL_ROCKCHIP_NINE 9
53 #define PINCTRL_ROCKCHIP_TEN 10
54 #define PINCTRL_ROCKCHIP_ELEVEN 11
55 #define PINCTRL_ROCKCHIP_TWELVE 12
56 #define PINCTRL_ROCKCHIP_THIRTEEN 13
57 #define PINCTRL_ROCKCHIP_FOURTEEN 14
58 #define PINCTRL_ROCKCHIP_FIFTEEN 15
59 #define PINCTRL_ROCKCHIP_SIXTEEN 16
60 #define PINCTRL_ROCKCHIP_EIGHTEEN 18
61 #define PINCTRL_ROCKCHIP_NINTEEN 19
62 #define PINCTRL_ROCKCHIP_TWENTY 20
63 #define PINCTRL_ROCKCHIP_TWENTYONE 21
64 #define PINCTRL_ROCKCHIP_TWENTYTWO 22
65 #define PINCTRL_ROCKCHIP_TWENTYTHREE 23
66 #define PINCTRL_ROCKCHIP_TWENTYFOUR 24
67 #define PINCTRL_ROCKCHIP_TWENTYSIX 26
68 #define PINCTRL_ROCKCHIP_TWENTYSEVEN 27
69 #define PINCTRL_ROCKCHIP_THIRTY 30
70 #define PINCTRL_ROCKCHIP_THIRTYONE 31
71 #define PINCTRL_ROCKCHIP_THIRTYTWO 32
72
73 /**
74 * Generate a bitmask for setting a value (v) with a write mask bit in hiword
75 * register 31:16 area.
76 */
77 #define WRITE_MASK_VAL(h, l, v) (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l))))
78
79 /*
80 * Encode variants of iomux registers into a type variable
81 */
82 #define IOMUX_GPIO_ONLY BIT(0)
83 #define IOMUX_WIDTH_4BIT BIT(1)
84 #define IOMUX_SOURCE_PMU BIT(2)
85 #define IOMUX_UNROUTED BIT(3)
86 #define IOMUX_WIDTH_3BIT BIT(4)
87 #define IOMUX_WIDTH_2BIT BIT(5)
88 #define IOMUX_WRITABLE_32BIT BIT(6)
89 #define IOMUX_L_SOURCE_PMU BIT(7)
90
91 #define PIN_BANK(id, pins, label) \
92 { \
93 .bank_num = (id), .nr_pins = (pins), .name = (label), \
94 .iomux = { \
95 {.offset = -1}, \
96 {.offset = -1}, \
97 {.offset = -1}, \
98 {.offset = -1}, \
99 }, \
100 }
101
102 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
103 { \
104 .bank_num = (id), .nr_pins = (pins), .name = (label), \
105 .iomux = { \
106 {.type = (iom0), .offset = -1}, \
107 {.type = (iom1), .offset = -1}, \
108 {.type = (iom2), .offset = -1}, \
109 {.type = (iom3), .offset = -1}, \
110 }, \
111 }
112
113 #define PIN_BANK_IOMUX_FLAGS_OFFSET(id, pins, label, iom0, iom1, iom2, iom3, offset0, offset1, offset2, offset3) \
114 { \
115 .bank_num = (id), .nr_pins = (pins), .name = (label), \
116 .iomux = { \
117 {.type = (iom0), .offset = (offset0)}, \
118 {.type = (iom1), .offset = (offset1)}, \
119 {.type = (iom2), .offset = (offset2)}, \
120 {.type = (iom3), .offset = (offset3)}, \
121 }, \
122 }
123
124 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
125 { \
126 .bank_num = (id), .nr_pins = (pins), .name = (label), \
127 .iomux = \
128 { \
129 {.offset = -1}, \
130 {.offset = -1}, \
131 {.offset = -1}, \
132 {.offset = -1}, \
133 }, \
134 .drv = { \
135 {.drv_type = (type0), .offset = -1}, \
136 {.drv_type = (type1), .offset = -1}, \
137 {.drv_type = (type2), .offset = -1}, \
138 {.drv_type = (type3), .offset = -1}, \
139 }, \
140 }
141
142 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, drv2, drv3, pull0, pull1, pull2, pull3) \
143 { \
144 .bank_num = (id), .nr_pins = (pins), .name = (label), \
145 .iomux = \
146 { \
147 {.offset = -1}, \
148 {.offset = -1}, \
149 {.offset = -1}, \
150 {.offset = -1}, \
151 }, \
152 .drv = \
153 { \
154 {.drv_type = (drv0), .offset = -1}, \
155 {.drv_type = (drv1), .offset = -1}, \
156 {.drv_type = (drv2), .offset = -1}, \
157 {.drv_type = (drv3), .offset = -1}, \
158 }, \
159 .pull_type[0] = (pull0), .pull_type[1] = (pull1), .pull_type[2] = (pull2), .pull_type[3] = (pull3), \
160 }
161
162 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, iom2, iom3, drv0, drv1, drv2, drv3, offset0, \
163 offset1, offset2, offset3) \
164 { \
165 .bank_num = (id), .nr_pins = (pins), .name = (label), \
166 .iomux = \
167 { \
168 {.type = (iom0), .offset = -1}, \
169 {.type = (iom1), .offset = -1}, \
170 {.type = (iom2), .offset = -1}, \
171 {.type = (iom3), .offset = -1}, \
172 }, \
173 .drv = { \
174 {.drv_type = (drv0), .offset = (offset0)}, \
175 {.drv_type = (drv1), .offset = (offset1)}, \
176 {.drv_type = (drv2), .offset = (offset2)}, \
177 {.drv_type = (drv3), .offset = (offset3)}, \
178 }, \
179 }
180
181 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, label, iom0, iom1, iom2, iom3, drv0, drv1, drv2, \
182 drv3, offset0, offset1, offset2, offset3, pull0, pull1, \
183 pull2, pull3) \
184 { \
185 .bank_num = (id), .nr_pins = (pins), .name = (label), \
186 .iomux = \
187 { \
188 {.type = (iom0), .offset = -1}, \
189 {.type = (iom1), .offset = -1}, \
190 {.type = (iom2), .offset = -1}, \
191 {.type = (iom3), .offset = -1}, \
192 }, \
193 .drv = \
194 { \
195 {.drv_type = (drv0), .offset = (offset0)}, \
196 {.drv_type = (drv1), .offset = (offset1)}, \
197 {.drv_type = (drv2), .offset = (offset2)}, \
198 {.drv_type = (drv3), .offset = (offset3)}, \
199 }, \
200 .pull_type[0] = (pull0), .pull_type[1] = (pull1), .pull_type[2] = (pull2), .pull_type[3] = (pull3), \
201 }
202
203 #define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \
204 { \
205 .bank_num = (ID), .pin = (PIN), .func = (FUNC), .route_offset = (REG), .route_val = (VAL), \
206 .route_location = (FLAG), \
207 }
208
209 #define RK_MUXROUTE_SAME(ID, PIN, FUNC, REG, VAL) PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME)
210
211 #define RK_MUXROUTE_GRF(ID, PIN, FUNC, REG, VAL) PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF)
212
213 #define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL) PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU)
214
215 static struct regmap_config rockchip_regmap_config = {
216 .reg_bits = PINCTRL_ROCKCHIP_THIRTYTWO,
217 .val_bits = PINCTRL_ROCKCHIP_THIRTYTWO,
218 .reg_stride = PINCTRL_ROCKCHIP_FOUR,
219 };
220
pinctrl_name_to_group(const struct rockchip_pinctrl * info,const char * name)221 static inline const struct rockchip_pin_group *pinctrl_name_to_group(const struct rockchip_pinctrl *info,
222 const char *name)
223 {
224 int i;
225
226 for (i = 0; i < info->ngroups; i++) {
227 if (!strcmp(info->groups[i].name, name)) {
228 return &info->groups[i];
229 }
230 }
231
232 return NULL;
233 }
234
235 /*
236 * given a pin number that is local to a pin controller, find out the pin bank
237 * and the register base of the pin bank.
238 */
pin_to_bank(struct rockchip_pinctrl * info,unsigned pin)239 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info, unsigned pin)
240 {
241 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
242
243 while (pin >= (b->pin_base + b->nr_pins)) {
244 b++;
245 }
246
247 return b;
248 }
249
bank_num_to_bank(struct rockchip_pinctrl * info,unsigned num)250 static struct rockchip_pin_bank *bank_num_to_bank(struct rockchip_pinctrl *info, unsigned num)
251 {
252 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
253 int i;
254
255 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
256 if (b->bank_num == num) {
257 return b;
258 }
259 }
260
261 return ERR_PTR(-EINVAL);
262 }
263
264 /*
265 * Pinctrl_ops handling
266 */
267
rockchip_get_groups_count(struct pinctrl_dev * pctldev)268 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
269 {
270 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
271
272 return info->ngroups;
273 }
274
rockchip_get_group_name(struct pinctrl_dev * pctldev,unsigned selector)275 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev, unsigned selector)
276 {
277 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
278
279 return info->groups[selector].name;
280 }
281
rockchip_get_group_pins(struct pinctrl_dev * pctldev,unsigned selector,const unsigned ** pins,unsigned * npins)282 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, const unsigned **pins,
283 unsigned *npins)
284 {
285 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
286
287 if (selector >= info->ngroups) {
288 return -EINVAL;
289 }
290
291 *pins = info->groups[selector].pins;
292 *npins = info->groups[selector].npins;
293
294 return 0;
295 }
296
rockchip_dt_node_to_map(struct pinctrl_dev * pctldev,struct device_node * np,struct pinctrl_map ** map,unsigned * num_maps)297 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, struct device_node *np, struct pinctrl_map **map,
298 unsigned *num_maps)
299 {
300 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
301 const struct rockchip_pin_group *grp;
302 struct pinctrl_map *new_map;
303 struct device_node *parent;
304 int map_num = 1;
305 int i;
306
307 /*
308 * first find the group of this node and check if we need to create
309 * config maps for pins
310 */
311 grp = pinctrl_name_to_group(info, np->name);
312 if (!grp) {
313 dev_err(info->dev, "unable to find group for node %pOFn\n", np);
314 return -EINVAL;
315 }
316
317 map_num += grp->npins;
318
319 new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL);
320 if (!new_map) {
321 return -ENOMEM;
322 }
323
324 *map = new_map;
325 *num_maps = map_num;
326
327 /* create mux map */
328 parent = of_get_parent(np);
329 if (!parent) {
330 kfree(new_map);
331 return -EINVAL;
332 }
333 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
334 new_map[0].data.mux.function = parent->name;
335 new_map[0].data.mux.group = np->name;
336 of_node_put(parent);
337
338 /* create config map */
339 new_map++;
340 for (i = 0; i < grp->npins; i++) {
341 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
342 new_map[i].data.configs.group_or_pin = pin_get_name(pctldev, grp->pins[i]);
343 new_map[i].data.configs.configs = grp->data[i].configs;
344 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
345 }
346
347 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", (*map)->data.mux.function, (*map)->data.mux.group,
348 map_num);
349
350 return 0;
351 }
352
rockchip_dt_free_map(struct pinctrl_dev * pctldev,struct pinctrl_map * map,unsigned num_maps)353 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev, struct pinctrl_map *map, unsigned num_maps)
354 {
355 kfree(map);
356 }
357
358 static const struct pinctrl_ops rockchip_pctrl_ops = {
359 .get_groups_count = rockchip_get_groups_count,
360 .get_group_name = rockchip_get_group_name,
361 .get_group_pins = rockchip_get_group_pins,
362 .dt_node_to_map = rockchip_dt_node_to_map,
363 .dt_free_map = rockchip_dt_free_map,
364 };
365
366 /*
367 * Hardware access
368 */
369
370 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
371 {.num = PINCTRL_ROCKCHIP_ONE,
372 .pin = PINCTRL_ROCKCHIP_ZERO,
373 .reg = 0x418,
374 .bit = PINCTRL_ROCKCHIP_ZERO,
375 .mask = 0x3},
376 {.num = PINCTRL_ROCKCHIP_ONE, .pin = PINCTRL_ROCKCHIP_ONE, .reg = 0x418, .bit = PINCTRL_ROCKCHIP_TWO, .mask = 0x3},
377 {.num = PINCTRL_ROCKCHIP_ONE, .pin = PINCTRL_ROCKCHIP_TWO, .reg = 0x418, .bit = PINCTRL_ROCKCHIP_FOUR, .mask = 0x3},
378 {.num = PINCTRL_ROCKCHIP_ONE,
379 .pin = PINCTRL_ROCKCHIP_THREE,
380 .reg = 0x418,
381 .bit = PINCTRL_ROCKCHIP_SIX,
382 .mask = 0x3},
383 {.num = PINCTRL_ROCKCHIP_ONE,
384 .pin = PINCTRL_ROCKCHIP_FOUR,
385 .reg = 0x418,
386 .bit = PINCTRL_ROCKCHIP_EIGHT,
387 .mask = 0x3},
388 {.num = PINCTRL_ROCKCHIP_ONE, .pin = PINCTRL_ROCKCHIP_FIVE, .reg = 0x418, .bit = PINCTRL_ROCKCHIP_TEN, .mask = 0x3},
389 {.num = PINCTRL_ROCKCHIP_ONE,
390 .pin = PINCTRL_ROCKCHIP_SIX,
391 .reg = 0x418,
392 .bit = PINCTRL_ROCKCHIP_TWELVE,
393 .mask = 0x3},
394 {.num = PINCTRL_ROCKCHIP_ONE,
395 .pin = PINCTRL_ROCKCHIP_SEVEN,
396 .reg = 0x418,
397 .bit = PINCTRL_ROCKCHIP_FOURTEEN,
398 .mask = 0x3},
399 {.num = PINCTRL_ROCKCHIP_ONE,
400 .pin = PINCTRL_ROCKCHIP_EIGHT,
401 .reg = 0x41c,
402 .bit = PINCTRL_ROCKCHIP_ZERO,
403 .mask = 0x3},
404 {.num = PINCTRL_ROCKCHIP_ONE, .pin = PINCTRL_ROCKCHIP_NINE, .reg = 0x41c, .bit = PINCTRL_ROCKCHIP_TWO, .mask = 0x3},
405 };
406
407 static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = {
408 {.num = PINCTRL_ROCKCHIP_ZERO, .pin = 20, .reg = 0x10000, .bit = PINCTRL_ROCKCHIP_ZERO, .mask = 0xf},
409 {.num = PINCTRL_ROCKCHIP_ZERO,
410 .pin = PINCTRL_ROCKCHIP_TWENTYONE,
411 .reg = 0x10000,
412 .bit = PINCTRL_ROCKCHIP_FOUR,
413 .mask = 0xf},
414 {.num = PINCTRL_ROCKCHIP_ZERO,
415 .pin = PINCTRL_ROCKCHIP_TWENTYTWO,
416 .reg = 0x10000,
417 .bit = PINCTRL_ROCKCHIP_EIGHT,
418 .mask = 0xf},
419 {.num = PINCTRL_ROCKCHIP_ZERO,
420 .pin = PINCTRL_ROCKCHIP_TWENTYTHREE,
421 .reg = 0x10000,
422 .bit = PINCTRL_ROCKCHIP_TWELVE,
423 .mask = 0xf},
424 };
425
426 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
427 {.num = PINCTRL_ROCKCHIP_TWO, .pin = 20, .reg = 0xe8, .bit = PINCTRL_ROCKCHIP_ZERO, .mask = 0x7},
428 {.num = PINCTRL_ROCKCHIP_TWO,
429 .pin = PINCTRL_ROCKCHIP_TWENTYONE,
430 .reg = 0xe8,
431 .bit = PINCTRL_ROCKCHIP_FOUR,
432 .mask = 0x7},
433 {.num = PINCTRL_ROCKCHIP_TWO,
434 .pin = PINCTRL_ROCKCHIP_TWENTYTWO,
435 .reg = 0xe8,
436 .bit = PINCTRL_ROCKCHIP_EIGHT,
437 .mask = 0x7},
438 {.num = PINCTRL_ROCKCHIP_TWO,
439 .pin = PINCTRL_ROCKCHIP_TWENTYTHREE,
440 .reg = 0xe8,
441 .bit = PINCTRL_ROCKCHIP_TWELVE,
442 .mask = 0x7},
443 {.num = PINCTRL_ROCKCHIP_TWO,
444 .pin = PINCTRL_ROCKCHIP_TWENTYFOUR,
445 .reg = 0xd4,
446 .bit = PINCTRL_ROCKCHIP_TWELVE,
447 .mask = 0x7},
448 };
449
450 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
451 {.num = PINCTRL_ROCKCHIP_ONE,
452 .pin = PINCTRL_ROCKCHIP_FOURTEEN,
453 .reg = 0x28,
454 .bit = PINCTRL_ROCKCHIP_TWELVE,
455 .mask = 0xf},
456 {.num = PINCTRL_ROCKCHIP_ONE,
457 .pin = PINCTRL_ROCKCHIP_FIFTEEN,
458 .reg = 0x2c,
459 .bit = PINCTRL_ROCKCHIP_ZERO,
460 .mask = 0x3},
461 {.num = PINCTRL_ROCKCHIP_ONE,
462 .pin = PINCTRL_ROCKCHIP_EIGHTEEN,
463 .reg = 0x30,
464 .bit = PINCTRL_ROCKCHIP_FOUR,
465 .mask = 0xf},
466 {.num = PINCTRL_ROCKCHIP_ONE,
467 .pin = PINCTRL_ROCKCHIP_NINTEEN,
468 .reg = 0x30,
469 .bit = PINCTRL_ROCKCHIP_EIGHT,
470 .mask = 0xf},
471 {.num = PINCTRL_ROCKCHIP_ONE, .pin = 20, .reg = 0x30, .bit = PINCTRL_ROCKCHIP_TWELVE, .mask = 0xf},
472 {.num = PINCTRL_ROCKCHIP_ONE,
473 .pin = PINCTRL_ROCKCHIP_TWENTYONE,
474 .reg = 0x34,
475 .bit = PINCTRL_ROCKCHIP_ZERO,
476 .mask = 0xf},
477 {.num = PINCTRL_ROCKCHIP_ONE,
478 .pin = PINCTRL_ROCKCHIP_TWENTYTWO,
479 .reg = 0x34,
480 .bit = PINCTRL_ROCKCHIP_FOUR,
481 .mask = 0xf},
482 {.num = PINCTRL_ROCKCHIP_ONE,
483 .pin = PINCTRL_ROCKCHIP_TWENTYTHREE,
484 .reg = 0x34,
485 .bit = PINCTRL_ROCKCHIP_EIGHT,
486 .mask = 0xf},
487 {.num = PINCTRL_ROCKCHIP_THREE,
488 .pin = PINCTRL_ROCKCHIP_TWELVE,
489 .reg = 0x68,
490 .bit = PINCTRL_ROCKCHIP_EIGHT,
491 .mask = 0xf},
492 {.num = PINCTRL_ROCKCHIP_THREE,
493 .pin = PINCTRL_ROCKCHIP_THIRTEEN,
494 .reg = 0x68,
495 .bit = PINCTRL_ROCKCHIP_TWELVE,
496 .mask = 0xf},
497 {.num = PINCTRL_ROCKCHIP_TWO, .pin = PINCTRL_ROCKCHIP_TWO, .reg = 0x608, .bit = PINCTRL_ROCKCHIP_ZERO, .mask = 0x7},
498 {.num = PINCTRL_ROCKCHIP_TWO,
499 .pin = PINCTRL_ROCKCHIP_THREE,
500 .reg = 0x608,
501 .bit = PINCTRL_ROCKCHIP_FOUR,
502 .mask = 0x7},
503 {.num = PINCTRL_ROCKCHIP_TWO,
504 .pin = PINCTRL_ROCKCHIP_SIXTEEN,
505 .reg = 0x610,
506 .bit = PINCTRL_ROCKCHIP_EIGHT,
507 .mask = 0x7},
508 {.num = PINCTRL_ROCKCHIP_THREE,
509 .pin = PINCTRL_ROCKCHIP_TEN,
510 .reg = 0x610,
511 .bit = PINCTRL_ROCKCHIP_ZERO,
512 .mask = 0x7},
513 {.num = PINCTRL_ROCKCHIP_THREE,
514 .pin = PINCTRL_ROCKCHIP_ELEVEN,
515 .reg = 0x610,
516 .bit = PINCTRL_ROCKCHIP_FOUR,
517 .mask = 0x7},
518 };
519
520 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
521 {.num = PINCTRL_ROCKCHIP_TWO,
522 .pin = PINCTRL_ROCKCHIP_EIGHT,
523 .reg = 0x24,
524 .bit = PINCTRL_ROCKCHIP_ZERO,
525 .mask = 0x3},
526 {.num = PINCTRL_ROCKCHIP_TWO, .pin = PINCTRL_ROCKCHIP_NINE, .reg = 0x24, .bit = PINCTRL_ROCKCHIP_TWO, .mask = 0x3},
527 {.num = PINCTRL_ROCKCHIP_TWO, .pin = PINCTRL_ROCKCHIP_TEN, .reg = 0x24, .bit = PINCTRL_ROCKCHIP_FOUR, .mask = 0x3},
528 {.num = PINCTRL_ROCKCHIP_TWO,
529 .pin = PINCTRL_ROCKCHIP_ELEVEN,
530 .reg = 0x24,
531 .bit = PINCTRL_ROCKCHIP_SIX,
532 .mask = 0x3},
533 {.num = PINCTRL_ROCKCHIP_TWO,
534 .pin = PINCTRL_ROCKCHIP_TWELVE,
535 .reg = 0x24,
536 .bit = PINCTRL_ROCKCHIP_EIGHT,
537 .mask = 0x3},
538 {.num = PINCTRL_ROCKCHIP_TWO,
539 .pin = PINCTRL_ROCKCHIP_THIRTEEN,
540 .reg = 0x24,
541 .bit = PINCTRL_ROCKCHIP_TEN,
542 .mask = 0x3},
543 {.num = PINCTRL_ROCKCHIP_TWO,
544 .pin = PINCTRL_ROCKCHIP_FOURTEEN,
545 .reg = 0x24,
546 .bit = PINCTRL_ROCKCHIP_TWELVE,
547 .mask = 0x3},
548 {.num = PINCTRL_ROCKCHIP_TWO,
549 .pin = PINCTRL_ROCKCHIP_FIFTEEN,
550 .reg = 0x28,
551 .bit = PINCTRL_ROCKCHIP_ZERO,
552 .mask = 0x7},
553 {.num = PINCTRL_ROCKCHIP_TWO,
554 .pin = PINCTRL_ROCKCHIP_TWENTYTHREE,
555 .reg = 0x30,
556 .bit = PINCTRL_ROCKCHIP_FOURTEEN,
557 .mask = 0x3},
558 };
559
560 static struct rockchip_mux_route_data rv1126_mux_route_data[] = {
561 RK_MUXROUTE_GRF(
562 PINCTRL_ROCKCHIP_THREE, RK_PD2, PINCTRL_ROCKCHIP_ONE, 0x10260,
563 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO)), /* I2S0_MCLK_M0 */
564 RK_MUXROUTE_GRF(
565 PINCTRL_ROCKCHIP_THREE, RK_PB0, PINCTRL_ROCKCHIP_THREE, 0x10260,
566 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ONE)), /* I2S0_MCLK_M1 */
567
568 RK_MUXROUTE_GRF(
569 PINCTRL_ROCKCHIP_ZERO, RK_PD4, PINCTRL_ROCKCHIP_FOUR, 0x10260,
570 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_THREE, PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_ZERO)), /* I2S1_MCLK_M0 */
571 RK_MUXROUTE_GRF(
572 PINCTRL_ROCKCHIP_ONE, RK_PD5, PINCTRL_ROCKCHIP_TWO, 0x10260,
573 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_THREE, PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_ONE)), /* I2S1_MCLK_M1 */
574 RK_MUXROUTE_GRF(
575 PINCTRL_ROCKCHIP_TWO, RK_PC7, PINCTRL_ROCKCHIP_SIX, 0x10260,
576 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_THREE, PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_TWO)), /* I2S1_MCLK_M2 */
577
578 RK_MUXROUTE_GRF(
579 PINCTRL_ROCKCHIP_ONE, RK_PD0, PINCTRL_ROCKCHIP_ONE, 0x10260,
580 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_ZERO)), /* I2S2_MCLK_M0 */
581 RK_MUXROUTE_GRF(
582 PINCTRL_ROCKCHIP_TWO, RK_PB3, PINCTRL_ROCKCHIP_TWO, 0x10260,
583 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_ONE)), /* I2S2_MCLK_M1 */
584
585 RK_MUXROUTE_GRF(
586 PINCTRL_ROCKCHIP_THREE, RK_PD4, PINCTRL_ROCKCHIP_TWO, 0x10260,
587 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWELVE, PINCTRL_ROCKCHIP_TWELVE, PINCTRL_ROCKCHIP_ZERO)), /* PDM_CLK0_M0 */
588 RK_MUXROUTE_GRF(
589 PINCTRL_ROCKCHIP_THREE, RK_PC0, PINCTRL_ROCKCHIP_THREE, 0x10260,
590 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWELVE, PINCTRL_ROCKCHIP_TWELVE, PINCTRL_ROCKCHIP_ONE)), /* PDM_CLK0_M1 */
591
592 RK_MUXROUTE_GRF(
593 PINCTRL_ROCKCHIP_THREE, RK_PC6, PINCTRL_ROCKCHIP_ONE, 0x10264,
594 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO)), /* CIF_CLKOUT_M0 */
595 RK_MUXROUTE_GRF(
596 PINCTRL_ROCKCHIP_TWO, RK_PD1, PINCTRL_ROCKCHIP_THREE, 0x10264,
597 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ONE)), /* CIF_CLKOUT_M1 */
598
599 RK_MUXROUTE_GRF(
600 PINCTRL_ROCKCHIP_THREE, RK_PA4, PINCTRL_ROCKCHIP_FIVE, 0x10264,
601 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FIVE, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_ZERO)), /* I2C3_SCL_M0 */
602 RK_MUXROUTE_GRF(
603 PINCTRL_ROCKCHIP_TWO, RK_PD4, PINCTRL_ROCKCHIP_SEVEN, 0x10264,
604 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FIVE, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_ONE)), /* I2C3_SCL_M1 */
605 RK_MUXROUTE_GRF(
606 PINCTRL_ROCKCHIP_ONE, RK_PD6, PINCTRL_ROCKCHIP_THREE, 0x10264,
607 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FIVE, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_TWO)), /* I2C3_SCL_M2 */
608
609 RK_MUXROUTE_GRF(
610 PINCTRL_ROCKCHIP_THREE, RK_PA0, PINCTRL_ROCKCHIP_SEVEN, 0x10264,
611 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_ZERO)), /* I2C4_SCL_M0 */
612 RK_MUXROUTE_GRF(PINCTRL_ROCKCHIP_FOUR, RK_PA0, PINCTRL_ROCKCHIP_FOUR, 0x10264,
613 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_ONE)), /* I2C4_SCL_M1 */
614
615 RK_MUXROUTE_GRF(
616 PINCTRL_ROCKCHIP_TWO, RK_PA5, PINCTRL_ROCKCHIP_SEVEN, 0x10264,
617 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_NINE, PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_ZERO)), /* I2C5_SCL_M0 */
618 RK_MUXROUTE_GRF(
619 PINCTRL_ROCKCHIP_THREE, RK_PB0, PINCTRL_ROCKCHIP_FIVE, 0x10264,
620 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_NINE, PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_ONE)), /* I2C5_SCL_M1 */
621 RK_MUXROUTE_GRF(
622 PINCTRL_ROCKCHIP_ONE, RK_PD0, PINCTRL_ROCKCHIP_FOUR, 0x10264,
623 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_NINE, PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_TWO)), /* I2C5_SCL_M2 */
624
625 RK_MUXROUTE_GRF(
626 PINCTRL_ROCKCHIP_THREE, RK_PC0, PINCTRL_ROCKCHIP_FIVE, 0x10264,
627 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ELEVEN, PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_ZERO)), /* SPI1_CLK_M0 */
628 RK_MUXROUTE_GRF(
629 PINCTRL_ROCKCHIP_ONE, RK_PC6, PINCTRL_ROCKCHIP_THREE, 0x10264,
630 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ELEVEN, PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_ONE)), /* SPI1_CLK_M1 */
631 RK_MUXROUTE_GRF(
632 PINCTRL_ROCKCHIP_TWO, RK_PD5, PINCTRL_ROCKCHIP_SIX, 0x10264,
633 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ELEVEN, PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_TWO)), /* SPI1_CLK_M2 */
634
635 RK_MUXROUTE_GRF(
636 PINCTRL_ROCKCHIP_THREE, RK_PC0, PINCTRL_ROCKCHIP_TWO, 0x10264,
637 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWELVE, PINCTRL_ROCKCHIP_TWELVE, PINCTRL_ROCKCHIP_ZERO)), /* RGMII_CLK_M0 */
638 RK_MUXROUTE_GRF(
639 PINCTRL_ROCKCHIP_TWO, RK_PB7, PINCTRL_ROCKCHIP_TWO, 0x10264,
640 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWELVE, PINCTRL_ROCKCHIP_TWELVE, PINCTRL_ROCKCHIP_ONE)), /* RGMII_CLK_M1 */
641
642 RK_MUXROUTE_GRF(
643 PINCTRL_ROCKCHIP_THREE, RK_PA1, PINCTRL_ROCKCHIP_THREE, 0x10264,
644 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_THIRTEEN, PINCTRL_ROCKCHIP_THIRTEEN, PINCTRL_ROCKCHIP_ZERO)), /* CAN_TXD_M0 */
645 RK_MUXROUTE_GRF(
646 PINCTRL_ROCKCHIP_THREE, RK_PA7, PINCTRL_ROCKCHIP_FIVE, 0x10264,
647 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_THIRTEEN, PINCTRL_ROCKCHIP_THIRTEEN, PINCTRL_ROCKCHIP_ONE)), /* CAN_TXD_M1 */
648
649 RK_MUXROUTE_GRF(PINCTRL_ROCKCHIP_THREE, RK_PA4, PINCTRL_ROCKCHIP_SIX, 0x10268,
650 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO)), /* PWM8_M0 */
651 RK_MUXROUTE_GRF(PINCTRL_ROCKCHIP_TWO, RK_PD7, PINCTRL_ROCKCHIP_FIVE, 0x10268,
652 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ONE)), /* PWM8_M1 */
653
654 RK_MUXROUTE_GRF(PINCTRL_ROCKCHIP_THREE, RK_PA5, PINCTRL_ROCKCHIP_SIX, 0x10268,
655 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_ZERO)), /* PWM9_M0 */
656 RK_MUXROUTE_GRF(PINCTRL_ROCKCHIP_TWO, RK_PD6, PINCTRL_ROCKCHIP_FIVE, 0x10268,
657 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_ONE)), /* PWM9_M1 */
658
659 RK_MUXROUTE_GRF(PINCTRL_ROCKCHIP_THREE, RK_PA6, PINCTRL_ROCKCHIP_SIX, 0x10268,
660 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_ZERO)), /* PWM10_M0 */
661 RK_MUXROUTE_GRF(PINCTRL_ROCKCHIP_TWO, RK_PD5, PINCTRL_ROCKCHIP_FIVE, 0x10268,
662 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_ONE)), /* PWM10_M1 */
663
664 RK_MUXROUTE_GRF(
665 PINCTRL_ROCKCHIP_THREE, RK_PA7, PINCTRL_ROCKCHIP_SIX, 0x10268,
666 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_ZERO)), /* PWM11_IR_M0 */
667 RK_MUXROUTE_GRF(PINCTRL_ROCKCHIP_THREE, RK_PA1, PINCTRL_ROCKCHIP_FIVE, 0x10268,
668 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_ONE)), /* PWM11_IR_M1 */
669
670 RK_MUXROUTE_GRF(
671 PINCTRL_ROCKCHIP_ONE, RK_PA5, PINCTRL_ROCKCHIP_THREE, 0x10268,
672 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_ZERO)), /* UART2_TX_M0 */
673 RK_MUXROUTE_GRF(
674 PINCTRL_ROCKCHIP_THREE, RK_PA2, PINCTRL_ROCKCHIP_ONE, 0x10268,
675 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_ONE)), /* UART2_TX_M1 */
676
677 RK_MUXROUTE_GRF(
678 PINCTRL_ROCKCHIP_THREE, RK_PC6, PINCTRL_ROCKCHIP_THREE, 0x10268,
679 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ELEVEN, PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_ZERO)), /* UART3_TX_M0 */
680 RK_MUXROUTE_GRF(
681 PINCTRL_ROCKCHIP_ONE, RK_PA7, PINCTRL_ROCKCHIP_TWO, 0x10268,
682 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ELEVEN, PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_ONE)), /* UART3_TX_M1 */
683 RK_MUXROUTE_GRF(
684 PINCTRL_ROCKCHIP_THREE, RK_PA0, PINCTRL_ROCKCHIP_FOUR, 0x10268,
685 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ELEVEN, PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_TWO)), /* UART3_TX_M2 */
686
687 RK_MUXROUTE_GRF(
688 PINCTRL_ROCKCHIP_THREE, RK_PA4, PINCTRL_ROCKCHIP_FOUR, 0x10268,
689 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_THIRTEEN, PINCTRL_ROCKCHIP_TWELVE, PINCTRL_ROCKCHIP_ZERO)), /* UART4_TX_M0 */
690 RK_MUXROUTE_GRF(
691 PINCTRL_ROCKCHIP_TWO, RK_PA6, PINCTRL_ROCKCHIP_FOUR, 0x10268,
692 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_THIRTEEN, PINCTRL_ROCKCHIP_TWELVE, PINCTRL_ROCKCHIP_ONE)), /* UART4_TX_M1 */
693 RK_MUXROUTE_GRF(
694 PINCTRL_ROCKCHIP_ONE, RK_PD5, PINCTRL_ROCKCHIP_THREE, 0x10268,
695 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_THIRTEEN, PINCTRL_ROCKCHIP_TWELVE, PINCTRL_ROCKCHIP_TWO)), /* UART4_TX_M2 */
696
697 RK_MUXROUTE_GRF(
698 PINCTRL_ROCKCHIP_THREE, RK_PA6, PINCTRL_ROCKCHIP_FOUR, 0x10268,
699 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FIFTEEN, PINCTRL_ROCKCHIP_FOURTEEN, PINCTRL_ROCKCHIP_ZERO)), /* UART5_TX_M0 */
700 RK_MUXROUTE_GRF(
701 PINCTRL_ROCKCHIP_TWO, RK_PB0, PINCTRL_ROCKCHIP_FOUR, 0x10268,
702 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FIFTEEN, PINCTRL_ROCKCHIP_FOURTEEN, PINCTRL_ROCKCHIP_ONE)), /* UART5_TX_M1 */
703 RK_MUXROUTE_GRF(
704 PINCTRL_ROCKCHIP_TWO, RK_PA0, PINCTRL_ROCKCHIP_THREE, 0x10268,
705 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FIFTEEN, PINCTRL_ROCKCHIP_FOURTEEN, PINCTRL_ROCKCHIP_TWO)), /* UART5_TX_M2 */
706
707 RK_MUXROUTE_PMU(PINCTRL_ROCKCHIP_ZERO, RK_PB6, PINCTRL_ROCKCHIP_THREE, 0x0114,
708 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO)), /* PWM0_M0 */
709 RK_MUXROUTE_PMU(PINCTRL_ROCKCHIP_TWO, RK_PB3, PINCTRL_ROCKCHIP_FIVE, 0x0114,
710 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ONE)), /* PWM0_M1 */
711
712 RK_MUXROUTE_PMU(PINCTRL_ROCKCHIP_ZERO, RK_PB7, PINCTRL_ROCKCHIP_THREE, 0x0114,
713 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_ZERO)), /* PWM1_M0 */
714 RK_MUXROUTE_PMU(PINCTRL_ROCKCHIP_TWO, RK_PB2, PINCTRL_ROCKCHIP_FIVE, 0x0114,
715 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_ONE)), /* PWM1_M1 */
716
717 RK_MUXROUTE_PMU(PINCTRL_ROCKCHIP_ZERO, RK_PC0, PINCTRL_ROCKCHIP_THREE, 0x0114,
718 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_ZERO)), /* PWM2_M0 */
719 RK_MUXROUTE_PMU(PINCTRL_ROCKCHIP_TWO, RK_PB1, PINCTRL_ROCKCHIP_FIVE, 0x0114,
720 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_ONE)), /* PWM2_M1 */
721
722 RK_MUXROUTE_PMU(PINCTRL_ROCKCHIP_ZERO, RK_PC1, PINCTRL_ROCKCHIP_THREE, 0x0114,
723 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_ZERO)), /* PWM3_IR_M0 */
724 RK_MUXROUTE_PMU(PINCTRL_ROCKCHIP_TWO, RK_PB0, PINCTRL_ROCKCHIP_FIVE, 0x0114,
725 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_ONE)), /* PWM3_IR_M1 */
726
727 RK_MUXROUTE_PMU(
728 PINCTRL_ROCKCHIP_ZERO, RK_PC2, PINCTRL_ROCKCHIP_THREE, 0x0114,
729 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_ZERO)), /* PWM4_M0 */
730 RK_MUXROUTE_PMU(PINCTRL_ROCKCHIP_TWO, RK_PA7, PINCTRL_ROCKCHIP_FIVE, 0x0114,
731 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_ONE)), /* PWM4_M1 */
732
733 RK_MUXROUTE_PMU(PINCTRL_ROCKCHIP_ZERO, RK_PC3, PINCTRL_ROCKCHIP_THREE, 0x0114,
734 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_ZERO)), /* PWM5_M0 */
735 RK_MUXROUTE_PMU(PINCTRL_ROCKCHIP_TWO, RK_PA6, PINCTRL_ROCKCHIP_FIVE, 0x0114,
736 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_ONE)), /* PWM5_M1 */
737
738 RK_MUXROUTE_PMU(
739 PINCTRL_ROCKCHIP_ZERO, RK_PB2, PINCTRL_ROCKCHIP_THREE, 0x0114,
740 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWELVE, PINCTRL_ROCKCHIP_TWELVE, PINCTRL_ROCKCHIP_ZERO)), /* PWM6_M0 */
741 RK_MUXROUTE_PMU(
742 PINCTRL_ROCKCHIP_TWO, RK_PD4, PINCTRL_ROCKCHIP_FIVE, 0x0114,
743 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWELVE, PINCTRL_ROCKCHIP_TWELVE, PINCTRL_ROCKCHIP_ONE)), /* PWM6_M1 */
744
745 RK_MUXROUTE_PMU(
746 PINCTRL_ROCKCHIP_ZERO, RK_PB1, PINCTRL_ROCKCHIP_THREE, 0x0114,
747 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FOURTEEN, PINCTRL_ROCKCHIP_FOURTEEN, PINCTRL_ROCKCHIP_ZERO)), /* PWM7_IR_M0 */
748 RK_MUXROUTE_PMU(
749 PINCTRL_ROCKCHIP_THREE, RK_PA0, PINCTRL_ROCKCHIP_FIVE, 0x0114,
750 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FOURTEEN, PINCTRL_ROCKCHIP_FOURTEEN, PINCTRL_ROCKCHIP_ONE)), /* PWM7_IR_M1 */
751
752 RK_MUXROUTE_PMU(
753 PINCTRL_ROCKCHIP_ZERO, RK_PB0, PINCTRL_ROCKCHIP_ONE, 0x0118,
754 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ONE, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO)), /* SPI0_CLK_M0 */
755 RK_MUXROUTE_PMU(
756 PINCTRL_ROCKCHIP_TWO, RK_PA1, PINCTRL_ROCKCHIP_ONE, 0x0118,
757 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ONE, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ONE)), /* SPI0_CLK_M1 */
758 RK_MUXROUTE_PMU(
759 PINCTRL_ROCKCHIP_TWO, RK_PB2, PINCTRL_ROCKCHIP_SIX, 0x0118,
760 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ONE, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_TWO)), /* SPI0_CLK_M2 */
761
762 RK_MUXROUTE_PMU(
763 PINCTRL_ROCKCHIP_ZERO, RK_PB6, PINCTRL_ROCKCHIP_TWO, 0x0118,
764 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_ZERO)), /* UART1_TX_M0 */
765 RK_MUXROUTE_PMU(PINCTRL_ROCKCHIP_ONE, RK_PD0, PINCTRL_ROCKCHIP_FIVE, 0x0118,
766 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_ONE)), /* UART1_TX_M1 */
767 };
768
rockchip_get_recalced_mux(struct rockchip_pin_bank * bank,int pin,int * reg,u8 * bit,int * mask)769 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, int *reg, u8 *bit, int *mask)
770 {
771 struct rockchip_pinctrl *info = bank->drvdata;
772 struct rockchip_pin_ctrl *ctrl = info->ctrl;
773 struct rockchip_mux_recalced_data *data;
774 int i;
775
776 for (i = 0; i < ctrl->niomux_recalced; i++) {
777 data = &ctrl->iomux_recalced[i];
778 if (data->num == bank->bank_num && data->pin == pin) {
779 break;
780 }
781 }
782
783 if (i >= ctrl->niomux_recalced) {
784 return;
785 }
786
787 *reg = data->reg;
788 *mask = data->mask;
789 *bit = data->bit;
790 }
791
792 static struct rockchip_mux_route_data rk1808_mux_route_data[] = {
793 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_THREE, RK_PB4, PINCTRL_ROCKCHIP_TWO, 0x190,
794 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_THREE)), /* i2c2m0_sda */
795 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ONE, RK_PB5, PINCTRL_ROCKCHIP_TWO, 0x190,
796 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_THREE) |
797 BIT(PINCTRL_ROCKCHIP_THREE)), /* i2c2m1_sda */
798 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ONE, RK_PA6, PINCTRL_ROCKCHIP_TWO, 0x190,
799 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_FOUR)), /* spi2m0_miso */
800 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_TWO, RK_PA4, PINCTRL_ROCKCHIP_THREE, 0x190,
801 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_FOUR) |
802 BIT(PINCTRL_ROCKCHIP_FOUR)), /* spi2m1_miso */
803 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_FOUR, RK_PB7, PINCTRL_ROCKCHIP_TWO, 0x190,
804 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_FIVE)), /* spi1m0_miso */
805 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_THREE, RK_PD2, PINCTRL_ROCKCHIP_THREE, 0x190,
806 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_FIVE) |
807 BIT(PINCTRL_ROCKCHIP_FIVE)), /* spi1m1_miso */
808 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_FOUR, RK_PB0, PINCTRL_ROCKCHIP_TWO, 0x190,
809 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_THIRTEEN)), /* uart1_rxm0 */
810 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ONE, RK_PB4, PINCTRL_ROCKCHIP_THREE, 0x190,
811 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_THIRTEEN) |
812 BIT(PINCTRL_ROCKCHIP_THIRTEEN)), /* uart1_rxm1 */
813 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_FOUR, RK_PA3, PINCTRL_ROCKCHIP_TWO, 0x190,
814 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_FOURTEEN) |
815 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_FIFTEEN)), /* uart2_rxm0 */
816 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_TWO, RK_PD1, PINCTRL_ROCKCHIP_TWO, 0x190,
817 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_FOURTEEN) |
818 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_FIFTEEN) |
819 BIT(PINCTRL_ROCKCHIP_FOURTEEN)), /* uart2_rxm1 */
820 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_THREE, RK_PA4, PINCTRL_ROCKCHIP_TWO, 0x190,
821 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_FOURTEEN) |
822 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_FIFTEEN) |
823 BIT(PINCTRL_ROCKCHIP_FIFTEEN)), /* uart2_rxm2 */
824 };
825
826 static struct rockchip_mux_route_data px30_mux_route_data[] = {
827 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_TWO, RK_PA0, PINCTRL_ROCKCHIP_ONE, 0x184,
828 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_SEVEN)), /* cif-d2m0 */
829 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_THREE, RK_PA3, PINCTRL_ROCKCHIP_THREE, 0x184,
830 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_SEVEN) |
831 BIT(PINCTRL_ROCKCHIP_SEVEN)), /* cif-d2m1 */
832 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_THREE, RK_PC6, PINCTRL_ROCKCHIP_TWO, 0x184,
833 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_EIGHT)), /* pdm-m0 */
834 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_TWO, RK_PC6, PINCTRL_ROCKCHIP_ONE, 0x184,
835 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_EIGHT) | BIT(PINCTRL_ROCKCHIP_EIGHT)), /* pdm-m1 */
836 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ONE, RK_PD3, PINCTRL_ROCKCHIP_TWO, 0x184,
837 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_TEN)), /* uart2-rxm0 */
838 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_TWO, RK_PB6, PINCTRL_ROCKCHIP_TWO, 0x184,
839 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_TEN) | BIT(PINCTRL_ROCKCHIP_TEN)), /* uart2-rxm1 */
840 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ZERO, RK_PC1, PINCTRL_ROCKCHIP_TWO, 0x184,
841 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_NINE)), /* uart3-rxm0 */
842 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ONE, RK_PB7, PINCTRL_ROCKCHIP_TWO, 0x184,
843 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_NINE) |
844 BIT(PINCTRL_ROCKCHIP_NINE)), /* uart3-rxm1 */
845 };
846
847 static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
848 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ONE, RK_PB2, PINCTRL_ROCKCHIP_ONE, 0x144,
849 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_THREE) |
850 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_FOUR)), /* spi-0 */
851 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ONE, RK_PD3, PINCTRL_ROCKCHIP_THREE, 0x144,
852 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_THREE) |
853 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_FOUR) |
854 BIT(PINCTRL_ROCKCHIP_THREE)), /* spi-1 */
855 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ZERO, RK_PB5, PINCTRL_ROCKCHIP_TWO, 0x144,
856 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_THREE) |
857 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_FOUR) |
858 BIT(PINCTRL_ROCKCHIP_FOUR)), /* spi-2 */
859 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ONE, RK_PA5, PINCTRL_ROCKCHIP_ONE, 0x144,
860 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_FIVE)), /* i2s-0 */
861 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ZERO, RK_PB6, PINCTRL_ROCKCHIP_ONE, 0x144,
862 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_FIVE) | BIT(PINCTRL_ROCKCHIP_FIVE)), /* i2s-1 */
863 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ONE, RK_PC6, PINCTRL_ROCKCHIP_TWO, 0x144,
864 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_SIX)), /* emmc-0 */
865 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_TWO, RK_PA4, PINCTRL_ROCKCHIP_TWO, 0x144,
866 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_SIX) | BIT(PINCTRL_ROCKCHIP_SIX)), /* emmc-1 */
867 };
868
869 static struct rockchip_mux_route_data rk3188_mux_route_data[] = {
870 RK_MUXROUTE_SAME(
871 PINCTRL_ROCKCHIP_ZERO, RK_PD0, PINCTRL_ROCKCHIP_ONE, 0xa0,
872 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_ELEVEN)), /* non-iomuxed emmc/flash pins on flash-dqs */
873 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ZERO, RK_PD0, PINCTRL_ROCKCHIP_TWO, 0xa0,
874 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_ELEVEN) |
875 BIT(PINCTRL_ROCKCHIP_ELEVEN)), /* non-iomuxed emmc/flash pins on emmc-clk */
876 };
877
878 static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
879 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ZERO, RK_PD2, PINCTRL_ROCKCHIP_ONE, 0x50,
880 BIT(PINCTRL_ROCKCHIP_SIXTEEN)), /* pwm0-0 */
881 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_THREE, RK_PC5, PINCTRL_ROCKCHIP_ONE, 0x50,
882 BIT(PINCTRL_ROCKCHIP_SIXTEEN) | BIT(PINCTRL_ROCKCHIP_ZERO)), /* pwm0-1 */
883 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ZERO, RK_PD3, PINCTRL_ROCKCHIP_ONE, 0x50,
884 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_ONE)), /* pwm1-0 */
885 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ZERO, RK_PD6, PINCTRL_ROCKCHIP_TWO, 0x50,
886 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_ONE) | BIT(PINCTRL_ROCKCHIP_ONE)), /* pwm1-1 */
887 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ZERO, RK_PD4, PINCTRL_ROCKCHIP_ONE, 0x50,
888 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_TWO)), /* pwm2-0 */
889 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ONE, RK_PB4, PINCTRL_ROCKCHIP_TWO, 0x50,
890 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_TWO) | BIT(PINCTRL_ROCKCHIP_TWO)), /* pwm2-1 */
891 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_THREE, RK_PD2, PINCTRL_ROCKCHIP_ONE, 0x50,
892 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_THREE)), /* pwm3-0 */
893 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ONE, RK_PB3, PINCTRL_ROCKCHIP_TWO, 0x50,
894 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_THREE) | BIT(PINCTRL_ROCKCHIP_THREE)), /* pwm3-1 */
895 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ONE, RK_PA1, PINCTRL_ROCKCHIP_ONE, 0x50,
896 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_FOUR)), /* sdio-0_d0 */
897 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_THREE, RK_PA2, PINCTRL_ROCKCHIP_ONE, 0x50,
898 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_FOUR) |
899 BIT(PINCTRL_ROCKCHIP_FOUR)), /* sdio-1_d0 */
900 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ZERO, RK_PB5, PINCTRL_ROCKCHIP_TWO, 0x50,
901 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_FIVE)), /* spi-0_rx */
902 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_TWO, RK_PA0, PINCTRL_ROCKCHIP_TWO, 0x50,
903 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_FIVE) | BIT(PINCTRL_ROCKCHIP_FIVE)), /* spi-1_rx */
904 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ONE, RK_PC6, PINCTRL_ROCKCHIP_TWO, 0x50,
905 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_SEVEN)), /* emmc-0_cmd */
906 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_TWO, RK_PA4, PINCTRL_ROCKCHIP_TWO, 0x50,
907 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_SEVEN) |
908 BIT(PINCTRL_ROCKCHIP_SEVEN)), /* emmc-1_cmd */
909 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ONE, RK_PC3, PINCTRL_ROCKCHIP_TWO, 0x50,
910 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_EIGHT)), /* uart2-0_rx */
911 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ONE, RK_PB2, PINCTRL_ROCKCHIP_TWO, 0x50,
912 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_EIGHT) |
913 BIT(PINCTRL_ROCKCHIP_EIGHT)), /* uart2-1_rx */
914 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ONE, RK_PB2, PINCTRL_ROCKCHIP_ONE, 0x50,
915 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_ELEVEN)), /* uart1-0_rx */
916 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_THREE, RK_PB5, PINCTRL_ROCKCHIP_ONE, 0x50,
917 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_ELEVEN) |
918 BIT(PINCTRL_ROCKCHIP_ELEVEN)), /* uart1-1_rx */
919 };
920
921 static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
922 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_SEVEN, RK_PC0, PINCTRL_ROCKCHIP_TWO, 0x264,
923 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_TWELVE) |
924 BIT(PINCTRL_ROCKCHIP_TWELVE)), /* edphdmi_cecinoutt1 */
925 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_SEVEN, RK_PC7, PINCTRL_ROCKCHIP_FOUR, 0x264,
926 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_TWELVE)), /* edphdmi_cecinout */
927 };
928
929 static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
930 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ZERO, RK_PC3, PINCTRL_ROCKCHIP_ONE, 0x314,
931 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_ZERO) | BIT(PINCTRL_ROCKCHIP_ZERO)), /* rtc_clk */
932 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ONE, RK_PC6, PINCTRL_ROCKCHIP_TWO, 0x314,
933 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_TWO) |
934 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_THREE)), /* uart2_rxm0 */
935 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_FOUR, RK_PD2, PINCTRL_ROCKCHIP_TWO, 0x314,
936 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_TWO) |
937 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_THREE) |
938 BIT(PINCTRL_ROCKCHIP_TWO)), /* uart2_rxm1 */
939 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ZERO, RK_PB7, PINCTRL_ROCKCHIP_TWO, 0x608,
940 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_EIGHT) |
941 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_NINE)), /* i2c3_sdam0 */
942 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_THREE, RK_PB4, PINCTRL_ROCKCHIP_TWO, 0x608,
943 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_EIGHT) |
944 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_NINE) |
945 BIT(PINCTRL_ROCKCHIP_EIGHT)), /* i2c3_sdam1 */
946 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_TWO, RK_PA0, PINCTRL_ROCKCHIP_THREE, 0x608,
947 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_EIGHT) |
948 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_NINE) |
949 BIT(PINCTRL_ROCKCHIP_NINE)), /* i2c3_sdam2 */
950 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ONE, RK_PA3, PINCTRL_ROCKCHIP_TWO, 0x308,
951 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_THREE)), /* i2s-8ch-1-sclktxm0 */
952 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ONE, RK_PA4, PINCTRL_ROCKCHIP_TWO, 0x308,
953 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_THREE)), /* i2s-8ch-1-sclkrxm0 */
954 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ONE, RK_PB5, PINCTRL_ROCKCHIP_TWO, 0x308,
955 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_THREE) |
956 BIT(PINCTRL_ROCKCHIP_THREE)), /* i2s-8ch-1-sclktxm1 */
957 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ONE, RK_PB6, PINCTRL_ROCKCHIP_TWO, 0x308,
958 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_THREE) |
959 BIT(PINCTRL_ROCKCHIP_THREE)), /* i2s-8ch-1-sclkrxm1 */
960 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ONE, RK_PA4, PINCTRL_ROCKCHIP_THREE, 0x308,
961 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_TWELVE) |
962 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_THIRTEEN)), /* pdm-clkm0 */
963 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ONE, RK_PB6, PINCTRL_ROCKCHIP_FOUR, 0x308,
964 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_TWELVE) |
965 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_THIRTEEN) |
966 BIT(PINCTRL_ROCKCHIP_TWELVE)), /* pdm-clkm1 */
967 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_TWO, RK_PA6, PINCTRL_ROCKCHIP_TWO, 0x308,
968 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_TWELVE) |
969 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_THIRTEEN) |
970 BIT(PINCTRL_ROCKCHIP_THIRTEEN)), /* pdm-clkm2 */
971 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_TWO, RK_PA4, PINCTRL_ROCKCHIP_THREE, 0x600,
972 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_TWO) |
973 BIT(PINCTRL_ROCKCHIP_TWO)), /* pdm-clkm-m2 */
974 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_THREE, RK_PB2, PINCTRL_ROCKCHIP_THREE, 0x314,
975 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_NINE)), /* spi1_miso */
976 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_TWO, RK_PA4, PINCTRL_ROCKCHIP_TWO, 0x314,
977 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_NINE) |
978 BIT(PINCTRL_ROCKCHIP_NINE)), /* spi1_miso_m1 */
979 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ZERO, RK_PB3, PINCTRL_ROCKCHIP_THREE, 0x314,
980 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_TEN) |
981 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_ELEVEN)), /* owire_m0 */
982 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ONE, RK_PC6, PINCTRL_ROCKCHIP_SEVEN, 0x314,
983 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_TEN) |
984 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_ELEVEN) |
985 BIT(PINCTRL_ROCKCHIP_TEN)), /* owire_m1 */
986 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_TWO, RK_PA2, PINCTRL_ROCKCHIP_FIVE, 0x314,
987 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_TEN) |
988 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_ELEVEN) |
989 BIT(PINCTRL_ROCKCHIP_ELEVEN)), /* owire_m2 */
990 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ZERO, RK_PB3, PINCTRL_ROCKCHIP_TWO, 0x314,
991 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_TWELVE) |
992 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_THIRTEEN)), /* can_rxd_m0 */
993 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ONE, RK_PC6, PINCTRL_ROCKCHIP_FIVE, 0x314,
994 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_TWELVE) |
995 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_THIRTEEN) |
996 BIT(PINCTRL_ROCKCHIP_TWELVE)), /* can_rxd_m1 */
997 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_TWO, RK_PA2, PINCTRL_ROCKCHIP_FOUR, 0x314,
998 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_TWELVE) |
999 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_THIRTEEN) |
1000 BIT(PINCTRL_ROCKCHIP_THIRTEEN)), /* can_rxd_m2 */
1001 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ONE, RK_PC4, PINCTRL_ROCKCHIP_THREE, 0x314,
1002 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_FOURTEEN)), /* mac_rxd0_m0 */
1003 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_FOUR, RK_PA2, PINCTRL_ROCKCHIP_TWO, 0x314,
1004 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_FOURTEEN) |
1005 BIT(PINCTRL_ROCKCHIP_FOURTEEN)), /* mac_rxd0_m1 */
1006 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_THREE, RK_PB4, PINCTRL_ROCKCHIP_FOUR, 0x314,
1007 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_FIFTEEN)), /* uart3_rx */
1008 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ZERO, RK_PC1, PINCTRL_ROCKCHIP_THREE, 0x314,
1009 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_FIFTEEN) |
1010 BIT(PINCTRL_ROCKCHIP_FIFTEEN)), /* uart3_rx_m1 */
1011 };
1012
1013 static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
1014 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ONE, RK_PA1, PINCTRL_ROCKCHIP_TWO, 0x50,
1015 BIT(PINCTRL_ROCKCHIP_SIXTEEN) |
1016 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_ONE)), /* uart2dbg_rxm0 */
1017 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_TWO, RK_PA1, PINCTRL_ROCKCHIP_ONE, 0x50,
1018 BIT(PINCTRL_ROCKCHIP_SIXTEEN) | BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_ONE) |
1019 BIT(PINCTRL_ROCKCHIP_ZERO)), /* uart2dbg_rxm1 */
1020 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ONE, RK_PB3, PINCTRL_ROCKCHIP_TWO, 0x50,
1021 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_TWO) |
1022 BIT(PINCTRL_ROCKCHIP_TWO)), /* gmac-m1_rxd0 */
1023 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ONE, RK_PB6, PINCTRL_ROCKCHIP_TWO, 0x50,
1024 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_TEN) |
1025 BIT(PINCTRL_ROCKCHIP_TEN)), /* gmac-m1-optimized_rxd3 */
1026 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_TWO, RK_PC3, PINCTRL_ROCKCHIP_TWO, 0x50,
1027 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_THREE)), /* pdm_sdi0m0 */
1028 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ONE, RK_PC7, PINCTRL_ROCKCHIP_THREE, 0x50,
1029 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_THREE) |
1030 BIT(PINCTRL_ROCKCHIP_THREE)), /* pdm_sdi0m1 */
1031 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_THREE, RK_PA2, PINCTRL_ROCKCHIP_FOUR, 0x50,
1032 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_FOUR) |
1033 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_FIVE) |
1034 BIT(PINCTRL_ROCKCHIP_FIVE)), /* spi_rxdm2 */
1035 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_ONE, RK_PD0, PINCTRL_ROCKCHIP_ONE, 0x50,
1036 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_SIX)), /* i2s2_sdim0 */
1037 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_THREE, RK_PA2, PINCTRL_ROCKCHIP_SIX, 0x50,
1038 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_SIX) | BIT(PINCTRL_ROCKCHIP_SIX)), /* i2s2_sdim1 */
1039 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_TWO, RK_PC6, PINCTRL_ROCKCHIP_THREE, 0x50,
1040 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_SEVEN) |
1041 BIT(PINCTRL_ROCKCHIP_SEVEN)), /* card_iom1 */
1042 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_TWO, RK_PC0, PINCTRL_ROCKCHIP_THREE, 0x50,
1043 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_EIGHT) |
1044 BIT(PINCTRL_ROCKCHIP_EIGHT)), /* tsp_d5m1 */
1045 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_TWO, RK_PC0, PINCTRL_ROCKCHIP_FOUR, 0x50,
1046 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_NINE) |
1047 BIT(PINCTRL_ROCKCHIP_NINE)), /* cif_data5m1 */
1048 };
1049
1050 static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
1051 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_FOUR, RK_PB0, PINCTRL_ROCKCHIP_TWO, 0xe21c,
1052 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_TEN) |
1053 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_ELEVEN)), /* uart2dbga_rx */
1054 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_FOUR, RK_PC0, PINCTRL_ROCKCHIP_TWO, 0xe21c,
1055 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_TEN) |
1056 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_ELEVEN) |
1057 BIT(PINCTRL_ROCKCHIP_TEN)), /* uart2dbgb_rx */
1058 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_FOUR, RK_PC3, PINCTRL_ROCKCHIP_ONE, 0xe21c,
1059 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_TEN) |
1060 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_ELEVEN) |
1061 BIT(PINCTRL_ROCKCHIP_ELEVEN)), /* uart2dbgc_rx */
1062 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_TWO, RK_PD2, PINCTRL_ROCKCHIP_TWO, 0xe21c,
1063 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_FOURTEEN)), /* pcie_clkreqn */
1064 RK_MUXROUTE_SAME(PINCTRL_ROCKCHIP_FOUR, RK_PD0, PINCTRL_ROCKCHIP_ONE, 0xe21c,
1065 BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_FOURTEEN) |
1066 BIT(PINCTRL_ROCKCHIP_FOURTEEN)), /* pcie_clkreqnb */
1067 };
1068
1069 static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
1070 RK_MUXROUTE_PMU(
1071 PINCTRL_ROCKCHIP_ZERO, RK_PB7, PINCTRL_ROCKCHIP_ONE, 0x0110,
1072 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ONE, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO)), /* PWM0 IO mux M0 */
1073 RK_MUXROUTE_PMU(
1074 PINCTRL_ROCKCHIP_ZERO, RK_PC7, PINCTRL_ROCKCHIP_TWO, 0x0110,
1075 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ONE, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ONE)), /* PWM0 IO mux M1 */
1076 RK_MUXROUTE_PMU(
1077 PINCTRL_ROCKCHIP_ZERO, RK_PC0, PINCTRL_ROCKCHIP_ONE, 0x0110,
1078 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_THREE, PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_ZERO)), /* PWM1 IO mux M0 */
1079 RK_MUXROUTE_PMU(
1080 PINCTRL_ROCKCHIP_ZERO, RK_PB5, PINCTRL_ROCKCHIP_FOUR, 0x0110,
1081 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_THREE, PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_ONE)), /* PWM1 IO mux M1 */
1082 RK_MUXROUTE_PMU(
1083 PINCTRL_ROCKCHIP_ZERO, RK_PC1, PINCTRL_ROCKCHIP_ONE, 0x0110,
1084 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FIVE, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_ZERO)), /* PWM2 IO mux M0 */
1085 RK_MUXROUTE_PMU(
1086 PINCTRL_ROCKCHIP_ZERO, RK_PB6, PINCTRL_ROCKCHIP_FOUR, 0x0110,
1087 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FIVE, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_ONE)), /* PWM2 IO mux M1 */
1088 RK_MUXROUTE_PMU(
1089 PINCTRL_ROCKCHIP_ZERO, RK_PB3, PINCTRL_ROCKCHIP_TWO, 0x0300,
1090 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO)), /* CAN0 IO mux M0 */
1091 RK_MUXROUTE_GRF(
1092 PINCTRL_ROCKCHIP_TWO, RK_PA1, PINCTRL_ROCKCHIP_FOUR, 0x0300,
1093 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ONE)), /* CAN0 IO mux M1 */
1094 RK_MUXROUTE_GRF(
1095 PINCTRL_ROCKCHIP_ONE, RK_PA1, PINCTRL_ROCKCHIP_THREE, 0x0300,
1096 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_ZERO)), /* CAN1 IO mux M0 */
1097 RK_MUXROUTE_GRF(
1098 PINCTRL_ROCKCHIP_FOUR, RK_PC3, PINCTRL_ROCKCHIP_THREE, 0x0300,
1099 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_ONE)), /* CAN1 IO mux M1 */
1100 RK_MUXROUTE_GRF(
1101 PINCTRL_ROCKCHIP_FOUR, RK_PB5, PINCTRL_ROCKCHIP_THREE, 0x0300,
1102 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_ZERO)), /* CAN2 IO mux M0 */
1103 RK_MUXROUTE_GRF(
1104 PINCTRL_ROCKCHIP_TWO, RK_PB2, PINCTRL_ROCKCHIP_FOUR, 0x0300,
1105 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_ONE)), /* CAN2 IO mux M1 */
1106 RK_MUXROUTE_GRF(
1107 PINCTRL_ROCKCHIP_FOUR, RK_PC4, PINCTRL_ROCKCHIP_ONE, 0x0300,
1108 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_ZERO)), /* HPDIN IO mux M0 */
1109 RK_MUXROUTE_PMU(
1110 PINCTRL_ROCKCHIP_ZERO, RK_PC2, PINCTRL_ROCKCHIP_TWO, 0x0300,
1111 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_ONE)), /* HPDIN IO mux M1 */
1112 RK_MUXROUTE_GRF(
1113 PINCTRL_ROCKCHIP_THREE, RK_PB1, PINCTRL_ROCKCHIP_THREE, 0x0300,
1114 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_ZERO)), /* GMAC1 IO mux M0 */
1115 RK_MUXROUTE_GRF(
1116 PINCTRL_ROCKCHIP_FOUR, RK_PA7, PINCTRL_ROCKCHIP_THREE, 0x0300,
1117 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_ONE)), /* GMAC1 IO mux M1 */
1118 RK_MUXROUTE_GRF(
1119 PINCTRL_ROCKCHIP_FOUR, RK_PD1, PINCTRL_ROCKCHIP_ONE, 0x0300,
1120 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_ZERO)), /* HDMITX IO mux M0 */
1121 RK_MUXROUTE_PMU(
1122 PINCTRL_ROCKCHIP_ZERO, RK_PC7, PINCTRL_ROCKCHIP_ONE, 0x0300,
1123 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_ONE)), /* HDMITX IO mux M1 */
1124 RK_MUXROUTE_PMU(PINCTRL_ROCKCHIP_ZERO, RK_PB6, PINCTRL_ROCKCHIP_ONE, 0x0300,
1125 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FOURTEEN, PINCTRL_ROCKCHIP_FOURTEEN,
1126 PINCTRL_ROCKCHIP_ZERO)), /* I2C2 IO mux M0 */
1127 RK_MUXROUTE_GRF(PINCTRL_ROCKCHIP_FOUR, RK_PB4, PINCTRL_ROCKCHIP_ONE, 0x0300,
1128 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FOURTEEN, PINCTRL_ROCKCHIP_FOURTEEN,
1129 PINCTRL_ROCKCHIP_ONE)), /* I2C2 IO mux M1 */
1130 RK_MUXROUTE_GRF(
1131 PINCTRL_ROCKCHIP_ONE, RK_PA0, PINCTRL_ROCKCHIP_ONE, 0x0304,
1132 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO)), /* I2C3 IO mux M0 */
1133 RK_MUXROUTE_GRF(
1134 PINCTRL_ROCKCHIP_THREE, RK_PB6, PINCTRL_ROCKCHIP_FOUR, 0x0304,
1135 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ONE)), /* I2C3 IO mux M1 */
1136 RK_MUXROUTE_GRF(
1137 PINCTRL_ROCKCHIP_FOUR, RK_PB2, PINCTRL_ROCKCHIP_ONE, 0x0304,
1138 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_ZERO)), /* I2C4 IO mux M0 */
1139 RK_MUXROUTE_GRF(
1140 PINCTRL_ROCKCHIP_TWO, RK_PB1, PINCTRL_ROCKCHIP_TWO, 0x0304,
1141 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_ONE)), /* I2C4 IO mux M1 */
1142 RK_MUXROUTE_GRF(
1143 PINCTRL_ROCKCHIP_THREE, RK_PB4, PINCTRL_ROCKCHIP_FOUR, 0x0304,
1144 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_ZERO)), /* I2C5 IO mux M0 */
1145 RK_MUXROUTE_GRF(
1146 PINCTRL_ROCKCHIP_FOUR, RK_PD0, PINCTRL_ROCKCHIP_TWO, 0x0304,
1147 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_ONE)), /* I2C5 IO mux M1 */
1148 RK_MUXROUTE_GRF(PINCTRL_ROCKCHIP_THREE, RK_PB1, PINCTRL_ROCKCHIP_FIVE, 0x0304,
1149 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FOURTEEN, PINCTRL_ROCKCHIP_FOURTEEN,
1150 PINCTRL_ROCKCHIP_ZERO)), /* PWM8 IO mux M0 */
1151 RK_MUXROUTE_GRF(PINCTRL_ROCKCHIP_ONE, RK_PD5, PINCTRL_ROCKCHIP_FOUR, 0x0304,
1152 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FOURTEEN, PINCTRL_ROCKCHIP_FOURTEEN,
1153 PINCTRL_ROCKCHIP_ONE)), /* PWM8 IO mux M1 */
1154 RK_MUXROUTE_GRF(
1155 PINCTRL_ROCKCHIP_THREE, RK_PB2, PINCTRL_ROCKCHIP_FIVE, 0x0308,
1156 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO)), /* PWM9 IO mux M0 */
1157 RK_MUXROUTE_GRF(
1158 PINCTRL_ROCKCHIP_ONE, RK_PD6, PINCTRL_ROCKCHIP_FOUR, 0x0308,
1159 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ONE)), /* PWM9 IO mux M1 */
1160 RK_MUXROUTE_GRF(
1161 PINCTRL_ROCKCHIP_THREE, RK_PB5, PINCTRL_ROCKCHIP_FIVE, 0x0308,
1162 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_ZERO)), /* PWM10 IO mux M0 */
1163 RK_MUXROUTE_GRF(
1164 PINCTRL_ROCKCHIP_TWO, RK_PA1, PINCTRL_ROCKCHIP_TWO, 0x0308,
1165 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_ONE)), /* PWM10 IO mux M1 */
1166 RK_MUXROUTE_GRF(
1167 PINCTRL_ROCKCHIP_THREE, RK_PB6, PINCTRL_ROCKCHIP_FIVE, 0x0308,
1168 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_ZERO)), /* PWM11 IO mux M0 */
1169 RK_MUXROUTE_GRF(
1170 PINCTRL_ROCKCHIP_FOUR, RK_PC0, PINCTRL_ROCKCHIP_THREE, 0x0308,
1171 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_ONE)), /* PWM11 IO mux M1 */
1172 RK_MUXROUTE_GRF(
1173 PINCTRL_ROCKCHIP_THREE, RK_PB7, PINCTRL_ROCKCHIP_TWO, 0x0308,
1174 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_ZERO)), /* PWM12 IO mux M0 */
1175 RK_MUXROUTE_GRF(
1176 PINCTRL_ROCKCHIP_FOUR, RK_PC5, PINCTRL_ROCKCHIP_ONE, 0x0308,
1177 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_ONE)), /* PWM12 IO mux M1 */
1178 RK_MUXROUTE_GRF(
1179 PINCTRL_ROCKCHIP_THREE, RK_PC0, PINCTRL_ROCKCHIP_TWO, 0x0308,
1180 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_ZERO)), /* PWM13 IO mux M0 */
1181 RK_MUXROUTE_GRF(
1182 PINCTRL_ROCKCHIP_FOUR, RK_PC6, PINCTRL_ROCKCHIP_ONE, 0x0308,
1183 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_ONE)), /* PWM13 IO mux M1 */
1184 RK_MUXROUTE_GRF(
1185 PINCTRL_ROCKCHIP_THREE, RK_PC4, PINCTRL_ROCKCHIP_ONE, 0x0308,
1186 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_ZERO)), /* PWM14 IO mux M0 */
1187 RK_MUXROUTE_GRF(
1188 PINCTRL_ROCKCHIP_FOUR, RK_PC2, PINCTRL_ROCKCHIP_ONE, 0x0308,
1189 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_ONE)), /* PWM14 IO mux M1 */
1190 RK_MUXROUTE_GRF(
1191 PINCTRL_ROCKCHIP_THREE, RK_PC5, PINCTRL_ROCKCHIP_ONE, 0x0308,
1192 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWELVE, PINCTRL_ROCKCHIP_TWELVE, PINCTRL_ROCKCHIP_ZERO)), /* PWM15 IO mux M0 */
1193 RK_MUXROUTE_GRF(
1194 PINCTRL_ROCKCHIP_FOUR, RK_PC3, PINCTRL_ROCKCHIP_ONE, 0x0308,
1195 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWELVE, PINCTRL_ROCKCHIP_TWELVE, PINCTRL_ROCKCHIP_ONE)), /* PWM15 IO mux M1 */
1196 RK_MUXROUTE_GRF(PINCTRL_ROCKCHIP_THREE, RK_PD2, PINCTRL_ROCKCHIP_THREE, 0x0308,
1197 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FOURTEEN, PINCTRL_ROCKCHIP_FOURTEEN,
1198 PINCTRL_ROCKCHIP_ZERO)), /* SDMMC2 IO mux M0 */
1199 RK_MUXROUTE_GRF(PINCTRL_ROCKCHIP_THREE, RK_PA5, PINCTRL_ROCKCHIP_FIVE, 0x0308,
1200 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FOURTEEN, PINCTRL_ROCKCHIP_FOURTEEN,
1201 PINCTRL_ROCKCHIP_ONE)), /* SDMMC2 IO mux M1 */
1202 RK_MUXROUTE_PMU(
1203 PINCTRL_ROCKCHIP_ZERO, RK_PB5, PINCTRL_ROCKCHIP_TWO, 0x030c,
1204 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO)), /* SPI0 IO mux M0 */
1205 RK_MUXROUTE_GRF(
1206 PINCTRL_ROCKCHIP_TWO, RK_PD3, PINCTRL_ROCKCHIP_THREE, 0x030c,
1207 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ONE)), /* SPI0 IO mux M1 */
1208 RK_MUXROUTE_GRF(
1209 PINCTRL_ROCKCHIP_TWO, RK_PB5, PINCTRL_ROCKCHIP_THREE, 0x030c,
1210 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_ZERO)), /* SPI1 IO mux M0 */
1211 RK_MUXROUTE_GRF(
1212 PINCTRL_ROCKCHIP_THREE, RK_PC3, PINCTRL_ROCKCHIP_THREE, 0x030c,
1213 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_ONE)), /* SPI1 IO mux M1 */
1214 RK_MUXROUTE_GRF(
1215 PINCTRL_ROCKCHIP_TWO, RK_PC1, PINCTRL_ROCKCHIP_FOUR, 0x030c,
1216 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_ZERO)), /* SPI2 IO mux M0 */
1217 RK_MUXROUTE_GRF(
1218 PINCTRL_ROCKCHIP_THREE, RK_PA0, PINCTRL_ROCKCHIP_THREE, 0x030c,
1219 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_ONE)), /* SPI2 IO mux M1 */
1220 RK_MUXROUTE_GRF(
1221 PINCTRL_ROCKCHIP_FOUR, RK_PB3, PINCTRL_ROCKCHIP_FOUR, 0x030c,
1222 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_ZERO)), /* SPI3 IO mux M0 */
1223 RK_MUXROUTE_GRF(
1224 PINCTRL_ROCKCHIP_FOUR, RK_PC2, PINCTRL_ROCKCHIP_TWO, 0x030c,
1225 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_ONE)), /* SPI3 IO mux M1 */
1226 RK_MUXROUTE_GRF(
1227 PINCTRL_ROCKCHIP_TWO, RK_PB4, PINCTRL_ROCKCHIP_TWO, 0x030c,
1228 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_ZERO)), /* UART1 IO mux M0 */
1229 RK_MUXROUTE_GRF(
1230 PINCTRL_ROCKCHIP_THREE, RK_PD6, PINCTRL_ROCKCHIP_FOUR, 0x030c,
1231 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_ONE)), /* UART1 IO mux M1 */
1232 RK_MUXROUTE_PMU(
1233 PINCTRL_ROCKCHIP_ZERO, RK_PD1, PINCTRL_ROCKCHIP_ONE, 0x030c,
1234 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_ZERO)), /* UART2 IO mux M0 */
1235 RK_MUXROUTE_GRF(
1236 PINCTRL_ROCKCHIP_ONE, RK_PD5, PINCTRL_ROCKCHIP_TWO, 0x030c,
1237 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_ONE)), /* UART2 IO mux M1 */
1238 RK_MUXROUTE_GRF(
1239 PINCTRL_ROCKCHIP_ONE, RK_PA1, PINCTRL_ROCKCHIP_TWO, 0x030c,
1240 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWELVE, PINCTRL_ROCKCHIP_TWELVE, PINCTRL_ROCKCHIP_ZERO)), /* UART3 IO mux M0 */
1241 RK_MUXROUTE_GRF(
1242 PINCTRL_ROCKCHIP_THREE, RK_PB7, PINCTRL_ROCKCHIP_FOUR, 0x030c,
1243 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWELVE, PINCTRL_ROCKCHIP_TWELVE, PINCTRL_ROCKCHIP_ONE)), /* UART3 IO mux M1 */
1244 RK_MUXROUTE_GRF(PINCTRL_ROCKCHIP_ONE, RK_PA6, PINCTRL_ROCKCHIP_TWO, 0x030c,
1245 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FOURTEEN, PINCTRL_ROCKCHIP_FOURTEEN,
1246 PINCTRL_ROCKCHIP_ZERO)), /* UART4 IO mux M0 */
1247 RK_MUXROUTE_GRF(PINCTRL_ROCKCHIP_THREE, RK_PB2, PINCTRL_ROCKCHIP_FOUR, 0x030c,
1248 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FOURTEEN, PINCTRL_ROCKCHIP_FOURTEEN,
1249 PINCTRL_ROCKCHIP_ONE)), /* UART4 IO mux M1 */
1250 RK_MUXROUTE_GRF(
1251 PINCTRL_ROCKCHIP_TWO, RK_PA2, PINCTRL_ROCKCHIP_THREE, 0x0310,
1252 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO)), /* UART5 IO mux M0 */
1253 RK_MUXROUTE_GRF(
1254 PINCTRL_ROCKCHIP_THREE, RK_PC2, PINCTRL_ROCKCHIP_FOUR, 0x0310,
1255 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ONE)), /* UART5 IO mux M1 */
1256 RK_MUXROUTE_GRF(
1257 PINCTRL_ROCKCHIP_TWO, RK_PA4, PINCTRL_ROCKCHIP_THREE, 0x0310,
1258 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_ZERO)), /* UART6 IO mux M0 */
1259 RK_MUXROUTE_GRF(
1260 PINCTRL_ROCKCHIP_ONE, RK_PD5, PINCTRL_ROCKCHIP_THREE, 0x0310,
1261 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_ONE)), /* UART6 IO mux M1 */
1262 RK_MUXROUTE_GRF(
1263 PINCTRL_ROCKCHIP_TWO, RK_PA6, PINCTRL_ROCKCHIP_THREE, 0x0310,
1264 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FIVE, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_ZERO)), /* UART7 IO mux M0 */
1265 RK_MUXROUTE_GRF(
1266 PINCTRL_ROCKCHIP_THREE, RK_PC4, PINCTRL_ROCKCHIP_FOUR, 0x0310,
1267 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FIVE, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_ONE)), /* UART7 IO mux M1 */
1268 RK_MUXROUTE_GRF(
1269 PINCTRL_ROCKCHIP_FOUR, RK_PA2, PINCTRL_ROCKCHIP_FOUR, 0x0310,
1270 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FIVE, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_TWO)), /* UART7 IO mux M2 */
1271 RK_MUXROUTE_GRF(
1272 PINCTRL_ROCKCHIP_TWO, RK_PC5, PINCTRL_ROCKCHIP_THREE, 0x0310,
1273 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_ZERO)), /* UART8 IO mux M0 */
1274 RK_MUXROUTE_GRF(
1275 PINCTRL_ROCKCHIP_TWO, RK_PD7, PINCTRL_ROCKCHIP_FOUR, 0x0310,
1276 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_ONE)), /* UART8 IO mux M1 */
1277 RK_MUXROUTE_GRF(
1278 PINCTRL_ROCKCHIP_TWO, RK_PB0, PINCTRL_ROCKCHIP_THREE, 0x0310,
1279 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_NINE, PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_ZERO)), /* UART9 IO mux M0 */
1280 RK_MUXROUTE_GRF(
1281 PINCTRL_ROCKCHIP_FOUR, RK_PC5, PINCTRL_ROCKCHIP_FOUR, 0x0310,
1282 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_NINE, PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_ONE)), /* UART9 IO mux M1 */
1283 RK_MUXROUTE_GRF(
1284 PINCTRL_ROCKCHIP_FOUR, RK_PA4, PINCTRL_ROCKCHIP_FOUR, 0x0310,
1285 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_NINE, PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_TWO)), /* UART9 IO mux M2 */
1286 RK_MUXROUTE_GRF(
1287 PINCTRL_ROCKCHIP_ONE, RK_PA2, PINCTRL_ROCKCHIP_ONE, 0x0310,
1288 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ELEVEN, PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_ZERO)), /* I2S1 IO mux M0 */
1289 RK_MUXROUTE_GRF(
1290 PINCTRL_ROCKCHIP_THREE, RK_PC6, PINCTRL_ROCKCHIP_FOUR, 0x0310,
1291 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ELEVEN, PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_ONE)), /* I2S1 IO mux M1 */
1292 RK_MUXROUTE_GRF(
1293 PINCTRL_ROCKCHIP_TWO, RK_PD0, PINCTRL_ROCKCHIP_FIVE, 0x0310,
1294 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ELEVEN, PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_TWO)), /* I2S1 IO mux M2 */
1295 RK_MUXROUTE_GRF(
1296 PINCTRL_ROCKCHIP_TWO, RK_PC1, PINCTRL_ROCKCHIP_ONE, 0x0310,
1297 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWELVE, PINCTRL_ROCKCHIP_TWELVE, PINCTRL_ROCKCHIP_ZERO)), /* I2S2 IO mux M0 */
1298 RK_MUXROUTE_GRF(
1299 PINCTRL_ROCKCHIP_FOUR, RK_PB6, PINCTRL_ROCKCHIP_FIVE, 0x0310,
1300 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_TWELVE, PINCTRL_ROCKCHIP_TWELVE, PINCTRL_ROCKCHIP_ONE)), /* I2S2 IO mux M1 */
1301 RK_MUXROUTE_GRF(PINCTRL_ROCKCHIP_THREE, RK_PA2, PINCTRL_ROCKCHIP_FOUR, 0x0310,
1302 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FOURTEEN, PINCTRL_ROCKCHIP_FOURTEEN,
1303 PINCTRL_ROCKCHIP_ZERO)), /* I2S3 IO mux M0 */
1304 RK_MUXROUTE_GRF(PINCTRL_ROCKCHIP_FOUR, RK_PC2, PINCTRL_ROCKCHIP_FIVE, 0x0310,
1305 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FOURTEEN, PINCTRL_ROCKCHIP_FOURTEEN,
1306 PINCTRL_ROCKCHIP_ONE)), /* I2S3 IO mux M1 */
1307 RK_MUXROUTE_GRF(
1308 PINCTRL_ROCKCHIP_ONE, RK_PA4, PINCTRL_ROCKCHIP_THREE, 0x0314,
1309 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ONE, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO)), /* PDM IO mux M0 */
1310 RK_MUXROUTE_GRF(
1311 PINCTRL_ROCKCHIP_ONE, RK_PA6, PINCTRL_ROCKCHIP_THREE, 0x0314,
1312 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ONE, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ZERO)), /* PDM IO mux M0 */
1313 RK_MUXROUTE_GRF(
1314 PINCTRL_ROCKCHIP_THREE, RK_PD6, PINCTRL_ROCKCHIP_FIVE, 0x0314,
1315 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ONE, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ONE)), /* PDM IO mux M1 */
1316 RK_MUXROUTE_GRF(
1317 PINCTRL_ROCKCHIP_FOUR, RK_PA0, PINCTRL_ROCKCHIP_FOUR, 0x0314,
1318 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ONE, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_ONE)), /* PDM IO mux M1 */
1319 RK_MUXROUTE_GRF(
1320 PINCTRL_ROCKCHIP_THREE, RK_PC4, PINCTRL_ROCKCHIP_FIVE, 0x0314,
1321 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_ONE, PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_TWO)), /* PDM IO mux M2 */
1322 RK_MUXROUTE_PMU(
1323 PINCTRL_ROCKCHIP_ZERO, RK_PA5, PINCTRL_ROCKCHIP_THREE, 0x0314,
1324 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_THREE, PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_ZERO)), /* PCIE20 IO mux M0 */
1325 RK_MUXROUTE_GRF(
1326 PINCTRL_ROCKCHIP_TWO, RK_PD0, PINCTRL_ROCKCHIP_FOUR, 0x0314,
1327 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_THREE, PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_ONE)), /* PCIE20 IO mux M1 */
1328 RK_MUXROUTE_GRF(
1329 PINCTRL_ROCKCHIP_ONE, RK_PB0, PINCTRL_ROCKCHIP_FOUR, 0x0314,
1330 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_THREE, PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_TWO)), /* PCIE20 IO mux M2 */
1331 RK_MUXROUTE_PMU(
1332 PINCTRL_ROCKCHIP_ZERO, RK_PA4, PINCTRL_ROCKCHIP_THREE, 0x0314,
1333 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FIVE, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_ZERO)), /* PCIE30X1 IO mux M0 */
1334 RK_MUXROUTE_GRF(
1335 PINCTRL_ROCKCHIP_TWO, RK_PD2, PINCTRL_ROCKCHIP_FOUR, 0x0314,
1336 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FIVE, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_ONE)), /* PCIE30X1 IO mux M1 */
1337 RK_MUXROUTE_GRF(
1338 PINCTRL_ROCKCHIP_ONE, RK_PA5, PINCTRL_ROCKCHIP_FOUR, 0x0314,
1339 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_FIVE, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_TWO)), /* PCIE30X1 IO mux M2 */
1340 RK_MUXROUTE_PMU(
1341 PINCTRL_ROCKCHIP_ZERO, RK_PA6, PINCTRL_ROCKCHIP_TWO, 0x0314,
1342 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_SEVEN, PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_ZERO)), /* PCIE30X2 IO mux M0 */
1343 RK_MUXROUTE_GRF(
1344 PINCTRL_ROCKCHIP_TWO, RK_PD4, PINCTRL_ROCKCHIP_FOUR, 0x0314,
1345 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_SEVEN, PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_ONE)), /* PCIE30X2 IO mux M1 */
1346 RK_MUXROUTE_GRF(
1347 PINCTRL_ROCKCHIP_FOUR, RK_PC2, PINCTRL_ROCKCHIP_FOUR, 0x0314,
1348 WRITE_MASK_VAL(PINCTRL_ROCKCHIP_SEVEN, PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_TWO)), /* PCIE30X2 IO mux M2 */
1349 };
1350
rockchip_get_mux_route(struct rockchip_pin_bank * bank,int pin,int mux,u32 * loc,u32 * reg,u32 * value)1351 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, int mux, u32 *loc, u32 *reg, u32 *value)
1352 {
1353 struct rockchip_pinctrl *info = bank->drvdata;
1354 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1355 struct rockchip_mux_route_data *data;
1356 int i;
1357
1358 for (i = 0; i < ctrl->niomux_routes; i++) {
1359 data = &ctrl->iomux_routes[i];
1360 if ((data->bank_num == bank->bank_num) && (data->pin == pin) && (data->func == mux)) {
1361 break;
1362 }
1363 }
1364
1365 if (i >= ctrl->niomux_routes) {
1366 return false;
1367 }
1368
1369 *loc = data->route_location;
1370 *reg = data->route_offset;
1371 *value = data->route_val;
1372
1373 return true;
1374 }
1375
rockchip_get_mux(struct rockchip_pin_bank * bank,int pin)1376 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
1377 {
1378 struct rockchip_pinctrl *info = bank->drvdata;
1379 int iomux_num = (pin / PINCTRL_ROCKCHIP_EIGHT);
1380 struct regmap *regmap;
1381 unsigned int val;
1382 int reg, ret, mask, mux_type;
1383 u8 bit;
1384
1385 if (iomux_num > PINCTRL_ROCKCHIP_THREE) {
1386 return -EINVAL;
1387 }
1388
1389 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1390 dev_err(info->dev, "pin %d is unrouted\n", pin);
1391 return -EINVAL;
1392 }
1393
1394 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
1395 return RK_FUNC_GPIO;
1396 }
1397
1398 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) {
1399 regmap = info->regmap_pmu;
1400 } else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) {
1401 regmap = (pin % PINCTRL_ROCKCHIP_EIGHT < PINCTRL_ROCKCHIP_FOUR) ? info->regmap_pmu : info->regmap_base;
1402 } else {
1403 regmap = info->regmap_base;
1404 }
1405
1406 /* get basic quadrupel of mux registers and the correct reg inside */
1407 mux_type = bank->iomux[iomux_num].type;
1408 reg = bank->iomux[iomux_num].offset;
1409 if (mux_type & IOMUX_WIDTH_4BIT) {
1410 if ((pin % PINCTRL_ROCKCHIP_EIGHT) >= PINCTRL_ROCKCHIP_FOUR) {
1411 reg += 0x4;
1412 }
1413 bit = (pin % PINCTRL_ROCKCHIP_FOUR) * PINCTRL_ROCKCHIP_FOUR;
1414 mask = 0xf;
1415 } else if (mux_type & IOMUX_WIDTH_3BIT) {
1416 if ((pin % PINCTRL_ROCKCHIP_EIGHT) >= PINCTRL_ROCKCHIP_FIVE) {
1417 reg += 0x4;
1418 }
1419 bit = (pin % PINCTRL_ROCKCHIP_EIGHT % PINCTRL_ROCKCHIP_FIVE) * PINCTRL_ROCKCHIP_THREE;
1420 mask = 0x7;
1421 } else {
1422 bit = (pin % PINCTRL_ROCKCHIP_EIGHT) * 0x2;
1423 mask = 0x3;
1424 }
1425
1426 if (bank->recalced_mask & BIT(pin)) {
1427 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
1428 }
1429
1430 ret = regmap_read(regmap, reg, &val);
1431 if (ret) {
1432 return ret;
1433 }
1434
1435 return ((val >> bit) & mask);
1436 }
1437
rockchip_verify_mux(struct rockchip_pin_bank * bank,int pin,int mux)1438 static int rockchip_verify_mux(struct rockchip_pin_bank *bank, int pin, int mux)
1439 {
1440 struct rockchip_pinctrl *info = bank->drvdata;
1441 int iomux_num = (pin / PINCTRL_ROCKCHIP_EIGHT);
1442
1443 if (iomux_num > PINCTRL_ROCKCHIP_THREE) {
1444 return -EINVAL;
1445 }
1446
1447 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1448 dev_err(info->dev, "pin %d is unrouted\n", pin);
1449 return -EINVAL;
1450 }
1451
1452 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
1453 if (mux != RK_FUNC_GPIO) {
1454 dev_err(info->dev, "pin %d only supports a gpio mux\n", pin);
1455 return -ENOTSUPP;
1456 }
1457 }
1458
1459 return 0;
1460 }
1461
1462 /*
1463 * Set a new mux function for a pin.
1464 *
1465 * The register is divided into the upper and lower 16 bit. When changing
1466 * a value, the previous register value is not read and changed. Instead
1467 * it seems the changed bits are marked in the upper 16 bit, while the
1468 * changed value gets set in the same offset in the lower 16 bit.
1469 * All pin settings seem to be 2 bit wide in both the upper and lower
1470 * parts.
1471 * @bank: pin bank to change
1472 * @pin: pin to change
1473 * @mux: new mux function to set
1474 */
rockchip_set_mux(struct rockchip_pin_bank * bank,int pin,int mux)1475 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
1476 {
1477 struct rockchip_pinctrl *info = bank->drvdata;
1478 int iomux_num = (pin / PINCTRL_ROCKCHIP_EIGHT);
1479 struct regmap *regmap;
1480 int reg, ret, mask, mux_type;
1481 u8 bit;
1482 u32 data, rmask, route_location, route_reg, route_val;
1483
1484 ret = rockchip_verify_mux(bank, pin, mux);
1485 if (ret < 0) {
1486 return ret;
1487 }
1488
1489 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
1490 return 0;
1491 }
1492
1493 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
1494
1495 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) {
1496 regmap = info->regmap_pmu;
1497 } else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) {
1498 regmap = (pin % PINCTRL_ROCKCHIP_EIGHT < PINCTRL_ROCKCHIP_FOUR) ? info->regmap_pmu : info->regmap_base;
1499 } else {
1500 regmap = info->regmap_base;
1501 }
1502
1503 /* get basic quadrupel of mux registers and the correct reg inside */
1504 mux_type = bank->iomux[iomux_num].type;
1505 reg = bank->iomux[iomux_num].offset;
1506 if (mux_type & IOMUX_WIDTH_4BIT) {
1507 if ((pin % PINCTRL_ROCKCHIP_EIGHT) >= PINCTRL_ROCKCHIP_FOUR) {
1508 reg += 0x4;
1509 }
1510 bit = (pin % PINCTRL_ROCKCHIP_FOUR) * PINCTRL_ROCKCHIP_FOUR;
1511 mask = 0xf;
1512 } else if (mux_type & IOMUX_WIDTH_3BIT) {
1513 if ((pin % PINCTRL_ROCKCHIP_EIGHT) >= PINCTRL_ROCKCHIP_FIVE) {
1514 reg += 0x4;
1515 }
1516 bit = (pin % PINCTRL_ROCKCHIP_EIGHT % PINCTRL_ROCKCHIP_FIVE) * PINCTRL_ROCKCHIP_THREE;
1517 mask = 0x7;
1518 } else {
1519 bit = (pin % PINCTRL_ROCKCHIP_EIGHT) * 0x2;
1520 mask = 0x3;
1521 }
1522
1523 if (bank->recalced_mask & BIT(pin)) {
1524 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
1525 }
1526
1527 if (mux > mask) {
1528 return -EINVAL;
1529 }
1530
1531 if (bank->route_mask & BIT(pin)) {
1532 if (rockchip_get_mux_route(bank, pin, mux, &route_location, &route_reg, &route_val)) {
1533 struct regmap *route_regmap = regmap;
1534
1535 /* handle special locations */
1536 switch (route_location) {
1537 case ROCKCHIP_ROUTE_PMU:
1538 route_regmap = info->regmap_pmu;
1539 break;
1540 case ROCKCHIP_ROUTE_GRF:
1541 route_regmap = info->regmap_base;
1542 break;
1543 }
1544
1545 ret = regmap_write(route_regmap, route_reg, route_val);
1546 if (ret) {
1547 return ret;
1548 }
1549 }
1550 }
1551
1552 if (mux_type & IOMUX_WRITABLE_32BIT) {
1553 ret = regmap_read(regmap, reg, &data);
1554 if (ret) {
1555 return ret;
1556 }
1557
1558 data &= ~(mask << bit);
1559 data |= (mux & mask) << bit;
1560 ret = regmap_write(regmap, reg, data);
1561 } else {
1562 data = (mask << (bit + PINCTRL_ROCKCHIP_SIXTEEN));
1563 rmask = data | (data >> PINCTRL_ROCKCHIP_SIXTEEN);
1564 data |= (mux & mask) << bit;
1565 ret = regmap_update_bits(regmap, reg, rmask, data);
1566 }
1567
1568 return ret;
1569 }
1570
1571 #define PX30_PULL_PMU_OFFSET 0x10
1572 #define PX30_PULL_GRF_OFFSET 0x60
1573 #define PX30_PULL_BITS_PER_PIN 2
1574 #define PX30_PULL_PINS_PER_REG 8
1575 #define PX30_PULL_BANK_STRIDE 16
1576
px30_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1577 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg,
1578 u8 *bit)
1579 {
1580 struct rockchip_pinctrl *info = bank->drvdata;
1581
1582 /* The first 32 pins of the first bank are located in PMU */
1583 if (bank->bank_num == 0) {
1584 *regmap = info->regmap_pmu;
1585 *reg = PX30_PULL_PMU_OFFSET;
1586 } else {
1587 *regmap = info->regmap_base;
1588 *reg = PX30_PULL_GRF_OFFSET;
1589
1590 /* correct the offset, as we're starting with the 2nd bank */
1591 *reg -= 0x10;
1592 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
1593 }
1594
1595 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * PINCTRL_ROCKCHIP_FOUR);
1596 *bit = (pin_num % PX30_PULL_PINS_PER_REG);
1597 *bit *= PX30_PULL_BITS_PER_PIN;
1598 }
1599
1600 #define PX30_DRV_PMU_OFFSET 0x20
1601 #define PX30_DRV_GRF_OFFSET 0xf0
1602 #define PX30_DRV_BITS_PER_PIN 2
1603 #define PX30_DRV_PINS_PER_REG 8
1604 #define PX30_DRV_BANK_STRIDE 16
1605
px30_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1606 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg,
1607 u8 *bit)
1608 {
1609 struct rockchip_pinctrl *info = bank->drvdata;
1610
1611 /* The first 32 pins of the first bank are located in PMU */
1612 if (bank->bank_num == 0) {
1613 *regmap = info->regmap_pmu;
1614 *reg = PX30_DRV_PMU_OFFSET;
1615 } else {
1616 *regmap = info->regmap_base;
1617 *reg = PX30_DRV_GRF_OFFSET;
1618
1619 /* correct the offset, as we're starting with the 2nd bank */
1620 *reg -= 0x10;
1621 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
1622 }
1623
1624 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * PINCTRL_ROCKCHIP_FOUR);
1625 *bit = (pin_num % PX30_DRV_PINS_PER_REG);
1626 *bit *= PX30_DRV_BITS_PER_PIN;
1627 }
1628
1629 #define PX30_SCHMITT_PMU_OFFSET 0x38
1630 #define PX30_SCHMITT_GRF_OFFSET 0xc0
1631 #define PX30_SCHMITT_PINS_PER_PMU_REG 16
1632 #define PX30_SCHMITT_BANK_STRIDE 16
1633 #define PX30_SCHMITT_PINS_PER_GRF_REG 8
1634
px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1635 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg,
1636 u8 *bit)
1637 {
1638 struct rockchip_pinctrl *info = bank->drvdata;
1639 int pins_per_reg;
1640
1641 if (bank->bank_num == 0) {
1642 *regmap = info->regmap_pmu;
1643 *reg = PX30_SCHMITT_PMU_OFFSET;
1644 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
1645 } else {
1646 *regmap = info->regmap_base;
1647 *reg = PX30_SCHMITT_GRF_OFFSET;
1648 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
1649 *reg += (bank->bank_num - PINCTRL_ROCKCHIP_ONE) * PX30_SCHMITT_BANK_STRIDE;
1650 }
1651
1652 *reg += ((pin_num / pins_per_reg) * PINCTRL_ROCKCHIP_FOUR);
1653 *bit = pin_num % pins_per_reg;
1654
1655 return 0;
1656 }
1657
1658 #define RV1108_PULL_PMU_OFFSET 0x10
1659 #define RV1108_PULL_OFFSET 0x110
1660 #define RV1108_PULL_PINS_PER_REG 8
1661 #define RV1108_PULL_BITS_PER_PIN 2
1662 #define RV1108_PULL_BANK_STRIDE 16
1663
rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1664 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg,
1665 u8 *bit)
1666 {
1667 struct rockchip_pinctrl *info = bank->drvdata;
1668
1669 /* The first 24 pins of the first bank are located in PMU */
1670 if (bank->bank_num == 0) {
1671 *regmap = info->regmap_pmu;
1672 *reg = RV1108_PULL_PMU_OFFSET;
1673 } else {
1674 *reg = RV1108_PULL_OFFSET;
1675 *regmap = info->regmap_base;
1676 /* correct the offset, as we're starting with the 2nd bank */
1677 *reg -= 0x10;
1678 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
1679 }
1680
1681 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * PINCTRL_ROCKCHIP_FOUR);
1682 *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
1683 *bit *= RV1108_PULL_BITS_PER_PIN;
1684 }
1685
1686 #define RV1108_DRV_PMU_OFFSET 0x20
1687 #define RV1108_DRV_GRF_OFFSET 0x210
1688 #define RV1108_DRV_BITS_PER_PIN 2
1689 #define RV1108_DRV_PINS_PER_REG 8
1690 #define RV1108_DRV_BANK_STRIDE 16
1691
rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1692 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg,
1693 u8 *bit)
1694 {
1695 struct rockchip_pinctrl *info = bank->drvdata;
1696
1697 /* The first 24 pins of the first bank are located in PMU */
1698 if (bank->bank_num == 0) {
1699 *regmap = info->regmap_pmu;
1700 *reg = RV1108_DRV_PMU_OFFSET;
1701 } else {
1702 *regmap = info->regmap_base;
1703 *reg = RV1108_DRV_GRF_OFFSET;
1704
1705 /* correct the offset, as we're starting with the 2nd bank */
1706 *reg -= 0x10;
1707 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
1708 }
1709
1710 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * PINCTRL_ROCKCHIP_FOUR);
1711 *bit = pin_num % RV1108_DRV_PINS_PER_REG;
1712 *bit *= RV1108_DRV_BITS_PER_PIN;
1713 }
1714
1715 #define RV1108_SCHMITT_PMU_OFFSET 0x30
1716 #define RV1108_SCHMITT_GRF_OFFSET 0x388
1717 #define RV1108_SCHMITT_BANK_STRIDE 8
1718 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16
1719 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8
1720
rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1721 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap,
1722 int *reg, u8 *bit)
1723 {
1724 struct rockchip_pinctrl *info = bank->drvdata;
1725 int pins_per_reg;
1726
1727 if (bank->bank_num == 0) {
1728 *regmap = info->regmap_pmu;
1729 *reg = RV1108_SCHMITT_PMU_OFFSET;
1730 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
1731 } else {
1732 *regmap = info->regmap_base;
1733 *reg = RV1108_SCHMITT_GRF_OFFSET;
1734 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
1735 *reg += (bank->bank_num - PINCTRL_ROCKCHIP_ONE) * RV1108_SCHMITT_BANK_STRIDE;
1736 }
1737 *reg += ((pin_num / pins_per_reg) * PINCTRL_ROCKCHIP_FOUR);
1738 *bit = pin_num % pins_per_reg;
1739
1740 return 0;
1741 }
1742
1743 #define RV1126_PULL_PMU_OFFSET 0x40
1744 #define RV1126_PULL_GRF_GPIO1A0_OFFSET 0x10108
1745 #define RV1126_PULL_PINS_PER_REG 8
1746 #define RV1126_PULL_BITS_PER_PIN 2
1747 #define RV1126_PULL_BANK_STRIDE 16
1748 #define RV1126_GPIO_C4_D7(p) (p >= 20 && p <= PINCTRL_ROCKCHIP_THIRTYONE) /* GPIO0_C4 ~ GPIO0_D7 */
1749
rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1750 static void rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg,
1751 u8 *bit)
1752 {
1753 struct rockchip_pinctrl *info = bank->drvdata;
1754
1755 /* The first 24 pins of the first bank are located in PMU */
1756 if (bank->bank_num == 0) {
1757 if (RV1126_GPIO_C4_D7(pin_num)) {
1758 *regmap = info->regmap_base;
1759 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
1760 *reg -= (((PINCTRL_ROCKCHIP_THIRTYONE - pin_num) / RV1126_PULL_PINS_PER_REG + PINCTRL_ROCKCHIP_ONE) *
1761 PINCTRL_ROCKCHIP_FOUR);
1762 *bit = pin_num % RV1126_PULL_PINS_PER_REG;
1763 *bit *= RV1126_PULL_BITS_PER_PIN;
1764 return;
1765 }
1766 *regmap = info->regmap_pmu;
1767 *reg = RV1126_PULL_PMU_OFFSET;
1768 } else {
1769 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
1770 *regmap = info->regmap_base;
1771 *reg += (bank->bank_num - PINCTRL_ROCKCHIP_ONE) * RV1126_PULL_BANK_STRIDE;
1772 }
1773
1774 *reg += ((pin_num / RV1126_PULL_PINS_PER_REG) * PINCTRL_ROCKCHIP_FOUR);
1775 *bit = (pin_num % RV1126_PULL_PINS_PER_REG);
1776 *bit *= RV1126_PULL_BITS_PER_PIN;
1777 }
1778
1779 #define RV1126_DRV_PMU_OFFSET 0x20
1780 #define RV1126_DRV_GRF_GPIO1A0_OFFSET 0x10090
1781 #define RV1126_DRV_BITS_PER_PIN 4
1782 #define RV1126_DRV_PINS_PER_REG 4
1783 #define RV1126_DRV_BANK_STRIDE 32
1784
rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1785 static void rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg,
1786 u8 *bit)
1787 {
1788 struct rockchip_pinctrl *info = bank->drvdata;
1789
1790 /* The first 24 pins of the first bank are located in PMU */
1791 if (bank->bank_num == 0) {
1792 if (RV1126_GPIO_C4_D7(pin_num)) {
1793 *regmap = info->regmap_base;
1794 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
1795 *reg -= (((PINCTRL_ROCKCHIP_THIRTYONE - pin_num) / RV1126_DRV_PINS_PER_REG + PINCTRL_ROCKCHIP_ONE) *
1796 PINCTRL_ROCKCHIP_FOUR);
1797 *reg -= 0x4;
1798 *bit = pin_num % RV1126_DRV_PINS_PER_REG;
1799 *bit *= RV1126_DRV_BITS_PER_PIN;
1800 return;
1801 }
1802 *regmap = info->regmap_pmu;
1803 *reg = RV1126_DRV_PMU_OFFSET;
1804 } else {
1805 *regmap = info->regmap_base;
1806 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
1807 *reg += (bank->bank_num - PINCTRL_ROCKCHIP_ONE) * RV1126_DRV_BANK_STRIDE;
1808 }
1809
1810 *reg += ((pin_num / RV1126_DRV_PINS_PER_REG) * PINCTRL_ROCKCHIP_FOUR);
1811 *bit = pin_num % RV1126_DRV_PINS_PER_REG;
1812 *bit *= RV1126_DRV_BITS_PER_PIN;
1813 }
1814
1815 #define RV1126_SCHMITT_PMU_OFFSET 0x60
1816 #define RV1126_SCHMITT_GRF_GPIO1A0_OFFSET 0x10188
1817 #define RV1126_SCHMITT_BANK_STRIDE 16
1818 #define RV1126_SCHMITT_PINS_PER_GRF_REG 8
1819 #define RV1126_SCHMITT_PINS_PER_PMU_REG 8
1820
rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1821 static int rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap,
1822 int *reg, u8 *bit)
1823 {
1824 struct rockchip_pinctrl *info = bank->drvdata;
1825 int pins_per_reg;
1826
1827 if (bank->bank_num == 0) {
1828 if (RV1126_GPIO_C4_D7(pin_num)) {
1829 *regmap = info->regmap_base;
1830 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
1831 *reg -= (((PINCTRL_ROCKCHIP_THIRTYONE - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + PINCTRL_ROCKCHIP_ONE) *
1832 PINCTRL_ROCKCHIP_FOUR);
1833 *bit = pin_num % RV1126_SCHMITT_PINS_PER_GRF_REG;
1834 return 0;
1835 }
1836 *regmap = info->regmap_pmu;
1837 *reg = RV1126_SCHMITT_PMU_OFFSET;
1838 pins_per_reg = RV1126_SCHMITT_PINS_PER_PMU_REG;
1839 } else {
1840 *regmap = info->regmap_base;
1841 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
1842 pins_per_reg = RV1126_SCHMITT_PINS_PER_GRF_REG;
1843 *reg += (bank->bank_num - PINCTRL_ROCKCHIP_ONE) * RV1126_SCHMITT_BANK_STRIDE;
1844 }
1845 *reg += ((pin_num / pins_per_reg) * PINCTRL_ROCKCHIP_FOUR);
1846 *bit = pin_num % pins_per_reg;
1847
1848 return 0;
1849 }
1850
1851 #define RK3308_SCHMITT_PINS_PER_REG 8
1852 #define RK3308_SCHMITT_BANK_STRIDE 16
1853 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0
1854
rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1855 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap,
1856 int *reg, u8 *bit)
1857 {
1858 struct rockchip_pinctrl *info = bank->drvdata;
1859
1860 *regmap = info->regmap_base;
1861 *reg = RK3308_SCHMITT_GRF_OFFSET;
1862
1863 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE;
1864 *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * PINCTRL_ROCKCHIP_FOUR);
1865 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG;
1866
1867 return 0;
1868 }
1869
1870 #define RK1808_PULL_PMU_OFFSET 0x10
1871 #define RK1808_PULL_GRF_OFFSET 0x80
1872 #define RK1808_PULL_PINS_PER_REG 8
1873 #define RK1808_PULL_BITS_PER_PIN 2
1874 #define RK1808_PULL_BANK_STRIDE 16
1875
rk1808_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1876 static void rk1808_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg,
1877 u8 *bit)
1878 {
1879 struct rockchip_pinctrl *info = bank->drvdata;
1880
1881 if (bank->bank_num == 0) {
1882 *regmap = info->regmap_pmu;
1883 *reg = RK1808_PULL_PMU_OFFSET;
1884 } else {
1885 *reg = RK1808_PULL_GRF_OFFSET;
1886 *regmap = info->regmap_base;
1887 *reg += (bank->bank_num - PINCTRL_ROCKCHIP_ONE) * RK1808_PULL_BANK_STRIDE;
1888 }
1889
1890 *reg += ((pin_num / RK1808_PULL_PINS_PER_REG) * PINCTRL_ROCKCHIP_FOUR);
1891 *bit = (pin_num % RK1808_PULL_PINS_PER_REG);
1892 *bit *= RK1808_PULL_BITS_PER_PIN;
1893 }
1894
1895 #define RK1808_DRV_PMU_OFFSET 0x20
1896 #define RK1808_DRV_GRF_OFFSET 0x140
1897 #define RK1808_DRV_BITS_PER_PIN 2
1898 #define RK1808_DRV_PINS_PER_REG 8
1899 #define RK1808_DRV_BANK_STRIDE 16
1900
rk1808_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1901 static void rk1808_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg,
1902 u8 *bit)
1903 {
1904 struct rockchip_pinctrl *info = bank->drvdata;
1905
1906 if (bank->bank_num == 0) {
1907 *regmap = info->regmap_pmu;
1908 *reg = RK1808_DRV_PMU_OFFSET;
1909 } else {
1910 *regmap = info->regmap_base;
1911 *reg = RK1808_DRV_GRF_OFFSET;
1912 *reg += (bank->bank_num - PINCTRL_ROCKCHIP_ONE) * RK1808_DRV_BANK_STRIDE;
1913 }
1914
1915 *reg += ((pin_num / RK1808_DRV_PINS_PER_REG) * PINCTRL_ROCKCHIP_FOUR);
1916 *bit = pin_num % RK1808_DRV_PINS_PER_REG;
1917 *bit *= RK1808_DRV_BITS_PER_PIN;
1918 }
1919
1920 #define RK1808_SR_PMU_OFFSET 0x0030
1921 #define RK1808_SR_GRF_OFFSET 0x00c0
1922 #define RK1808_SR_BANK_STRIDE 16
1923 #define RK1808_SR_PINS_PER_REG 8
1924
rk1808_calc_slew_rate_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1925 static int rk1808_calc_slew_rate_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap,
1926 int *reg, u8 *bit)
1927 {
1928 struct rockchip_pinctrl *info = bank->drvdata;
1929
1930 if (bank->bank_num == 0) {
1931 *regmap = info->regmap_pmu;
1932 *reg = RK1808_SR_PMU_OFFSET;
1933 } else {
1934 *regmap = info->regmap_base;
1935 *reg = RK1808_SR_GRF_OFFSET;
1936 *reg += (bank->bank_num - PINCTRL_ROCKCHIP_ONE) * RK1808_SR_BANK_STRIDE;
1937 }
1938 *reg += ((pin_num / RK1808_SR_PINS_PER_REG) * PINCTRL_ROCKCHIP_FOUR);
1939 *bit = pin_num % RK1808_SR_PINS_PER_REG;
1940
1941 return 0;
1942 }
1943
1944 #define RK1808_SCHMITT_PMU_OFFSET 0x0040
1945 #define RK1808_SCHMITT_GRF_OFFSET 0x0100
1946 #define RK1808_SCHMITT_BANK_STRIDE 16
1947 #define RK1808_SCHMITT_PINS_PER_REG 8
1948
rk1808_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1949 static int rk1808_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap,
1950 int *reg, u8 *bit)
1951 {
1952 struct rockchip_pinctrl *info = bank->drvdata;
1953
1954 if (bank->bank_num == 0) {
1955 *regmap = info->regmap_pmu;
1956 *reg = RK1808_SCHMITT_PMU_OFFSET;
1957 } else {
1958 *regmap = info->regmap_base;
1959 *reg = RK1808_SCHMITT_GRF_OFFSET;
1960 *reg += (bank->bank_num - PINCTRL_ROCKCHIP_ONE) * RK1808_SCHMITT_BANK_STRIDE;
1961 }
1962 *reg += ((pin_num / RK1808_SCHMITT_PINS_PER_REG) * PINCTRL_ROCKCHIP_FOUR);
1963 *bit = pin_num % RK1808_SCHMITT_PINS_PER_REG;
1964
1965 return 0;
1966 }
1967
1968 #define RK2928_PULL_OFFSET 0x118
1969 #define RK2928_PULL_PINS_PER_REG 16
1970 #define RK2928_PULL_BANK_STRIDE 8
1971
rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1972 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg,
1973 u8 *bit)
1974 {
1975 struct rockchip_pinctrl *info = bank->drvdata;
1976
1977 *regmap = info->regmap_base;
1978 *reg = RK2928_PULL_OFFSET;
1979 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1980 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * PINCTRL_ROCKCHIP_FOUR;
1981
1982 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1983 };
1984
1985 #define RK3128_PULL_OFFSET 0x118
1986
rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1987 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg,
1988 u8 *bit)
1989 {
1990 struct rockchip_pinctrl *info = bank->drvdata;
1991
1992 *regmap = info->regmap_base;
1993 *reg = RK3128_PULL_OFFSET;
1994 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1995 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * PINCTRL_ROCKCHIP_FOUR);
1996
1997 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1998 }
1999
2000 #define RK3188_PULL_OFFSET 0x164
2001 #define RK3188_PULL_BITS_PER_PIN 2
2002 #define RK3188_PULL_PINS_PER_REG 8
2003 #define RK3188_PULL_BANK_STRIDE 16
2004 #define RK3188_PULL_PMU_OFFSET 0x64
2005
rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2006 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg,
2007 u8 *bit)
2008 {
2009 struct rockchip_pinctrl *info = bank->drvdata;
2010
2011 /* The first 12 pins of the first bank are located elsewhere */
2012 if (bank->bank_num == 0 && pin_num < PINCTRL_ROCKCHIP_TWELVE) {
2013 *regmap = info->regmap_pmu ? info->regmap_pmu : bank->regmap_pull;
2014 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
2015 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * PINCTRL_ROCKCHIP_FOUR);
2016 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
2017 *bit *= RK3188_PULL_BITS_PER_PIN;
2018 } else {
2019 *regmap = info->regmap_pull ? info->regmap_pull : info->regmap_base;
2020 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
2021
2022 /* correct the offset, as it is the 2nd pull register */
2023 *reg -= PINCTRL_ROCKCHIP_FOUR;
2024 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2025 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * PINCTRL_ROCKCHIP_FOUR);
2026
2027 /*
2028 * The bits in these registers have an inverse ordering
2029 * with the lowest pin being in bits 15:14 and the highest
2030 * pin in bits 1:0
2031 */
2032 *bit = PINCTRL_ROCKCHIP_SEVEN - (pin_num % RK3188_PULL_PINS_PER_REG);
2033 *bit *= RK3188_PULL_BITS_PER_PIN;
2034 }
2035 }
2036
2037 #define RK3288_PULL_OFFSET 0x140
rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2038 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg,
2039 u8 *bit)
2040 {
2041 struct rockchip_pinctrl *info = bank->drvdata;
2042
2043 /* The first 24 pins of the first bank are located in PMU */
2044 if (bank->bank_num == 0) {
2045 *regmap = info->regmap_pmu;
2046 *reg = RK3188_PULL_PMU_OFFSET;
2047
2048 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * PINCTRL_ROCKCHIP_FOUR);
2049 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
2050 *bit *= RK3188_PULL_BITS_PER_PIN;
2051 } else {
2052 *regmap = info->regmap_base;
2053 *reg = RK3288_PULL_OFFSET;
2054
2055 /* correct the offset, as we're starting with the 2nd bank */
2056 *reg -= 0x10;
2057 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2058 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * PINCTRL_ROCKCHIP_FOUR);
2059
2060 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
2061 *bit *= RK3188_PULL_BITS_PER_PIN;
2062 }
2063 }
2064
2065 #define RK3288_DRV_PMU_OFFSET 0x70
2066 #define RK3288_DRV_GRF_OFFSET 0x1c0
2067 #define RK3288_DRV_BITS_PER_PIN 2
2068 #define RK3288_DRV_PINS_PER_REG 8
2069 #define RK3288_DRV_BANK_STRIDE 16
2070
rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2071 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg,
2072 u8 *bit)
2073 {
2074 struct rockchip_pinctrl *info = bank->drvdata;
2075
2076 /* The first 24 pins of the first bank are located in PMU */
2077 if (bank->bank_num == 0) {
2078 *regmap = info->regmap_pmu;
2079 *reg = RK3288_DRV_PMU_OFFSET;
2080
2081 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * PINCTRL_ROCKCHIP_FOUR);
2082 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
2083 *bit *= RK3288_DRV_BITS_PER_PIN;
2084 } else {
2085 *regmap = info->regmap_base;
2086 *reg = RK3288_DRV_GRF_OFFSET;
2087
2088 /* correct the offset, as we're starting with the 2nd bank */
2089 *reg -= 0x10;
2090 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
2091 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * PINCTRL_ROCKCHIP_FOUR);
2092
2093 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
2094 *bit *= RK3288_DRV_BITS_PER_PIN;
2095 }
2096 }
2097
2098 #define RK3228_PULL_OFFSET 0x100
2099
rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2100 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg,
2101 u8 *bit)
2102 {
2103 struct rockchip_pinctrl *info = bank->drvdata;
2104
2105 *regmap = info->regmap_base;
2106 *reg = RK3228_PULL_OFFSET;
2107 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2108 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * PINCTRL_ROCKCHIP_FOUR);
2109
2110 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
2111 *bit *= RK3188_PULL_BITS_PER_PIN;
2112 }
2113
2114 #define RK3228_DRV_GRF_OFFSET 0x200
2115
rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2116 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg,
2117 u8 *bit)
2118 {
2119 struct rockchip_pinctrl *info = bank->drvdata;
2120
2121 *regmap = info->regmap_base;
2122 *reg = RK3228_DRV_GRF_OFFSET;
2123 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
2124 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * PINCTRL_ROCKCHIP_FOUR);
2125
2126 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
2127 *bit *= RK3288_DRV_BITS_PER_PIN;
2128 }
2129
2130 #define RK3308_PULL_OFFSET 0xa0
2131
rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2132 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg,
2133 u8 *bit)
2134 {
2135 struct rockchip_pinctrl *info = bank->drvdata;
2136
2137 *regmap = info->regmap_base;
2138 *reg = RK3308_PULL_OFFSET;
2139 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2140 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * PINCTRL_ROCKCHIP_FOUR);
2141
2142 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
2143 *bit *= RK3188_PULL_BITS_PER_PIN;
2144 }
2145
2146 #define RK3308_DRV_GRF_OFFSET 0x100
2147
rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2148 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg,
2149 u8 *bit)
2150 {
2151 struct rockchip_pinctrl *info = bank->drvdata;
2152
2153 *regmap = info->regmap_base;
2154 *reg = RK3308_DRV_GRF_OFFSET;
2155 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
2156 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * PINCTRL_ROCKCHIP_FOUR);
2157
2158 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
2159 *bit *= RK3288_DRV_BITS_PER_PIN;
2160 }
2161
2162 #define RK3368_PULL_GRF_OFFSET 0x100
2163 #define RK3368_PULL_PMU_OFFSET 0x10
2164
rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2165 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg,
2166 u8 *bit)
2167 {
2168 struct rockchip_pinctrl *info = bank->drvdata;
2169
2170 /* The first 32 pins of the first bank are located in PMU */
2171 if (bank->bank_num == 0) {
2172 *regmap = info->regmap_pmu;
2173 *reg = RK3368_PULL_PMU_OFFSET;
2174
2175 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * PINCTRL_ROCKCHIP_FOUR);
2176 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
2177 *bit *= RK3188_PULL_BITS_PER_PIN;
2178 } else {
2179 *regmap = info->regmap_base;
2180 *reg = RK3368_PULL_GRF_OFFSET;
2181
2182 /* correct the offset, as we're starting with the 2nd bank */
2183 *reg -= 0x10;
2184 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2185 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * PINCTRL_ROCKCHIP_FOUR);
2186
2187 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
2188 *bit *= RK3188_PULL_BITS_PER_PIN;
2189 }
2190 }
2191
2192 #define RK3368_DRV_PMU_OFFSET 0x20
2193 #define RK3368_DRV_GRF_OFFSET 0x200
2194
rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2195 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg,
2196 u8 *bit)
2197 {
2198 struct rockchip_pinctrl *info = bank->drvdata;
2199
2200 /* The first 32 pins of the first bank are located in PMU */
2201 if (bank->bank_num == 0) {
2202 *regmap = info->regmap_pmu;
2203 *reg = RK3368_DRV_PMU_OFFSET;
2204
2205 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * PINCTRL_ROCKCHIP_FOUR);
2206 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
2207 *bit *= RK3288_DRV_BITS_PER_PIN;
2208 } else {
2209 *regmap = info->regmap_base;
2210 *reg = RK3368_DRV_GRF_OFFSET;
2211
2212 /* correct the offset, as we're starting with the 2nd bank */
2213 *reg -= 0x10;
2214 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
2215 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * PINCTRL_ROCKCHIP_FOUR);
2216
2217 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
2218 *bit *= RK3288_DRV_BITS_PER_PIN;
2219 }
2220 }
2221
2222 #define RK3399_PULL_GRF_OFFSET 0xe040
2223 #define RK3399_PULL_PMU_OFFSET 0x40
2224 #define RK3399_DRV_3BITS_PER_PIN 3
2225
rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2226 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg,
2227 u8 *bit)
2228 {
2229 struct rockchip_pinctrl *info = bank->drvdata;
2230
2231 /* The bank0:16 and bank1:32 pins are located in PMU */
2232 if ((bank->bank_num == 0) || (bank->bank_num == PINCTRL_ROCKCHIP_ONE)) {
2233 *regmap = info->regmap_pmu;
2234 *reg = RK3399_PULL_PMU_OFFSET;
2235
2236 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2237
2238 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * PINCTRL_ROCKCHIP_FOUR);
2239 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
2240 *bit *= RK3188_PULL_BITS_PER_PIN;
2241 } else {
2242 *regmap = info->regmap_base;
2243 *reg = RK3399_PULL_GRF_OFFSET;
2244
2245 /* correct the offset, as we're starting with the 3rd bank */
2246 *reg -= 0x20;
2247 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2248 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * PINCTRL_ROCKCHIP_FOUR);
2249
2250 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
2251 *bit *= RK3188_PULL_BITS_PER_PIN;
2252 }
2253 }
2254
rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2255 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg,
2256 u8 *bit)
2257 {
2258 struct rockchip_pinctrl *info = bank->drvdata;
2259 int drv_num = (pin_num / 8);
2260
2261 /* The bank0:16 and bank1:32 pins are located in PMU */
2262 if ((bank->bank_num == 0) || (bank->bank_num == PINCTRL_ROCKCHIP_ONE)) {
2263 *regmap = info->regmap_pmu;
2264 } else {
2265 *regmap = info->regmap_base;
2266 }
2267
2268 *reg = bank->drv[drv_num].offset;
2269 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
2270 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) {
2271 *bit = (pin_num % 0x8) * PINCTRL_ROCKCHIP_THREE;
2272 } else {
2273 *bit = (pin_num % 0x8) * 0x2;
2274 }
2275 }
2276
2277 #define RK3568_SR_PMU_OFFSET 0x60
2278 #define RK3568_SR_GRF_OFFSET 0x0180
2279 #define RK3568_SR_BANK_STRIDE 0x10
2280 #define RK3568_SR_PINS_PER_REG 16
2281
rk3568_calc_slew_rate_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2282 static int rk3568_calc_slew_rate_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap,
2283 int *reg, u8 *bit)
2284 {
2285 struct rockchip_pinctrl *info = bank->drvdata;
2286
2287 if (bank->bank_num == 0) {
2288 *regmap = info->regmap_pmu;
2289 *reg = RK3568_SR_PMU_OFFSET;
2290 } else {
2291 *regmap = info->regmap_base;
2292 *reg = RK3568_SR_GRF_OFFSET;
2293 *reg += (bank->bank_num - PINCTRL_ROCKCHIP_ONE) * RK3568_SR_BANK_STRIDE;
2294 }
2295 *reg += ((pin_num / RK3568_SR_PINS_PER_REG) * PINCTRL_ROCKCHIP_FOUR);
2296 *bit = pin_num % RK3568_SR_PINS_PER_REG;
2297
2298 return 0;
2299 }
2300
2301 #define RK3568_PULL_PMU_OFFSET 0x20
2302 #define RK3568_PULL_GRF_OFFSET 0x80
2303 #define RK3568_PULL_BITS_PER_PIN 2
2304 #define RK3568_PULL_PINS_PER_REG 8
2305 #define RK3568_PULL_BANK_STRIDE 0x10
2306
rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2307 static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg,
2308 u8 *bit)
2309 {
2310 struct rockchip_pinctrl *info = bank->drvdata;
2311
2312 if (bank->bank_num == 0) {
2313 *regmap = info->regmap_pmu;
2314 *reg = RK3568_PULL_PMU_OFFSET;
2315 *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE;
2316 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * PINCTRL_ROCKCHIP_FOUR);
2317
2318 *bit = pin_num % RK3568_PULL_PINS_PER_REG;
2319 *bit *= RK3568_PULL_BITS_PER_PIN;
2320 } else {
2321 *regmap = info->regmap_base;
2322 *reg = RK3568_PULL_GRF_OFFSET;
2323 *reg += (bank->bank_num - PINCTRL_ROCKCHIP_ONE) * RK3568_PULL_BANK_STRIDE;
2324 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * PINCTRL_ROCKCHIP_FOUR);
2325
2326 *bit = (pin_num % RK3568_PULL_PINS_PER_REG);
2327 *bit *= RK3568_PULL_BITS_PER_PIN;
2328 }
2329 }
2330
2331 #define RK3568_DRV_PMU_OFFSET 0x70
2332 #define RK3568_DRV_GRF_OFFSET 0x200
2333 #define RK3568_DRV_BITS_PER_PIN 8
2334 #define RK3568_DRV_PINS_PER_REG 2
2335 #define RK3568_DRV_BANK_STRIDE 0x40
2336
rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2337 static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg,
2338 u8 *bit)
2339 {
2340 struct rockchip_pinctrl *info = bank->drvdata;
2341
2342 /* The first 32 pins of the first bank are located in PMU */
2343 if (bank->bank_num == 0) {
2344 *regmap = info->regmap_pmu;
2345 *reg = RK3568_DRV_PMU_OFFSET;
2346 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * PINCTRL_ROCKCHIP_FOUR);
2347
2348 *bit = pin_num % RK3568_DRV_PINS_PER_REG;
2349 *bit *= RK3568_DRV_BITS_PER_PIN;
2350 } else {
2351 *regmap = info->regmap_base;
2352 *reg = RK3568_DRV_GRF_OFFSET;
2353 *reg += (bank->bank_num - PINCTRL_ROCKCHIP_ONE) * RK3568_DRV_BANK_STRIDE;
2354 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * PINCTRL_ROCKCHIP_FOUR);
2355
2356 *bit = (pin_num % RK3568_DRV_PINS_PER_REG);
2357 *bit *= RK3568_DRV_BITS_PER_PIN;
2358 }
2359
2360 if (rockchip_get_cpu_version() == 0) {
2361 if ((bank->bank_num == 1 && (pin_num == PINCTRL_ROCKCHIP_FIFTEEN || pin_num == PINCTRL_ROCKCHIP_TWENTYTHREE ||
2362 pin_num == PINCTRL_ROCKCHIP_THIRTYONE)) ||
2363 ((bank->bank_num == PINCTRL_ROCKCHIP_TWO || bank->bank_num == PINCTRL_ROCKCHIP_THREE ||
2364 bank->bank_num == PINCTRL_ROCKCHIP_FOUR) &&
2365 (pin_num == PINCTRL_ROCKCHIP_SEVEN || pin_num == PINCTRL_ROCKCHIP_FIFTEEN ||
2366 pin_num == PINCTRL_ROCKCHIP_TWENTYTHREE || pin_num == PINCTRL_ROCKCHIP_THIRTYONE))) {
2367 *bit -= RK3568_DRV_BITS_PER_PIN;
2368 }
2369 }
2370 }
2371
2372 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][PINCTRL_ROCKCHIP_EIGHT] = {
2373 {PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_TWELVE, -1, -1, -1, -1},
2374 {PINCTRL_ROCKCHIP_THREE, PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_NINE, PINCTRL_ROCKCHIP_TWELVE, -1, -1, -1, -1},
2375 {PINCTRL_ROCKCHIP_FIVE, PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_FIFTEEN, PINCTRL_ROCKCHIP_TWENTY, -1, -1, -1, -1},
2376 {PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_TWELVE,
2377 PINCTRL_ROCKCHIP_FOURTEEN, PINCTRL_ROCKCHIP_SIXTEEN, PINCTRL_ROCKCHIP_EIGHTEEN},
2378 {PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_SEVEN, PINCTRL_ROCKCHIP_TEN, PINCTRL_ROCKCHIP_THIRTEEN,
2379 PINCTRL_ROCKCHIP_SIXTEEN, PINCTRL_ROCKCHIP_NINTEEN, PINCTRL_ROCKCHIP_TWENTYTWO, PINCTRL_ROCKCHIP_TWENTYSIX}};
2380
rockchip_get_drive_perpin(struct rockchip_pin_bank * bank,int pin_num)2381 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, int pin_num)
2382 {
2383 struct rockchip_pinctrl *info = bank->drvdata;
2384 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2385 struct regmap *regmap;
2386 int reg, ret;
2387 u32 data, temp, rmask_bits;
2388 u8 bit;
2389 int drv_type = bank->drv[pin_num / 8].drv_type;
2390
2391 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
2392
2393 switch (drv_type) {
2394 case DRV_TYPE_IO_1V8_3V0_AUTO:
2395 case DRV_TYPE_IO_3V3_ONLY:
2396 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
2397 switch (bit) {
2398 case 0 ... PINCTRL_ROCKCHIP_TWELVE:
2399 /* regular case, nothing to do */
2400 break;
2401 case PINCTRL_ROCKCHIP_FIFTEEN:
2402 /*
2403 * drive-strength offset is special, as it is
2404 * spread over 2 registers
2405 */
2406 ret = regmap_read(regmap, reg, &data);
2407 if (ret) {
2408 return ret;
2409 }
2410
2411 ret = regmap_read(regmap, reg + 0x4, &temp);
2412 if (ret) {
2413 return ret;
2414 }
2415
2416 /*
2417 * the bit data[15] contains bit 0 of the value
2418 * while temp[1:0] contains bits 2 and 1
2419 */
2420 data >>= PINCTRL_ROCKCHIP_FIFTEEN;
2421 temp &= 0x3;
2422 temp <<= PINCTRL_ROCKCHIP_ONE;
2423 data |= temp;
2424
2425 return rockchip_perpin_drv_list[drv_type][data];
2426 case PINCTRL_ROCKCHIP_EIGHTEEN ... PINCTRL_ROCKCHIP_TWENTYONE:
2427 /* setting fully enclosed in the second register */
2428 reg += PINCTRL_ROCKCHIP_FOUR;
2429 bit -= PINCTRL_ROCKCHIP_SIXTEEN;
2430 break;
2431 default:
2432 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n", bit, drv_type);
2433 return -EINVAL;
2434 }
2435
2436 break;
2437 case DRV_TYPE_IO_DEFAULT:
2438 case DRV_TYPE_IO_1V8_OR_3V0:
2439 case DRV_TYPE_IO_1V8_ONLY:
2440 rmask_bits = RK3288_DRV_BITS_PER_PIN;
2441 break;
2442 default:
2443 dev_err(info->dev, "unsupported pinctrl drive type: %d\n", drv_type);
2444 return -EINVAL;
2445 }
2446
2447 ret = regmap_read(regmap, reg, &data);
2448 if (ret) {
2449 return ret;
2450 }
2451
2452 data >>= bit;
2453 data &= (PINCTRL_ROCKCHIP_ONE << rmask_bits) - PINCTRL_ROCKCHIP_ONE;
2454
2455 return rockchip_perpin_drv_list[drv_type][data];
2456 }
2457
rockchip_set_drive_perpin(struct rockchip_pin_bank * bank,int pin_num,int strength)2458 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, int pin_num, int strength)
2459 {
2460 struct rockchip_pinctrl *info = bank->drvdata;
2461 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2462 struct regmap *regmap;
2463 int reg, ret, i;
2464 u32 data, rmask, rmask_bits, temp;
2465 u8 bit;
2466 int drv_type = bank->drv[pin_num / 8].drv_type;
2467
2468 dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n", bank->bank_num, pin_num, strength);
2469
2470 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
2471 if (ctrl->type == RV1126) {
2472 rmask_bits = RV1126_DRV_BITS_PER_PIN;
2473 ret = strength;
2474 goto config;
2475 } else if (ctrl->type == RK3568) {
2476 rmask_bits = RK3568_DRV_BITS_PER_PIN;
2477 ret = (PINCTRL_ROCKCHIP_ONE << (strength + PINCTRL_ROCKCHIP_ONE)) - PINCTRL_ROCKCHIP_ONE;
2478 goto config;
2479 }
2480
2481 ret = -EINVAL;
2482 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
2483 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
2484 ret = i;
2485 break;
2486 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
2487 ret = rockchip_perpin_drv_list[drv_type][i];
2488 break;
2489 }
2490 }
2491
2492 if (ret < 0) {
2493 dev_err(info->dev, "unsupported driver strength %d\n", strength);
2494 return ret;
2495 }
2496
2497 switch (drv_type) {
2498 case DRV_TYPE_IO_1V8_3V0_AUTO:
2499 case DRV_TYPE_IO_3V3_ONLY:
2500 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
2501 switch (bit) {
2502 case 0 ... PINCTRL_ROCKCHIP_TWELVE:
2503 /* regular case, nothing to do */
2504 break;
2505 case PINCTRL_ROCKCHIP_FIFTEEN:
2506 /*
2507 * drive-strength offset is special, as it is spread
2508 * over 2 registers, the bit data[15] contains bit 0
2509 * of the value while temp[1:0] contains bits 2 and 1
2510 */
2511 data = (ret & 0x1) << PINCTRL_ROCKCHIP_FIFTEEN;
2512 temp = (ret >> 0x1) & 0x3;
2513
2514 rmask = BIT(PINCTRL_ROCKCHIP_FIFTEEN) | BIT(PINCTRL_ROCKCHIP_THIRTYONE);
2515 data |= BIT(PINCTRL_ROCKCHIP_THIRTYONE);
2516 ret = regmap_update_bits(regmap, reg, rmask, data);
2517 if (ret) {
2518 return ret;
2519 }
2520
2521 rmask = 0x3 | (0x3 << PINCTRL_ROCKCHIP_SIXTEEN);
2522 temp |= (0x3 << PINCTRL_ROCKCHIP_SIXTEEN);
2523 reg += 0x4;
2524 ret = regmap_update_bits(regmap, reg, rmask, temp);
2525
2526 return ret;
2527 case PINCTRL_ROCKCHIP_EIGHTEEN ... PINCTRL_ROCKCHIP_TWENTYONE:
2528 /* setting fully enclosed in the second register */
2529 reg += PINCTRL_ROCKCHIP_FOUR;
2530 bit -= PINCTRL_ROCKCHIP_SIXTEEN;
2531 break;
2532 default:
2533 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n", bit, drv_type);
2534 return -EINVAL;
2535 }
2536 break;
2537 case DRV_TYPE_IO_DEFAULT:
2538 case DRV_TYPE_IO_1V8_OR_3V0:
2539 case DRV_TYPE_IO_1V8_ONLY:
2540 rmask_bits = RK3288_DRV_BITS_PER_PIN;
2541 break;
2542 default:
2543 dev_err(info->dev, "unsupported pinctrl drive type: %d\n", drv_type);
2544 return -EINVAL;
2545 }
2546
2547 config:
2548 /* enable the write to the equivalent lower bits */
2549 data = ((PINCTRL_ROCKCHIP_ONE << rmask_bits) - PINCTRL_ROCKCHIP_ONE) << (bit + PINCTRL_ROCKCHIP_SIXTEEN);
2550 rmask = data | (data >> PINCTRL_ROCKCHIP_SIXTEEN);
2551 data |= (ret << bit);
2552
2553 ret = regmap_update_bits(regmap, reg, rmask, data);
2554 if (ret) {
2555 return ret;
2556 }
2557
2558 if (ctrl->type == RK3568 && rockchip_get_cpu_version() == 0) {
2559 if (bank->bank_num == 1 && pin_num == PINCTRL_ROCKCHIP_TWENTYONE) {
2560 reg = 0x0840;
2561 } else if (bank->bank_num == PINCTRL_ROCKCHIP_TWO && pin_num == PINCTRL_ROCKCHIP_TWO) {
2562 reg = 0x0844;
2563 } else if (bank->bank_num == PINCTRL_ROCKCHIP_TWO && pin_num == PINCTRL_ROCKCHIP_EIGHT) {
2564 reg = 0x0848;
2565 } else if (bank->bank_num == PINCTRL_ROCKCHIP_THREE && pin_num == 0) {
2566 reg = 0x084c;
2567 } else if (bank->bank_num == PINCTRL_ROCKCHIP_THREE && pin_num == PINCTRL_ROCKCHIP_SIX) {
2568 reg = 0x0850;
2569 } else if (bank->bank_num == PINCTRL_ROCKCHIP_FOUR && pin_num == 0) {
2570 reg = 0x0854;
2571 } else {
2572 return 0;
2573 }
2574
2575 data = ((PINCTRL_ROCKCHIP_ONE << rmask_bits) - PINCTRL_ROCKCHIP_ONE) << PINCTRL_ROCKCHIP_SIXTEEN;
2576 rmask = data | (data >> PINCTRL_ROCKCHIP_SIXTEEN);
2577 data |= (PINCTRL_ROCKCHIP_ONE << (strength + PINCTRL_ROCKCHIP_ONE)) - PINCTRL_ROCKCHIP_ONE;
2578
2579 ret = regmap_update_bits(regmap, reg, rmask, data);
2580 if (ret) {
2581 return ret;
2582 }
2583 }
2584
2585 return 0;
2586 }
2587
2588 static int rockchip_pull_list[PULL_TYPE_MAX][PINCTRL_ROCKCHIP_FOUR] = {
2589 {PIN_CONFIG_BIAS_DISABLE, PIN_CONFIG_BIAS_PULL_UP, PIN_CONFIG_BIAS_PULL_DOWN, PIN_CONFIG_BIAS_BUS_HOLD},
2590 {PIN_CONFIG_BIAS_DISABLE, PIN_CONFIG_BIAS_PULL_DOWN, PIN_CONFIG_BIAS_DISABLE, PIN_CONFIG_BIAS_PULL_UP},
2591 };
2592
rockchip_get_pull(struct rockchip_pin_bank * bank,int pin_num)2593 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
2594 {
2595 struct rockchip_pinctrl *info = bank->drvdata;
2596 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2597 struct regmap *regmap;
2598 int reg, ret, pull_type;
2599 u8 bit;
2600 u32 data;
2601
2602 /* rk3066b does support any pulls */
2603 if (ctrl->type == RK3066B) {
2604 return PIN_CONFIG_BIAS_DISABLE;
2605 }
2606
2607 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
2608
2609 ret = regmap_read(regmap, reg, &data);
2610 if (ret) {
2611 return ret;
2612 }
2613
2614 switch (ctrl->type) {
2615 case RK2928:
2616 case RK3128:
2617 return !(data & BIT(bit)) ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT : PIN_CONFIG_BIAS_DISABLE;
2618 case PX30:
2619 case RV1108:
2620 case RV1126:
2621 case RK1808:
2622 case RK3188:
2623 case RK3288:
2624 case RK3308:
2625 case RK3368:
2626 case RK3399:
2627 case RK3568:
2628 pull_type = bank->pull_type[pin_num / 0x8];
2629 data >>= bit;
2630 data &= (PINCTRL_ROCKCHIP_ONE << RK3188_PULL_BITS_PER_PIN) - PINCTRL_ROCKCHIP_ONE;
2631
2632 return rockchip_pull_list[pull_type][data];
2633 default:
2634 dev_err(info->dev, "unsupported pinctrl type\n");
2635 return -EINVAL;
2636 };
2637 }
2638
rockchip_set_pull(struct rockchip_pin_bank * bank,int pin_num,int pull)2639 static int rockchip_set_pull(struct rockchip_pin_bank *bank, int pin_num, int pull)
2640 {
2641 struct rockchip_pinctrl *info = bank->drvdata;
2642 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2643 struct regmap *regmap;
2644 int reg, ret, i, pull_type;
2645 u8 bit;
2646 u32 data, rmask;
2647
2648 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n", bank->bank_num, pin_num, pull);
2649
2650 /* rk3066b does support any pulls */
2651 if (ctrl->type == RK3066B) {
2652 return pull ? -EINVAL : 0;
2653 }
2654
2655 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
2656
2657 switch (ctrl->type) {
2658 case RK2928:
2659 case RK3128:
2660 data = BIT(bit + PINCTRL_ROCKCHIP_SIXTEEN);
2661 if (pull == PIN_CONFIG_BIAS_DISABLE) {
2662 data |= BIT(bit);
2663 }
2664 ret = regmap_write(regmap, reg, data);
2665 break;
2666 case PX30:
2667 case RV1108:
2668 case RV1126:
2669 case RK1808:
2670 case RK3188:
2671 case RK3288:
2672 case RK3308:
2673 case RK3368:
2674 case RK3399:
2675 case RK3568:
2676 pull_type = bank->pull_type[pin_num / PINCTRL_ROCKCHIP_EIGHT];
2677 ret = -EINVAL;
2678 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); i++) {
2679 if (rockchip_pull_list[pull_type][i] == pull) {
2680 ret = i;
2681 break;
2682 }
2683 }
2684 /*
2685 * In the TRM, pull-up being 1 for everything except the GPIO0_D0-D6,
2686 * where that pull up value becomes 3.
2687 */
2688 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= PINCTRL_ROCKCHIP_TWENTYSEVEN &&
2689 pin_num <= PINCTRL_ROCKCHIP_THIRTY) {
2690 if (ret == PINCTRL_ROCKCHIP_ONE) {
2691 ret = PINCTRL_ROCKCHIP_THREE;
2692 }
2693 }
2694
2695 if (ret < 0) {
2696 dev_err(info->dev, "unsupported pull setting %d\n", pull);
2697 return ret;
2698 }
2699
2700 /* enable the write to the equivalent lower bits */
2701 data = ((1 << RK3188_PULL_BITS_PER_PIN) - PINCTRL_ROCKCHIP_ONE) << (bit + PINCTRL_ROCKCHIP_SIXTEEN);
2702 rmask = data | (data >> PINCTRL_ROCKCHIP_SIXTEEN);
2703 data |= (ret << bit);
2704
2705 ret = regmap_update_bits(regmap, reg, rmask, data);
2706 break;
2707 default:
2708 dev_err(info->dev, "unsupported pinctrl type\n");
2709 return -EINVAL;
2710 }
2711
2712 return ret;
2713 }
2714
2715 #define RK3328_SCHMITT_BITS_PER_PIN 1
2716 #define RK3328_SCHMITT_PINS_PER_REG 16
2717 #define RK3328_SCHMITT_BANK_STRIDE 8
2718 #define RK3328_SCHMITT_GRF_OFFSET 0x380
2719
rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2720 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap,
2721 int *reg, u8 *bit)
2722 {
2723 struct rockchip_pinctrl *info = bank->drvdata;
2724
2725 *regmap = info->regmap_base;
2726 *reg = RK3328_SCHMITT_GRF_OFFSET;
2727
2728 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
2729 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * PINCTRL_ROCKCHIP_FOUR);
2730 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
2731
2732 return 0;
2733 }
2734
2735 #define RK3568_SCHMITT_BITS_PER_PIN 2
2736 #define RK3568_SCHMITT_PINS_PER_REG 8
2737 #define RK3568_SCHMITT_BANK_STRIDE 0x10
2738 #define RK3568_SCHMITT_GRF_OFFSET 0xc0
2739 #define RK3568_SCHMITT_PMUGRF_OFFSET 0x30
2740
rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2741 static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap,
2742 int *reg, u8 *bit)
2743 {
2744 struct rockchip_pinctrl *info = bank->drvdata;
2745
2746 if (bank->bank_num == 0) {
2747 *regmap = info->regmap_pmu;
2748 *reg = RK3568_SCHMITT_PMUGRF_OFFSET;
2749 } else {
2750 *regmap = info->regmap_base;
2751 *reg = RK3568_SCHMITT_GRF_OFFSET;
2752 *reg += (bank->bank_num - PINCTRL_ROCKCHIP_ONE) * RK3568_SCHMITT_BANK_STRIDE;
2753 }
2754
2755 *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * PINCTRL_ROCKCHIP_FOUR);
2756 *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG;
2757 *bit *= RK3568_SCHMITT_BITS_PER_PIN;
2758
2759 return 0;
2760 }
2761
rockchip_get_schmitt(struct rockchip_pin_bank * bank,int pin_num)2762 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
2763 {
2764 struct rockchip_pinctrl *info = bank->drvdata;
2765 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2766 struct regmap *regmap;
2767 int reg, ret;
2768 u8 bit;
2769 u32 data;
2770
2771 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
2772 if (ret) {
2773 return ret;
2774 }
2775
2776 ret = regmap_read(regmap, reg, &data);
2777 if (ret) {
2778 return ret;
2779 }
2780
2781 data >>= bit;
2782 switch (ctrl->type) {
2783 case RK3568:
2784 return data & ((PINCTRL_ROCKCHIP_ONE << RK3568_SCHMITT_BITS_PER_PIN) - PINCTRL_ROCKCHIP_ONE);
2785 default:
2786 break;
2787 }
2788
2789 return data & 0x1;
2790 }
2791
rockchip_set_schmitt(struct rockchip_pin_bank * bank,int pin_num,int enable)2792 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, int pin_num, int enable)
2793 {
2794 struct rockchip_pinctrl *info = bank->drvdata;
2795 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2796 struct regmap *regmap;
2797 int reg, ret;
2798 u8 bit;
2799 u32 data, rmask;
2800
2801 dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num, pin_num, enable);
2802
2803 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
2804 if (ret) {
2805 return ret;
2806 }
2807
2808 /* enable the write to the equivalent lower bits */
2809 switch (ctrl->type) {
2810 case RK3568:
2811 data = ((PINCTRL_ROCKCHIP_ONE << RK3568_SCHMITT_BITS_PER_PIN) - PINCTRL_ROCKCHIP_ONE)
2812 << (bit + PINCTRL_ROCKCHIP_SIXTEEN);
2813 rmask = data | (data >> PINCTRL_ROCKCHIP_SIXTEEN);
2814 data |= ((enable ? 0x2 : 0x1) << bit);
2815 break;
2816 default:
2817 data = BIT(bit + PINCTRL_ROCKCHIP_SIXTEEN) | (enable << bit);
2818 rmask = BIT(bit + PINCTRL_ROCKCHIP_SIXTEEN) | BIT(bit);
2819 break;
2820 }
2821
2822 return regmap_update_bits(regmap, reg, rmask, data);
2823 }
2824
2825 #define PX30_SLEW_RATE_PMU_OFFSET 0x30
2826 #define PX30_SLEW_RATE_GRF_OFFSET 0x90
2827 #define PX30_SLEW_RATE_PINS_PER_PMU_REG 16
2828 #define PX30_SLEW_RATE_BANK_STRIDE 16
2829 #define PX30_SLEW_RATE_PINS_PER_GRF_REG 8
2830
px30_calc_slew_rate_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2831 static int px30_calc_slew_rate_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap,
2832 int *reg, u8 *bit)
2833 {
2834 struct rockchip_pinctrl *info = bank->drvdata;
2835 int pins_per_reg;
2836
2837 if (bank->bank_num == 0) {
2838 *regmap = info->regmap_pmu;
2839 *reg = PX30_SLEW_RATE_PMU_OFFSET;
2840 pins_per_reg = PX30_SLEW_RATE_PINS_PER_PMU_REG;
2841 } else {
2842 *regmap = info->regmap_base;
2843 *reg = PX30_SLEW_RATE_GRF_OFFSET;
2844 pins_per_reg = PX30_SLEW_RATE_PINS_PER_GRF_REG;
2845 *reg += (bank->bank_num - PINCTRL_ROCKCHIP_ONE) * PX30_SLEW_RATE_BANK_STRIDE;
2846 }
2847 *reg += ((pin_num / pins_per_reg) * PINCTRL_ROCKCHIP_FOUR);
2848 *bit = pin_num % pins_per_reg;
2849
2850 return 0;
2851 }
2852
rockchip_get_slew_rate(struct rockchip_pin_bank * bank,int pin_num)2853 static int rockchip_get_slew_rate(struct rockchip_pin_bank *bank, int pin_num)
2854 {
2855 struct rockchip_pinctrl *info = bank->drvdata;
2856 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2857 struct regmap *regmap;
2858 int reg, ret;
2859 u8 bit;
2860 u32 data;
2861
2862 ret = ctrl->slew_rate_calc_reg(bank, pin_num, ®map, ®, &bit);
2863 if (ret) {
2864 return ret;
2865 }
2866
2867 ret = regmap_read(regmap, reg, &data);
2868 if (ret) {
2869 return ret;
2870 }
2871
2872 data >>= bit;
2873 return data & 0x1;
2874 }
2875
rockchip_set_slew_rate(struct rockchip_pin_bank * bank,int pin_num,int speed)2876 static int rockchip_set_slew_rate(struct rockchip_pin_bank *bank, int pin_num, int speed)
2877 {
2878 struct rockchip_pinctrl *info = bank->drvdata;
2879 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2880 struct regmap *regmap;
2881 int reg, ret;
2882 u8 bit;
2883 u32 data, rmask;
2884
2885 dev_dbg(info->dev, "setting slew rate of GPIO%d-%d to %d\n", bank->bank_num, pin_num, speed);
2886
2887 ret = ctrl->slew_rate_calc_reg(bank, pin_num, ®map, ®, &bit);
2888 if (ret) {
2889 return ret;
2890 }
2891
2892 /* enable the write to the equivalent lower bits */
2893 data = BIT(bit + PINCTRL_ROCKCHIP_SIXTEEN) | (speed << bit);
2894 rmask = BIT(bit + PINCTRL_ROCKCHIP_SIXTEEN) | BIT(bit);
2895
2896 return regmap_update_bits(regmap, reg, rmask, data);
2897 }
2898
2899 /*
2900 * Pinmux_ops handling
2901 */
2902
rockchip_pmx_get_funcs_count(struct pinctrl_dev * pctldev)2903 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
2904 {
2905 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2906
2907 return info->nfunctions;
2908 }
2909
rockchip_pmx_get_func_name(struct pinctrl_dev * pctldev,unsigned selector)2910 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev, unsigned selector)
2911 {
2912 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2913
2914 return info->functions[selector].name;
2915 }
2916
rockchip_pmx_get_groups(struct pinctrl_dev * pctldev,unsigned selector,const char * const ** groups,unsigned * const num_groups)2917 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, const char *const **groups,
2918 unsigned *const num_groups)
2919 {
2920 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2921
2922 *groups = info->functions[selector].groups;
2923 *num_groups = info->functions[selector].ngroups;
2924
2925 return 0;
2926 }
2927
rockchip_pmx_set(struct pinctrl_dev * pctldev,unsigned selector,unsigned group)2928 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, unsigned group)
2929 {
2930 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2931 const unsigned int *pins = info->groups[group].pins;
2932 const struct rockchip_pin_config *data = info->groups[group].data;
2933 struct rockchip_pin_bank *bank;
2934 int cnt, ret = 0;
2935
2936 dev_dbg(info->dev, "enable function %s group %s\n", info->functions[selector].name, info->groups[group].name);
2937
2938 /*
2939 * for each pin in the pin group selected, program the corresponding
2940 * pin function number in the config register.
2941 */
2942 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
2943 bank = pin_to_bank(info, pins[cnt]);
2944 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, data[cnt].func);
2945 if (ret) {
2946 break;
2947 }
2948 }
2949
2950 if (ret && cnt) {
2951 /* revert the already done pin settings */
2952 for (cnt--; cnt >= 0 && !data[cnt].func; cnt--) {
2953 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
2954 }
2955
2956 return ret;
2957 }
2958
2959 return 0;
2960 }
2961
2962 static const struct pinmux_ops rockchip_pmx_ops = {
2963 .get_functions_count = rockchip_pmx_get_funcs_count,
2964 .get_function_name = rockchip_pmx_get_func_name,
2965 .get_function_groups = rockchip_pmx_get_groups,
2966 .set_mux = rockchip_pmx_set,
2967 };
2968
2969 /*
2970 * Pinconf_ops handling
2971 */
2972
rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl * ctrl,enum pin_config_param pull)2973 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, enum pin_config_param pull)
2974 {
2975 switch (ctrl->type) {
2976 case RK2928:
2977 case RK3128:
2978 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || pull == PIN_CONFIG_BIAS_DISABLE);
2979 case RK3066B:
2980 return pull ? false : true;
2981 case PX30:
2982 case RV1108:
2983 case RV1126:
2984 case RK1808:
2985 case RK3188:
2986 case RK3288:
2987 case RK3308:
2988 case RK3368:
2989 case RK3399:
2990 case RK3568:
2991 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
2992 }
2993
2994 return false;
2995 }
2996
2997 /* set the pin config settings for a specified pin */
rockchip_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned num_configs)2998 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *configs,
2999 unsigned num_configs)
3000 {
3001 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
3002 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
3003 struct gpio_chip *gpio = &bank->gpio_chip;
3004 enum pin_config_param param;
3005 u32 arg;
3006 int i;
3007 int rc;
3008
3009 for (i = 0; i < num_configs; i++) {
3010 param = pinconf_to_config_param(configs[i]);
3011 arg = pinconf_to_config_argument(configs[i]);
3012
3013 switch (param) {
3014 case PIN_CONFIG_BIAS_DISABLE:
3015 rc = rockchip_set_pull(bank, pin - bank->pin_base, param);
3016 if (rc) {
3017 return rc;
3018 }
3019 break;
3020 case PIN_CONFIG_BIAS_PULL_UP:
3021 case PIN_CONFIG_BIAS_PULL_DOWN:
3022 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
3023 case PIN_CONFIG_BIAS_BUS_HOLD:
3024 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) {
3025 return -ENOTSUPP;
3026 }
3027
3028 if (!arg) {
3029 return -EINVAL;
3030 }
3031
3032 rc = rockchip_set_pull(bank, pin - bank->pin_base, param);
3033 if (rc) {
3034 return rc;
3035 }
3036 break;
3037 case PIN_CONFIG_OUTPUT:
3038 rc = rockchip_get_mux(bank, pin - bank->pin_base);
3039 if (rc != 0) {
3040 dev_err(info->dev, "pin-%d has been mux to func%d\n", pin, rc);
3041 return -EINVAL;
3042 }
3043
3044 rc = gpio->direction_output(gpio, pin - bank->pin_base, arg);
3045 if (rc) {
3046 return rc;
3047 }
3048 break;
3049 case PIN_CONFIG_DRIVE_STRENGTH:
3050 /* rk3288 is the first with per-pin drive-strength */
3051 if (!info->ctrl->drv_calc_reg) {
3052 return -ENOTSUPP;
3053 }
3054
3055 rc = rockchip_set_drive_perpin(bank, pin - bank->pin_base, arg);
3056 if (rc < 0) {
3057 return rc;
3058 }
3059 break;
3060 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
3061 if (!info->ctrl->schmitt_calc_reg) {
3062 return -ENOTSUPP;
3063 }
3064
3065 rc = rockchip_set_schmitt(bank, pin - bank->pin_base, arg);
3066 if (rc < 0) {
3067 return rc;
3068 }
3069 break;
3070 case PIN_CONFIG_SLEW_RATE:
3071 if (!info->ctrl->slew_rate_calc_reg) {
3072 return -ENOTSUPP;
3073 }
3074
3075 rc = rockchip_set_slew_rate(bank, pin - bank->pin_base, arg);
3076 if (rc < 0) {
3077 return rc;
3078 }
3079 break;
3080 default:
3081 return -ENOTSUPP;
3082 }
3083 } /* for each config */
3084
3085 return 0;
3086 }
3087
3088 /* get the pin config settings for a specified pin */
rockchip_pinconf_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)3089 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *config)
3090 {
3091 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
3092 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
3093 struct gpio_chip *gpio = &bank->gpio_chip;
3094 enum pin_config_param param = pinconf_to_config_param(*config);
3095 u16 arg;
3096 int rc;
3097
3098 switch (param) {
3099 case PIN_CONFIG_BIAS_DISABLE:
3100 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) {
3101 return -EINVAL;
3102 }
3103
3104 arg = 0;
3105 break;
3106 case PIN_CONFIG_BIAS_PULL_UP:
3107 case PIN_CONFIG_BIAS_PULL_DOWN:
3108 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
3109 case PIN_CONFIG_BIAS_BUS_HOLD:
3110 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) {
3111 return -ENOTSUPP;
3112 }
3113
3114 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) {
3115 return -EINVAL;
3116 }
3117
3118 arg = PINCTRL_ROCKCHIP_ONE;
3119 break;
3120 case PIN_CONFIG_OUTPUT:
3121 rc = rockchip_get_mux(bank, pin - bank->pin_base);
3122 if (rc != 0) {
3123 dev_err(info->dev, "pin-%d has been mux to func%d\n", pin, rc);
3124 return -EINVAL;
3125 }
3126
3127 rc = gpio->get(gpio, pin - bank->pin_base);
3128 if (rc < 0) {
3129 return rc;
3130 }
3131
3132 arg = rc ? 1 : 0;
3133 break;
3134 case PIN_CONFIG_DRIVE_STRENGTH:
3135 /* rk3288 is the first with per-pin drive-strength */
3136 if (!info->ctrl->drv_calc_reg) {
3137 return -ENOTSUPP;
3138 }
3139
3140 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
3141 if (rc < 0) {
3142 return rc;
3143 }
3144
3145 arg = rc;
3146 break;
3147 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
3148 if (!info->ctrl->schmitt_calc_reg) {
3149 return -ENOTSUPP;
3150 }
3151
3152 rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
3153 if (rc < 0) {
3154 return rc;
3155 }
3156
3157 arg = rc;
3158 break;
3159 case PIN_CONFIG_SLEW_RATE:
3160 if (!info->ctrl->slew_rate_calc_reg) {
3161 return -ENOTSUPP;
3162 }
3163
3164 rc = rockchip_get_slew_rate(bank, pin - bank->pin_base);
3165 if (rc < 0) {
3166 return rc;
3167 }
3168
3169 arg = rc;
3170 break;
3171 default:
3172 return -ENOTSUPP;
3173 }
3174
3175 *config = pinconf_to_config_packed(param, arg);
3176
3177 return 0;
3178 }
3179
3180 static const struct pinconf_ops rockchip_pinconf_ops = {
3181 .pin_config_get = rockchip_pinconf_get,
3182 .pin_config_set = rockchip_pinconf_set,
3183 .is_generic = true,
3184 };
3185
3186 static const struct of_device_id rockchip_bank_match[] = {
3187 {.compatible = "rockchip,gpio-bank"},
3188 {.compatible = "rockchip,rk3188-gpio-bank0"},
3189 {},
3190 };
3191
rockchip_pinctrl_child_count(struct rockchip_pinctrl * info,struct device_node * np)3192 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info, struct device_node *np)
3193 {
3194 struct device_node *child;
3195
3196 for_each_child_of_node(np, child)
3197 {
3198 if (of_match_node(rockchip_bank_match, child)) {
3199 continue;
3200 }
3201
3202 info->nfunctions++;
3203 info->ngroups += of_get_child_count(child);
3204 }
3205 }
3206
rockchip_pinctrl_parse_groups(struct device_node * np,struct rockchip_pin_group * grp,struct rockchip_pinctrl * info,u32 index)3207 static int rockchip_pinctrl_parse_groups(struct device_node *np, struct rockchip_pin_group *grp,
3208 struct rockchip_pinctrl *info, u32 index)
3209 {
3210 struct rockchip_pin_bank *bank;
3211 int size;
3212 const __be32 *list;
3213 int num;
3214 int i, j;
3215 int ret;
3216
3217 dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
3218
3219 /* Initialise group */
3220 grp->name = np->name;
3221
3222 /*
3223 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
3224 * do sanity check and calculate pins number
3225 */
3226 list = of_get_property(np, "rockchip,pins", &size);
3227 /* we do not check return since it's safe node passed down */
3228 size /= sizeof(*list);
3229 if (!size || size % PINCTRL_ROCKCHIP_FOUR) {
3230 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
3231 return -EINVAL;
3232 }
3233
3234 grp->npins = size / PINCTRL_ROCKCHIP_FOUR;
3235
3236 grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int), GFP_KERNEL);
3237 grp->data = devm_kcalloc(info->dev, grp->npins, sizeof(struct rockchip_pin_config), GFP_KERNEL);
3238 if (!grp->pins || !grp->data) {
3239 return -ENOMEM;
3240 }
3241
3242 for (i = 0, j = 0; i < size; i += PINCTRL_ROCKCHIP_FOUR, j++) {
3243 const __be32 *phandle;
3244 struct device_node *np_config;
3245
3246 num = be32_to_cpu(*list++);
3247 bank = bank_num_to_bank(info, num);
3248 if (IS_ERR(bank)) {
3249 return PTR_ERR(bank);
3250 }
3251
3252 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
3253 grp->data[j].func = be32_to_cpu(*list++);
3254
3255 phandle = list++;
3256 if (!phandle) {
3257 return -EINVAL;
3258 }
3259
3260 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
3261 ret = pinconf_generic_parse_dt_config(np_config, NULL, &grp->data[j].configs, &grp->data[j].nconfigs);
3262 if (ret) {
3263 return ret;
3264 }
3265 }
3266
3267 return 0;
3268 }
3269
rockchip_pinctrl_parse_functions(struct device_node * np,struct rockchip_pinctrl * info,u32 index)3270 static int rockchip_pinctrl_parse_functions(struct device_node *np, struct rockchip_pinctrl *info, u32 index)
3271 {
3272 struct device_node *child;
3273 struct rockchip_pmx_func *func;
3274 struct rockchip_pin_group *grp;
3275 int ret;
3276 static u32 grp_index;
3277 u32 i = 0;
3278
3279 dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
3280
3281 func = &info->functions[index];
3282
3283 /* Initialise function */
3284 func->name = np->name;
3285 func->ngroups = of_get_child_count(np);
3286 if (func->ngroups <= 0) {
3287 return 0;
3288 }
3289
3290 func->groups = devm_kcalloc(info->dev, func->ngroups, sizeof(char *), GFP_KERNEL);
3291 if (!func->groups) {
3292 return -ENOMEM;
3293 }
3294
3295 for_each_child_of_node(np, child)
3296 {
3297 func->groups[i] = child->name;
3298 grp = &info->groups[grp_index++];
3299 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
3300 if (ret) {
3301 of_node_put(child);
3302 return ret;
3303 }
3304 }
3305
3306 return 0;
3307 }
3308
rockchip_pinctrl_parse_dt(struct platform_device * pdev,struct rockchip_pinctrl * info)3309 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, struct rockchip_pinctrl *info)
3310 {
3311 struct device *dev = &pdev->dev;
3312 struct device_node *np = dev->of_node;
3313 struct device_node *child;
3314 int ret;
3315 int i;
3316
3317 rockchip_pinctrl_child_count(info, np);
3318
3319 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
3320 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
3321
3322 info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(struct rockchip_pmx_func), GFP_KERNEL);
3323 if (!info->functions) {
3324 return -ENOMEM;
3325 }
3326
3327 info->groups = devm_kcalloc(dev, info->ngroups, sizeof(struct rockchip_pin_group), GFP_KERNEL);
3328 if (!info->groups) {
3329 return -ENOMEM;
3330 }
3331
3332 i = 0;
3333
3334 for_each_child_of_node(np, child)
3335 {
3336 if (of_match_node(rockchip_bank_match, child)) {
3337 continue;
3338 }
3339
3340 ret = rockchip_pinctrl_parse_functions(child, info, i++);
3341 if (ret) {
3342 dev_err(&pdev->dev, "failed to parse function\n");
3343 of_node_put(child);
3344 return ret;
3345 }
3346 }
3347
3348 return 0;
3349 }
3350
rockchip_pinctrl_register(struct platform_device * pdev,struct rockchip_pinctrl * info)3351 static int rockchip_pinctrl_register(struct platform_device *pdev, struct rockchip_pinctrl *info)
3352 {
3353 struct pinctrl_desc *ctrldesc = &info->pctl;
3354 struct pinctrl_pin_desc *pindesc, *pdesc;
3355 struct rockchip_pin_bank *pin_bank;
3356 int pin, bank, ret;
3357 int k;
3358
3359 ctrldesc->name = "rockchip-pinctrl";
3360 ctrldesc->owner = THIS_MODULE;
3361 ctrldesc->pctlops = &rockchip_pctrl_ops;
3362 ctrldesc->pmxops = &rockchip_pmx_ops;
3363 ctrldesc->confops = &rockchip_pinconf_ops;
3364
3365 pindesc = devm_kcalloc(&pdev->dev, info->ctrl->nr_pins, sizeof(*pindesc), GFP_KERNEL);
3366 if (!pindesc) {
3367 return -ENOMEM;
3368 }
3369
3370 ctrldesc->pins = pindesc;
3371 ctrldesc->npins = info->ctrl->nr_pins;
3372
3373 pdesc = pindesc;
3374 for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) {
3375 pin_bank = &info->ctrl->pin_banks[bank];
3376 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
3377 pdesc->number = k;
3378 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d", pin_bank->name, pin);
3379 pdesc++;
3380 }
3381 }
3382
3383 ret = rockchip_pinctrl_parse_dt(pdev, info);
3384 if (ret) {
3385 return ret;
3386 }
3387
3388 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
3389 if (IS_ERR(info->pctl_dev)) {
3390 dev_err(&pdev->dev, "could not register pinctrl driver\n");
3391 return PTR_ERR(info->pctl_dev);
3392 }
3393
3394 return 0;
3395 }
3396
3397 static const struct of_device_id rockchip_pinctrl_dt_match[];
3398
3399 /* retrieve the soc specific data */
rockchip_pinctrl_get_soc_data(struct rockchip_pinctrl * d,struct platform_device * pdev)3400 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct rockchip_pinctrl *d, struct platform_device *pdev)
3401 {
3402 const struct of_device_id *match;
3403 struct device_node *node = pdev->dev.of_node;
3404 struct rockchip_pin_ctrl *ctrl;
3405 struct rockchip_pin_bank *bank;
3406 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
3407
3408 match = of_match_node(rockchip_pinctrl_dt_match, node);
3409 ctrl = (struct rockchip_pin_ctrl *)match->data;
3410
3411 grf_offs = ctrl->grf_mux_offset;
3412 pmu_offs = ctrl->pmu_mux_offset;
3413 drv_pmu_offs = ctrl->pmu_drv_offset;
3414 drv_grf_offs = ctrl->grf_drv_offset;
3415 bank = ctrl->pin_banks;
3416 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3417 int bank_pins = 0;
3418
3419 raw_spin_lock_init(&bank->slock);
3420 bank->drvdata = d;
3421 bank->pin_base = ctrl->nr_pins;
3422 ctrl->nr_pins += bank->nr_pins;
3423
3424 /* calculate iomux and drv offsets */
3425 for (j = 0; j < PINCTRL_ROCKCHIP_FOUR; j++) {
3426 struct rockchip_iomux *iom = &bank->iomux[j];
3427 struct rockchip_drv *drv = &bank->drv[j];
3428 int inc;
3429
3430 if (bank_pins >= bank->nr_pins) {
3431 break;
3432 }
3433
3434 /* preset iomux offset value, set new start value */
3435 if (iom->offset >= 0) {
3436 if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU)) {
3437 pmu_offs = iom->offset;
3438 } else {
3439 grf_offs = iom->offset;
3440 }
3441 } else { /* set current iomux offset */
3442 iom->offset =
3443 ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU)) ? pmu_offs : grf_offs;
3444 }
3445
3446 /* preset drv offset value, set new start value */
3447 if (drv->offset >= 0) {
3448 if (iom->type & IOMUX_SOURCE_PMU) {
3449 drv_pmu_offs = drv->offset;
3450 } else {
3451 drv_grf_offs = drv->offset;
3452 }
3453 } else { /* set current drv offset */
3454 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? drv_pmu_offs : drv_grf_offs;
3455 }
3456
3457 dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", i, j, iom->offset, drv->offset);
3458
3459 /*
3460 * Increase offset according to iomux width.
3461 * 4bit iomux'es are spread over two registers.
3462 */
3463 inc = (iom->type & (IOMUX_WIDTH_4BIT | IOMUX_WIDTH_3BIT | IOMUX_WIDTH_2BIT)) ? PINCTRL_ROCKCHIP_EIGHT
3464 : PINCTRL_ROCKCHIP_FOUR;
3465 if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU)) {
3466 pmu_offs += inc;
3467 } else {
3468 grf_offs += inc;
3469 }
3470
3471 /*
3472 * Increase offset according to drv width.
3473 * 3bit drive-strenth'es are spread over two registers.
3474 */
3475 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) {
3476 inc = PINCTRL_ROCKCHIP_EIGHT;
3477 } else {
3478 inc = PINCTRL_ROCKCHIP_FOUR;
3479 }
3480
3481 if (iom->type & IOMUX_SOURCE_PMU) {
3482 drv_pmu_offs += inc;
3483 } else {
3484 drv_grf_offs += inc;
3485 }
3486
3487 bank_pins += PINCTRL_ROCKCHIP_EIGHT;
3488 }
3489
3490 /* calculate the per-bank recalced_mask */
3491 for (j = 0; j < ctrl->niomux_recalced; j++) {
3492 int pin = 0;
3493
3494 if (ctrl->iomux_recalced[j].num == bank->bank_num) {
3495 pin = ctrl->iomux_recalced[j].pin;
3496 bank->recalced_mask |= BIT(pin);
3497 }
3498 }
3499
3500 /* calculate the per-bank route_mask */
3501 for (j = 0; j < ctrl->niomux_routes; j++) {
3502 int pin = 0;
3503
3504 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
3505 pin = ctrl->iomux_routes[j].pin;
3506 bank->route_mask |= BIT(pin);
3507 }
3508 }
3509 }
3510
3511 return ctrl;
3512 }
3513
3514 #define RK3288_GRF_GPIO6C_IOMUX 0x64
3515 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
3516
3517 static u32 rk3288_grf_gpio6c_iomux;
3518
rockchip_pinctrl_suspend(struct device * dev)3519 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
3520 {
3521 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3522 int ret = pinctrl_force_sleep(info->pctl_dev);
3523
3524 if (ret) {
3525 return ret;
3526 }
3527
3528 /*
3529 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
3530 * the setting here, and restore it at resume.
3531 */
3532 if (info->ctrl->type == RK3288) {
3533 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, &rk3288_grf_gpio6c_iomux);
3534 if (ret) {
3535 pinctrl_force_default(info->pctl_dev);
3536 return ret;
3537 }
3538 }
3539
3540 return 0;
3541 }
3542
rockchip_pinctrl_resume(struct device * dev)3543 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
3544 {
3545 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3546 int ret;
3547
3548 if (info->ctrl->type == RK3288) {
3549 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3550 rk3288_grf_gpio6c_iomux | GPIO6C6_SEL_WRITE_ENABLE);
3551 if (ret) {
3552 return ret;
3553 }
3554 }
3555
3556 return pinctrl_force_default(info->pctl_dev);
3557 }
3558
3559 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend, rockchip_pinctrl_resume);
3560
3561 /* SoC data specially handle */
3562
3563 /* rk3308 SoC data initialize */
3564 #define RK3308_GRF_SOC_CON13 0x608
3565 #define RK3308_GRF_SOC_CON15 0x610
3566
3567 /* RK3308_GRF_SOC_CON13 */
3568 #define RK3308_GRF_I2C3_IOFUNC_SRC_CTRL \
3569 (BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_TEN) | BIT(PINCTRL_ROCKCHIP_TEN))
3570 #define RK3308_GRF_GPIO2A3_SEL_SRC_CTRL \
3571 (BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_SEVEN) | BIT(PINCTRL_ROCKCHIP_SEVEN))
3572 #define RK3308_GRF_GPIO2A2_SEL_SRC_CTRL \
3573 (BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_THREE) | BIT(PINCTRL_ROCKCHIP_THREE))
3574
3575 /* RK3308_GRF_SOC_CON15 */
3576 #define RK3308_GRF_GPIO2C0_SEL_SRC_CTRL \
3577 (BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_ELEVEN) | BIT(PINCTRL_ROCKCHIP_ELEVEN))
3578 #define RK3308_GRF_GPIO3B3_SEL_SRC_CTRL \
3579 (BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_SEVEN) | BIT(PINCTRL_ROCKCHIP_SEVEN))
3580 #define RK3308_GRF_GPIO3B2_SEL_SRC_CTRL \
3581 (BIT(PINCTRL_ROCKCHIP_SIXTEEN + PINCTRL_ROCKCHIP_THREE) | BIT(PINCTRL_ROCKCHIP_THREE))
3582
rk3308_soc_data_init(struct rockchip_pinctrl * info)3583 static int rk3308_soc_data_init(struct rockchip_pinctrl *info)
3584 {
3585 int ret;
3586
3587 /*
3588 * Enable the special ctrl of selected sources.
3589 */
3590
3591 ret = regmap_write(info->regmap_base, RK3308_GRF_SOC_CON13,
3592 RK3308_GRF_I2C3_IOFUNC_SRC_CTRL | RK3308_GRF_GPIO2A3_SEL_SRC_CTRL |
3593 RK3308_GRF_GPIO2A2_SEL_SRC_CTRL);
3594 if (ret) {
3595 return ret;
3596 }
3597
3598 ret = regmap_write(info->regmap_base, RK3308_GRF_SOC_CON15,
3599 RK3308_GRF_GPIO2C0_SEL_SRC_CTRL | RK3308_GRF_GPIO3B3_SEL_SRC_CTRL |
3600 RK3308_GRF_GPIO3B2_SEL_SRC_CTRL);
3601
3602 return ret;
3603 }
3604
rockchip_pinctrl_probe(struct platform_device * pdev)3605 static int rockchip_pinctrl_probe(struct platform_device *pdev)
3606 {
3607 struct rockchip_pinctrl *info;
3608 struct device *dev = &pdev->dev;
3609 struct rockchip_pin_ctrl *ctrl;
3610 struct device_node *np = pdev->dev.of_node, *node;
3611 struct resource *res;
3612 void __iomem *base;
3613 int ret;
3614
3615 if (!dev->of_node) {
3616 dev_err(dev, "device tree node not found\n");
3617 return -ENODEV;
3618 }
3619
3620 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
3621 if (!info) {
3622 return -ENOMEM;
3623 }
3624
3625 info->dev = dev;
3626
3627 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
3628 if (!ctrl) {
3629 dev_err(dev, "driver data not available\n");
3630 return -EINVAL;
3631 }
3632 info->ctrl = ctrl;
3633
3634 node = of_parse_phandle(np, "rockchip,grf", 0);
3635 if (node) {
3636 info->regmap_base = syscon_node_to_regmap(node);
3637 of_node_put(node);
3638 if (IS_ERR(info->regmap_base)) {
3639 return PTR_ERR(info->regmap_base);
3640 }
3641 } else {
3642 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3643 base = devm_ioremap_resource(&pdev->dev, res);
3644 if (IS_ERR(base)) {
3645 return PTR_ERR(base);
3646 }
3647
3648 rockchip_regmap_config.max_register = resource_size(res) - PINCTRL_ROCKCHIP_FOUR;
3649 rockchip_regmap_config.name = "rockchip,pinctrl";
3650 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base, &rockchip_regmap_config);
3651
3652 /* to check for the old dt-bindings */
3653 info->reg_size = resource_size(res);
3654
3655 /* Honor the old binding, with pull registers as 2nd resource */
3656 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
3657 res = platform_get_resource(pdev, IORESOURCE_MEM, PINCTRL_ROCKCHIP_ONE);
3658 base = devm_ioremap_resource(&pdev->dev, res);
3659 if (IS_ERR(base)) {
3660 return PTR_ERR(base);
3661 }
3662
3663 rockchip_regmap_config.max_register = resource_size(res) - PINCTRL_ROCKCHIP_FOUR;
3664 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
3665 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev, base, &rockchip_regmap_config);
3666 }
3667 }
3668
3669 /* try to find the optional reference to the pmu syscon */
3670 node = of_parse_phandle(np, "rockchip,pmu", 0);
3671 if (node) {
3672 info->regmap_pmu = syscon_node_to_regmap(node);
3673 of_node_put(node);
3674 if (IS_ERR(info->regmap_pmu)) {
3675 return PTR_ERR(info->regmap_pmu);
3676 }
3677 }
3678
3679 /* Special handle for some Socs */
3680 if (ctrl->soc_data_init) {
3681 ret = ctrl->soc_data_init(info);
3682 if (ret) {
3683 return ret;
3684 }
3685 }
3686
3687 ret = rockchip_pinctrl_register(pdev, info);
3688 if (ret) {
3689 return ret;
3690 }
3691
3692 platform_set_drvdata(pdev, info);
3693
3694 ret = of_platform_populate(np, rockchip_bank_match, NULL, NULL);
3695 if (ret) {
3696 dev_err(&pdev->dev, "failed to register gpio device\n");
3697 return ret;
3698 }
3699 dev_info(dev, "probed %s\n", dev_name(dev));
3700
3701 return 0;
3702 }
3703
3704 static struct rockchip_pin_bank px30_pin_banks[] = {
3705 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio0", IOMUX_SOURCE_PMU, IOMUX_SOURCE_PMU,
3706 IOMUX_SOURCE_PMU, IOMUX_SOURCE_PMU),
3707 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_ONE, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio1", IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT,
3708 IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT),
3709 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio2", IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT,
3710 IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT),
3711 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_THREE, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio3", IOMUX_WIDTH_4BIT,
3712 IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT),
3713 };
3714
3715 static struct rockchip_pin_ctrl px30_pin_ctrl = {
3716 .pin_banks = px30_pin_banks,
3717 .nr_banks = ARRAY_SIZE(px30_pin_banks),
3718 .label = "PX30-GPIO",
3719 .type = PX30,
3720 .grf_mux_offset = 0x0,
3721 .pmu_mux_offset = 0x0,
3722 .iomux_routes = px30_mux_route_data,
3723 .niomux_routes = ARRAY_SIZE(px30_mux_route_data),
3724 .pull_calc_reg = px30_calc_pull_reg_and_bit,
3725 .drv_calc_reg = px30_calc_drv_reg_and_bit,
3726 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit,
3727 .slew_rate_calc_reg = px30_calc_slew_rate_reg_and_bit,
3728 };
3729
3730 static struct rockchip_pin_bank rv1108_pin_banks[] = {
3731 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio0", IOMUX_SOURCE_PMU, IOMUX_SOURCE_PMU,
3732 IOMUX_SOURCE_PMU, IOMUX_SOURCE_PMU),
3733 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_ONE, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio1", 0, 0, 0, 0),
3734 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio2", 0, 0, 0, 0),
3735 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_THREE, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio3", 0, 0, 0, 0),
3736 };
3737
3738 static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
3739 .pin_banks = rv1108_pin_banks,
3740 .nr_banks = ARRAY_SIZE(rv1108_pin_banks),
3741 .label = "RV1108-GPIO",
3742 .type = RV1108,
3743 .grf_mux_offset = 0x10,
3744 .pmu_mux_offset = 0x0,
3745 .iomux_recalced = rv1108_mux_recalced_data,
3746 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data),
3747 .pull_calc_reg = rv1108_calc_pull_reg_and_bit,
3748 .drv_calc_reg = rv1108_calc_drv_reg_and_bit,
3749 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
3750 };
3751
3752 static struct rockchip_pin_bank rv1126_pin_banks[] = {
3753 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio0",
3754 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
3755 IOMUX_WIDTH_4BIT | IOMUX_L_SOURCE_PMU, IOMUX_WIDTH_4BIT),
3756 PIN_BANK_IOMUX_FLAGS_OFFSET(PINCTRL_ROCKCHIP_ONE, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio1", IOMUX_WIDTH_4BIT,
3757 IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT, 0x10010, 0x10018, 0x10020,
3758 0x10028),
3759 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio2", IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT,
3760 IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT),
3761 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_THREE, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio3", IOMUX_WIDTH_4BIT,
3762 IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT),
3763 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_TWO, "gpio4", IOMUX_WIDTH_4BIT, 0, 0, 0),
3764 };
3765
3766 static struct rockchip_pin_ctrl rv1126_pin_ctrl = {
3767 .pin_banks = rv1126_pin_banks,
3768 .nr_banks = ARRAY_SIZE(rv1126_pin_banks),
3769 .label = "RV1126-GPIO",
3770 .type = RV1126,
3771 .grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */
3772 .pmu_mux_offset = 0x0,
3773 .iomux_routes = rv1126_mux_route_data,
3774 .niomux_routes = ARRAY_SIZE(rv1126_mux_route_data),
3775 .iomux_recalced = rv1126_mux_recalced_data,
3776 .niomux_recalced = ARRAY_SIZE(rv1126_mux_recalced_data),
3777 .pull_calc_reg = rv1126_calc_pull_reg_and_bit,
3778 .drv_calc_reg = rv1126_calc_drv_reg_and_bit,
3779 .schmitt_calc_reg = rv1126_calc_schmitt_reg_and_bit,
3780 };
3781
3782 static struct rockchip_pin_bank rk1808_pin_banks[] = {
3783 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio0", IOMUX_SOURCE_PMU, IOMUX_SOURCE_PMU,
3784 IOMUX_SOURCE_PMU, IOMUX_SOURCE_PMU),
3785 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_ONE, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio1", IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT,
3786 IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT),
3787 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio2", IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT,
3788 IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT),
3789 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_THREE, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio3", IOMUX_WIDTH_4BIT,
3790 IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT),
3791 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio4", IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT,
3792 IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT),
3793 };
3794
3795 static struct rockchip_pin_ctrl rk1808_pin_ctrl = {
3796 .pin_banks = rk1808_pin_banks,
3797 .nr_banks = ARRAY_SIZE(rk1808_pin_banks),
3798 .label = "RK1808-GPIO",
3799 .type = RK1808,
3800 .iomux_routes = rk1808_mux_route_data,
3801 .niomux_routes = ARRAY_SIZE(rk1808_mux_route_data),
3802 .grf_mux_offset = 0x0,
3803 .pmu_mux_offset = 0x0,
3804 .pull_calc_reg = rk1808_calc_pull_reg_and_bit,
3805 .drv_calc_reg = rk1808_calc_drv_reg_and_bit,
3806 .schmitt_calc_reg = rk1808_calc_schmitt_reg_and_bit,
3807 .slew_rate_calc_reg = rk1808_calc_slew_rate_reg_and_bit,
3808 };
3809
3810 static struct rockchip_pin_bank rk2928_pin_banks[] = {
3811 PIN_BANK(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio0"),
3812 PIN_BANK(PINCTRL_ROCKCHIP_ONE, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio1"),
3813 PIN_BANK(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio2"),
3814 PIN_BANK(PINCTRL_ROCKCHIP_THREE, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio3"),
3815 };
3816
3817 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
3818 .pin_banks = rk2928_pin_banks,
3819 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
3820 .label = "RK2928-GPIO",
3821 .type = RK2928,
3822 .grf_mux_offset = 0xa8,
3823 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3824 };
3825
3826 static struct rockchip_pin_bank rk3036_pin_banks[] = {
3827 PIN_BANK(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio0"),
3828 PIN_BANK(PINCTRL_ROCKCHIP_ONE, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio1"),
3829 PIN_BANK(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio2"),
3830 };
3831
3832 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
3833 .pin_banks = rk3036_pin_banks,
3834 .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
3835 .label = "RK3036-GPIO",
3836 .type = RK2928,
3837 .grf_mux_offset = 0xa8,
3838 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3839 };
3840
3841 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
3842 PIN_BANK(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio0"),
3843 PIN_BANK(PINCTRL_ROCKCHIP_ONE, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio1"),
3844 PIN_BANK(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio2"),
3845 PIN_BANK(PINCTRL_ROCKCHIP_THREE, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio3"),
3846 PIN_BANK(PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio4"),
3847 PIN_BANK(PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_SIXTEEN, "gpio6"),
3848 };
3849
3850 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
3851 .pin_banks = rk3066a_pin_banks,
3852 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
3853 .label = "RK3066a-GPIO",
3854 .type = RK2928,
3855 .grf_mux_offset = 0xa8,
3856 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3857 };
3858
3859 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
3860 PIN_BANK(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio0"),
3861 PIN_BANK(PINCTRL_ROCKCHIP_ONE, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio1"),
3862 PIN_BANK(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio2"),
3863 PIN_BANK(PINCTRL_ROCKCHIP_THREE, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio3"),
3864 };
3865
3866 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
3867 .pin_banks = rk3066b_pin_banks,
3868 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
3869 .label = "RK3066b-GPIO",
3870 .type = RK3066B,
3871 .grf_mux_offset = 0x60,
3872 };
3873
3874 static struct rockchip_pin_bank rk3128_pin_banks[] = {
3875 PIN_BANK(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio0"),
3876 PIN_BANK(PINCTRL_ROCKCHIP_ONE, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio1"),
3877 PIN_BANK(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio2"),
3878 PIN_BANK(PINCTRL_ROCKCHIP_THREE, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio3"),
3879 };
3880
3881 static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
3882 .pin_banks = rk3128_pin_banks,
3883 .nr_banks = ARRAY_SIZE(rk3128_pin_banks),
3884 .label = "RK3128-GPIO",
3885 .type = RK3128,
3886 .grf_mux_offset = 0xa8,
3887 .iomux_recalced = rk3128_mux_recalced_data,
3888 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data),
3889 .iomux_routes = rk3128_mux_route_data,
3890 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
3891 .pull_calc_reg = rk3128_calc_pull_reg_and_bit,
3892 };
3893
3894 static struct rockchip_pin_bank rk3188_pin_banks[] = {
3895 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
3896 PIN_BANK(PINCTRL_ROCKCHIP_ONE, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio1"),
3897 PIN_BANK(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio2"),
3898 PIN_BANK(PINCTRL_ROCKCHIP_THREE, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio3"),
3899 };
3900
3901 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
3902 .pin_banks = rk3188_pin_banks,
3903 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
3904 .label = "RK3188-GPIO",
3905 .type = RK3188,
3906 .grf_mux_offset = 0x60,
3907 .iomux_routes = rk3188_mux_route_data,
3908 .niomux_routes = ARRAY_SIZE(rk3188_mux_route_data),
3909 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
3910 };
3911
3912 static struct rockchip_pin_bank rk3228_pin_banks[] = {
3913 PIN_BANK(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio0"),
3914 PIN_BANK(PINCTRL_ROCKCHIP_ONE, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio1"),
3915 PIN_BANK(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio2"),
3916 PIN_BANK(PINCTRL_ROCKCHIP_THREE, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio3"),
3917 };
3918
3919 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
3920 .pin_banks = rk3228_pin_banks,
3921 .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
3922 .label = "RK3228-GPIO",
3923 .type = RK3288,
3924 .grf_mux_offset = 0x0,
3925 .iomux_routes = rk3228_mux_route_data,
3926 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data),
3927 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
3928 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
3929 };
3930
3931 static struct rockchip_pin_bank rk3288_pin_banks[] = {
3932 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_TWENTYFOUR, "gpio0",
3933 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT,
3934 IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT, IOMUX_UNROUTED),
3935 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_ONE, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio1", IOMUX_UNROUTED, IOMUX_UNROUTED,
3936 IOMUX_UNROUTED, 0),
3937 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
3938 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_THREE, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
3939 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio4", IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT,
3940 0, 0),
3941 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_FIVE, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio5", IOMUX_UNROUTED, 0, 0,
3942 IOMUX_UNROUTED),
3943 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_SIX, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
3944 PIN_BANK_IOMUX_FLAGS(7, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio7", 0, 0, IOMUX_WIDTH_4BIT, IOMUX_UNROUTED),
3945 PIN_BANK(PINCTRL_ROCKCHIP_EIGHT, PINCTRL_ROCKCHIP_SIXTEEN, "gpio8"),
3946 };
3947
3948 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
3949 .pin_banks = rk3288_pin_banks,
3950 .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
3951 .label = "RK3288-GPIO",
3952 .type = RK3288,
3953 .grf_mux_offset = 0x0,
3954 .pmu_mux_offset = 0x84,
3955 .iomux_routes = rk3288_mux_route_data,
3956 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data),
3957 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
3958 .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
3959 };
3960
3961 static struct rockchip_pin_bank rk3308_pin_banks[] = {
3962 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio0", IOMUX_WIDTH_2BIT, IOMUX_WIDTH_2BIT,
3963 IOMUX_WIDTH_2BIT, IOMUX_WIDTH_2BIT),
3964 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_ONE, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio1", IOMUX_WIDTH_2BIT, IOMUX_WIDTH_2BIT,
3965 IOMUX_WIDTH_2BIT, IOMUX_WIDTH_2BIT),
3966 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio2", IOMUX_WIDTH_2BIT, IOMUX_WIDTH_2BIT,
3967 IOMUX_WIDTH_2BIT, IOMUX_WIDTH_2BIT),
3968 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_THREE, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio3", IOMUX_WIDTH_2BIT,
3969 IOMUX_WIDTH_2BIT, IOMUX_WIDTH_2BIT, IOMUX_WIDTH_2BIT),
3970 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio4", IOMUX_WIDTH_2BIT, IOMUX_WIDTH_2BIT,
3971 IOMUX_WIDTH_2BIT, IOMUX_WIDTH_2BIT),
3972 };
3973
3974 static struct rockchip_pin_ctrl rk3308_pin_ctrl = {
3975 .pin_banks = rk3308_pin_banks,
3976 .nr_banks = ARRAY_SIZE(rk3308_pin_banks),
3977 .label = "RK3308-GPIO",
3978 .type = RK3308,
3979 .grf_mux_offset = 0x0,
3980 .iomux_recalced = rk3308_mux_recalced_data,
3981 .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data),
3982 .iomux_routes = rk3308_mux_route_data,
3983 .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data),
3984 .soc_data_init = rk3308_soc_data_init,
3985 .pull_calc_reg = rk3308_calc_pull_reg_and_bit,
3986 .drv_calc_reg = rk3308_calc_drv_reg_and_bit,
3987 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit,
3988 };
3989
3990 static struct rockchip_pin_bank rk3328_pin_banks[] = {
3991 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio0", 0, 0, 0, 0),
3992 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_ONE, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio1", 0, 0, 0, 0),
3993 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio2", 0, IOMUX_WIDTH_3BIT,
3994 IOMUX_WIDTH_3BIT, 0),
3995 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_THREE, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio3", IOMUX_WIDTH_3BIT,
3996 IOMUX_WIDTH_3BIT, 0, 0),
3997 };
3998
3999 static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
4000 .pin_banks = rk3328_pin_banks,
4001 .nr_banks = ARRAY_SIZE(rk3328_pin_banks),
4002 .label = "RK3328-GPIO",
4003 .type = RK3288,
4004 .grf_mux_offset = 0x0,
4005 .iomux_recalced = rk3328_mux_recalced_data,
4006 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
4007 .iomux_routes = rk3328_mux_route_data,
4008 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
4009 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
4010 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
4011 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
4012 };
4013
4014 static struct rockchip_pin_bank rk3368_pin_banks[] = {
4015 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio0", IOMUX_SOURCE_PMU, IOMUX_SOURCE_PMU,
4016 IOMUX_SOURCE_PMU, IOMUX_SOURCE_PMU),
4017 PIN_BANK(PINCTRL_ROCKCHIP_ONE, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio1"),
4018 PIN_BANK(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio2"),
4019 PIN_BANK(PINCTRL_ROCKCHIP_THREE, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio3"),
4020 };
4021
4022 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
4023 .pin_banks = rk3368_pin_banks,
4024 .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
4025 .label = "RK3368-GPIO",
4026 .type = RK3368,
4027 .grf_mux_offset = 0x0,
4028 .pmu_mux_offset = 0x0,
4029 .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
4030 .drv_calc_reg = rk3368_calc_drv_reg_and_bit,
4031 };
4032
4033 static struct rockchip_pin_bank rk3399_pin_banks[] = {
4034 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(
4035 PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio0", IOMUX_SOURCE_PMU, IOMUX_SOURCE_PMU,
4036 IOMUX_SOURCE_PMU, IOMUX_SOURCE_PMU, DRV_TYPE_IO_1V8_ONLY, DRV_TYPE_IO_1V8_ONLY, DRV_TYPE_IO_DEFAULT,
4037 DRV_TYPE_IO_DEFAULT, 0x80, 0x88, -1, -1, PULL_TYPE_IO_1V8_ONLY, PULL_TYPE_IO_1V8_ONLY, PULL_TYPE_IO_DEFAULT,
4038 PULL_TYPE_IO_DEFAULT),
4039 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(PINCTRL_ROCKCHIP_ONE, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio1", IOMUX_SOURCE_PMU,
4040 IOMUX_SOURCE_PMU, IOMUX_SOURCE_PMU, IOMUX_SOURCE_PMU, DRV_TYPE_IO_1V8_OR_3V0,
4041 DRV_TYPE_IO_1V8_OR_3V0, DRV_TYPE_IO_1V8_OR_3V0, DRV_TYPE_IO_1V8_OR_3V0, 0xa0, 0xa8,
4042 0xb0, 0xb8),
4043 PIN_BANK_DRV_FLAGS_PULL_FLAGS(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
4044 DRV_TYPE_IO_1V8_OR_3V0, DRV_TYPE_IO_1V8_ONLY, DRV_TYPE_IO_1V8_ONLY,
4045 PULL_TYPE_IO_DEFAULT, PULL_TYPE_IO_DEFAULT, PULL_TYPE_IO_1V8_ONLY,
4046 PULL_TYPE_IO_1V8_ONLY),
4047 PIN_BANK_DRV_FLAGS(PINCTRL_ROCKCHIP_THREE, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio3", DRV_TYPE_IO_3V3_ONLY,
4048 DRV_TYPE_IO_3V3_ONLY, DRV_TYPE_IO_3V3_ONLY, DRV_TYPE_IO_1V8_OR_3V0),
4049 PIN_BANK_DRV_FLAGS(PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
4050 DRV_TYPE_IO_1V8_3V0_AUTO, DRV_TYPE_IO_1V8_OR_3V0, DRV_TYPE_IO_1V8_OR_3V0),
4051 };
4052
4053 static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
4054 .pin_banks = rk3399_pin_banks,
4055 .nr_banks = ARRAY_SIZE(rk3399_pin_banks),
4056 .label = "RK3399-GPIO",
4057 .type = RK3399,
4058 .grf_mux_offset = 0xe000,
4059 .pmu_mux_offset = 0x0,
4060 .grf_drv_offset = 0xe100,
4061 .pmu_drv_offset = 0x80,
4062 .iomux_routes = rk3399_mux_route_data,
4063 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data),
4064 .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
4065 .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
4066 };
4067
4068 static struct rockchip_pin_bank rk3568_pin_banks[] = {
4069 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_ZERO, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio0",
4070 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
4071 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT),
4072 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_ONE, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio1", IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT,
4073 IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT),
4074 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_TWO, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio2", IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT,
4075 IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT),
4076 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_THREE, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio3", IOMUX_WIDTH_4BIT,
4077 IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT),
4078 PIN_BANK_IOMUX_FLAGS(PINCTRL_ROCKCHIP_FOUR, PINCTRL_ROCKCHIP_THIRTYTWO, "gpio4", IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT,
4079 IOMUX_WIDTH_4BIT, IOMUX_WIDTH_4BIT),
4080 };
4081
4082 static struct rockchip_pin_ctrl rk3568_pin_ctrl = {
4083 .pin_banks = rk3568_pin_banks,
4084 .nr_banks = ARRAY_SIZE(rk3568_pin_banks),
4085 .label = "RK3568-GPIO",
4086 .type = RK3568,
4087 .grf_mux_offset = 0x0,
4088 .pmu_mux_offset = 0x0,
4089 .grf_drv_offset = 0x0200,
4090 .pmu_drv_offset = 0x0070,
4091 .iomux_routes = rk3568_mux_route_data,
4092 .niomux_routes = ARRAY_SIZE(rk3568_mux_route_data),
4093 .pull_calc_reg = rk3568_calc_pull_reg_and_bit,
4094 .drv_calc_reg = rk3568_calc_drv_reg_and_bit,
4095 .slew_rate_calc_reg = rk3568_calc_slew_rate_reg_and_bit,
4096 .schmitt_calc_reg = rk3568_calc_schmitt_reg_and_bit,
4097 };
4098
4099 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
4100 {.compatible = "rockchip,px30-pinctrl", .data = &px30_pin_ctrl},
4101 {.compatible = "rockchip,rv1108-pinctrl", .data = &rv1108_pin_ctrl},
4102 {.compatible = "rockchip,rv1126-pinctrl", .data = &rv1126_pin_ctrl},
4103 {.compatible = "rockchip,rk1808-pinctrl", .data = &rk1808_pin_ctrl},
4104 {.compatible = "rockchip,rk2928-pinctrl", .data = &rk2928_pin_ctrl},
4105 {.compatible = "rockchip,rk3036-pinctrl", .data = &rk3036_pin_ctrl},
4106 {.compatible = "rockchip,rk3066a-pinctrl", .data = &rk3066a_pin_ctrl},
4107 {.compatible = "rockchip,rk3066b-pinctrl", .data = &rk3066b_pin_ctrl},
4108 {.compatible = "rockchip,rk3128-pinctrl", .data = (void *)&rk3128_pin_ctrl},
4109 {.compatible = "rockchip,rk3188-pinctrl", .data = &rk3188_pin_ctrl},
4110 {.compatible = "rockchip,rk3228-pinctrl", .data = &rk3228_pin_ctrl},
4111 {.compatible = "rockchip,rk3288-pinctrl", .data = &rk3288_pin_ctrl},
4112 {.compatible = "rockchip,rk3308-pinctrl", .data = &rk3308_pin_ctrl},
4113 {.compatible = "rockchip,rk3328-pinctrl", .data = &rk3328_pin_ctrl},
4114 {.compatible = "rockchip,rk3368-pinctrl", .data = &rk3368_pin_ctrl},
4115 {.compatible = "rockchip,rk3399-pinctrl", .data = &rk3399_pin_ctrl},
4116 {.compatible = "rockchip,rk3568-pinctrl", .data = &rk3568_pin_ctrl},
4117 {},
4118 };
4119
4120 static struct platform_driver rockchip_pinctrl_driver = {
4121 .probe = rockchip_pinctrl_probe,
4122 .driver =
4123 {
4124 .name = "rockchip-pinctrl",
4125 .pm = &rockchip_pinctrl_dev_pm_ops,
4126 .of_match_table = rockchip_pinctrl_dt_match,
4127 },
4128 };
4129
rockchip_pinctrl_drv_register(void)4130 static int __init rockchip_pinctrl_drv_register(void)
4131 {
4132 return platform_driver_register(&rockchip_pinctrl_driver);
4133 }
4134 postcore_initcall(rockchip_pinctrl_drv_register);
4135
rockchip_pinctrl_drv_unregister(void)4136 static void __exit rockchip_pinctrl_drv_unregister(void)
4137 {
4138 platform_driver_unregister(&rockchip_pinctrl_driver);
4139 }
4140 module_exit(rockchip_pinctrl_drv_unregister);
4141
4142 MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver");
4143 MODULE_LICENSE("GPL");
4144 MODULE_ALIAS("platform:pinctrl-rockchip");
4145 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
4146