1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2020, Rockchip Electronics Co., Ltd. 4 */ 5 6 #ifndef __ROCKCHIP_DMC_TIMING_H__ 7 #define __ROCKCHIP_DMC_TIMING_H__ 8 9 /* hope this define can adapt all future platfor */ 10 static const char *const px30_dts_timing[] = { 11 "ddr2_speed_bin", 12 "ddr3_speed_bin", 13 "ddr4_speed_bin", 14 "pd_idle", 15 "sr_idle", 16 "sr_mc_gate_idle", 17 "srpd_lite_idle", 18 "standby_idle", 19 20 "auto_pd_dis_freq", 21 "auto_sr_dis_freq", 22 "ddr2_dll_dis_freq", 23 "ddr3_dll_dis_freq", 24 "ddr4_dll_dis_freq", 25 "phy_dll_dis_freq", 26 27 "ddr2_odt_dis_freq", 28 "phy_ddr2_odt_dis_freq", 29 "ddr2_drv", 30 "ddr2_odt", 31 "phy_ddr2_ca_drv", 32 "phy_ddr2_ck_drv", 33 "phy_ddr2_dq_drv", 34 "phy_ddr2_odt", 35 36 "ddr3_odt_dis_freq", 37 "phy_ddr3_odt_dis_freq", 38 "ddr3_drv", 39 "ddr3_odt", 40 "phy_ddr3_ca_drv", 41 "phy_ddr3_ck_drv", 42 "phy_ddr3_dq_drv", 43 "phy_ddr3_odt", 44 45 "phy_lpddr2_odt_dis_freq", 46 "lpddr2_drv", 47 "phy_lpddr2_ca_drv", 48 "phy_lpddr2_ck_drv", 49 "phy_lpddr2_dq_drv", 50 "phy_lpddr2_odt", 51 52 "lpddr3_odt_dis_freq", 53 "phy_lpddr3_odt_dis_freq", 54 "lpddr3_drv", 55 "lpddr3_odt", 56 "phy_lpddr3_ca_drv", 57 "phy_lpddr3_ck_drv", 58 "phy_lpddr3_dq_drv", 59 "phy_lpddr3_odt", 60 61 "lpddr4_odt_dis_freq", 62 "phy_lpddr4_odt_dis_freq", 63 "lpddr4_drv", 64 "lpddr4_dq_odt", 65 "lpddr4_ca_odt", 66 "phy_lpddr4_ca_drv", 67 "phy_lpddr4_ck_cs_drv", 68 "phy_lpddr4_dq_drv", 69 "phy_lpddr4_odt", 70 71 "ddr4_odt_dis_freq", 72 "phy_ddr4_odt_dis_freq", 73 "ddr4_drv", 74 "ddr4_odt", 75 "phy_ddr4_ca_drv", 76 "phy_ddr4_ck_drv", 77 "phy_ddr4_dq_drv", 78 "phy_ddr4_odt", 79 }; 80 81 struct px30_ddr_dts_config_timing { 82 unsigned int ddr2_speed_bin; 83 unsigned int ddr3_speed_bin; 84 unsigned int ddr4_speed_bin; 85 unsigned int pd_idle; 86 unsigned int sr_idle; 87 unsigned int sr_mc_gate_idle; 88 unsigned int srpd_lite_idle; 89 unsigned int standby_idle; 90 91 unsigned int auto_pd_dis_freq; 92 unsigned int auto_sr_dis_freq; 93 /* for ddr2 only */ 94 unsigned int ddr2_dll_dis_freq; 95 /* for ddr3 only */ 96 unsigned int ddr3_dll_dis_freq; 97 /* for ddr4 only */ 98 unsigned int ddr4_dll_dis_freq; 99 unsigned int phy_dll_dis_freq; 100 101 unsigned int ddr2_odt_dis_freq; 102 unsigned int phy_ddr2_odt_dis_freq; 103 unsigned int ddr2_drv; 104 unsigned int ddr2_odt; 105 unsigned int phy_ddr2_ca_drv; 106 unsigned int phy_ddr2_ck_drv; 107 unsigned int phy_ddr2_dq_drv; 108 unsigned int phy_ddr2_odt; 109 110 unsigned int ddr3_odt_dis_freq; 111 unsigned int phy_ddr3_odt_dis_freq; 112 unsigned int ddr3_drv; 113 unsigned int ddr3_odt; 114 unsigned int phy_ddr3_ca_drv; 115 unsigned int phy_ddr3_ck_drv; 116 unsigned int phy_ddr3_dq_drv; 117 unsigned int phy_ddr3_odt; 118 119 unsigned int phy_lpddr2_odt_dis_freq; 120 unsigned int lpddr2_drv; 121 unsigned int phy_lpddr2_ca_drv; 122 unsigned int phy_lpddr2_ck_drv; 123 unsigned int phy_lpddr2_dq_drv; 124 unsigned int phy_lpddr2_odt; 125 126 unsigned int lpddr3_odt_dis_freq; 127 unsigned int phy_lpddr3_odt_dis_freq; 128 unsigned int lpddr3_drv; 129 unsigned int lpddr3_odt; 130 unsigned int phy_lpddr3_ca_drv; 131 unsigned int phy_lpddr3_ck_drv; 132 unsigned int phy_lpddr3_dq_drv; 133 unsigned int phy_lpddr3_odt; 134 135 unsigned int lpddr4_odt_dis_freq; 136 unsigned int phy_lpddr4_odt_dis_freq; 137 unsigned int lpddr4_drv; 138 unsigned int lpddr4_dq_odt; 139 unsigned int lpddr4_ca_odt; 140 unsigned int phy_lpddr4_ca_drv; 141 unsigned int phy_lpddr4_ck_cs_drv; 142 unsigned int phy_lpddr4_dq_drv; 143 unsigned int phy_lpddr4_odt; 144 145 unsigned int ddr4_odt_dis_freq; 146 unsigned int phy_ddr4_odt_dis_freq; 147 unsigned int ddr4_drv; 148 unsigned int ddr4_odt; 149 unsigned int phy_ddr4_ca_drv; 150 unsigned int phy_ddr4_ck_drv; 151 unsigned int phy_ddr4_dq_drv; 152 unsigned int phy_ddr4_odt; 153 154 unsigned int ca_skew[15]; 155 unsigned int cs0_skew[44]; 156 unsigned int cs1_skew[44]; 157 158 unsigned int available; 159 }; 160 161 static const char *const rk1808_dts_ca_timing[] = { 162 "a0_ddr3a9_de-skew", "a1_ddr3a14_de-skew", "a2_ddr3a13_de-skew", "a3_ddr3a11_de-skew", 163 "a4_ddr3a2_de-skew", "a5_ddr3a4_de-skew", "a6_ddr3a3_de-skew", "a7_ddr3a6_de-skew", 164 "a8_ddr3a5_de-skew", "a9_ddr3a1_de-skew", "a10_ddr3a0_de-skew", "a11_ddr3a7_de-skew", 165 "a12_ddr3casb_de-skew", "a13_ddr3a8_de-skew", "a14_ddr3odt0_de-skew", "a15_ddr3ba1_de-skew", 166 "a16_ddr3rasb_de-skew", "a17_ddr3null_de-skew", "ba0_ddr3ba2_de-skew", "ba1_ddr3a12_de-skew", 167 "bg0_ddr3ba0_de-skew", "bg1_ddr3web_de-skew", "cke_ddr3cke_de-skew", "ck_ddr3ck_de-skew", 168 "ckb_ddr3ckb_de-skew", "csb0_ddr3a10_de-skew", "odt0_ddr3a15_de-skew", "resetn_ddr3resetn_de-skew", 169 "actn_ddr3csb0_de-skew", "csb1_ddr3csb1_de-skew", "odt1_ddr3odt1_de-skew", 170 }; 171 172 static const char *const rk1808_dts_cs0_a_timing[] = { 173 "cs0_dm0_rx_de-skew", "cs0_dm0_tx_de-skew", "cs0_dq0_rx_de-skew", "cs0_dq0_tx_de-skew", 174 "cs0_dq1_rx_de-skew", "cs0_dq1_tx_de-skew", "cs0_dq2_rx_de-skew", "cs0_dq2_tx_de-skew", 175 "cs0_dq3_rx_de-skew", "cs0_dq3_tx_de-skew", "cs0_dq4_rx_de-skew", "cs0_dq4_tx_de-skew", 176 "cs0_dq5_rx_de-skew", "cs0_dq5_tx_de-skew", "cs0_dq6_rx_de-skew", "cs0_dq6_tx_de-skew", 177 "cs0_dq7_rx_de-skew", "cs0_dq7_tx_de-skew", "cs0_dqs0p_rx_de-skew", "cs0_dqs0p_tx_de-skew", 178 "cs0_dqs0n_tx_de-skew", "cs0_dm1_rx_de-skew", "cs0_dm1_tx_de-skew", "cs0_dq8_rx_de-skew", 179 "cs0_dq8_tx_de-skew", "cs0_dq9_rx_de-skew", "cs0_dq9_tx_de-skew", "cs0_dq10_rx_de-skew", 180 "cs0_dq10_tx_de-skew", "cs0_dq11_rx_de-skew", "cs0_dq11_tx_de-skew", "cs0_dq12_rx_de-skew", 181 "cs0_dq12_tx_de-skew", "cs0_dq13_rx_de-skew", "cs0_dq13_tx_de-skew", "cs0_dq14_rx_de-skew", 182 "cs0_dq14_tx_de-skew", "cs0_dq15_rx_de-skew", "cs0_dq15_tx_de-skew", "cs0_dqs1p_rx_de-skew", 183 "cs0_dqs1p_tx_de-skew", "cs0_dqs1n_tx_de-skew", "cs0_dqs0n_rx_de-skew", "cs0_dqs1n_rx_de-skew", 184 }; 185 186 static const char *const rk1808_dts_cs0_b_timing[] = { 187 "cs0_dm2_rx_de-skew", "cs0_dm2_tx_de-skew", "cs0_dq16_rx_de-skew", "cs0_dq16_tx_de-skew", 188 "cs0_dq17_rx_de-skew", "cs0_dq17_tx_de-skew", "cs0_dq18_rx_de-skew", "cs0_dq18_tx_de-skew", 189 "cs0_dq19_rx_de-skew", "cs0_dq19_tx_de-skew", "cs0_dq20_rx_de-skew", "cs0_dq20_tx_de-skew", 190 "cs0_dq21_rx_de-skew", "cs0_dq21_tx_de-skew", "cs0_dq22_rx_de-skew", "cs0_dq22_tx_de-skew", 191 "cs0_dq23_rx_de-skew", "cs0_dq23_tx_de-skew", "cs0_dqs2p_rx_de-skew", "cs0_dqs2p_tx_de-skew", 192 "cs0_dqs2n_tx_de-skew", "cs0_dm3_rx_de-skew", "cs0_dm3_tx_de-skew", "cs0_dq24_rx_de-skew", 193 "cs0_dq24_tx_de-skew", "cs0_dq25_rx_de-skew", "cs0_dq25_tx_de-skew", "cs0_dq26_rx_de-skew", 194 "cs0_dq26_tx_de-skew", "cs0_dq27_rx_de-skew", "cs0_dq27_tx_de-skew", "cs0_dq28_rx_de-skew", 195 "cs0_dq28_tx_de-skew", "cs0_dq29_rx_de-skew", "cs0_dq29_tx_de-skew", "cs0_dq30_rx_de-skew", 196 "cs0_dq30_tx_de-skew", "cs0_dq31_rx_de-skew", "cs0_dq31_tx_de-skew", "cs0_dqs3p_rx_de-skew", 197 "cs0_dqs3p_tx_de-skew", "cs0_dqs3n_tx_de-skew", "cs0_dqs2n_rx_de-skew", "cs0_dqs3n_rx_de-skew", 198 }; 199 200 static const char *const rk1808_dts_cs1_a_timing[] = { 201 "cs1_dm0_rx_de-skew", "cs1_dm0_tx_de-skew", "cs1_dq0_rx_de-skew", "cs1_dq0_tx_de-skew", 202 "cs1_dq1_rx_de-skew", "cs1_dq1_tx_de-skew", "cs1_dq2_rx_de-skew", "cs1_dq2_tx_de-skew", 203 "cs1_dq3_rx_de-skew", "cs1_dq3_tx_de-skew", "cs1_dq4_rx_de-skew", "cs1_dq4_tx_de-skew", 204 "cs1_dq5_rx_de-skew", "cs1_dq5_tx_de-skew", "cs1_dq6_rx_de-skew", "cs1_dq6_tx_de-skew", 205 "cs1_dq7_rx_de-skew", "cs1_dq7_tx_de-skew", "cs1_dqs0p_rx_de-skew", "cs1_dqs0p_tx_de-skew", 206 "cs1_dqs0n_tx_de-skew", "cs1_dm1_rx_de-skew", "cs1_dm1_tx_de-skew", "cs1_dq8_rx_de-skew", 207 "cs1_dq8_tx_de-skew", "cs1_dq9_rx_de-skew", "cs1_dq9_tx_de-skew", "cs1_dq10_rx_de-skew", 208 "cs1_dq10_tx_de-skew", "cs1_dq11_rx_de-skew", "cs1_dq11_tx_de-skew", "cs1_dq12_rx_de-skew", 209 "cs1_dq12_tx_de-skew", "cs1_dq13_rx_de-skew", "cs1_dq13_tx_de-skew", "cs1_dq14_rx_de-skew", 210 "cs1_dq14_tx_de-skew", "cs1_dq15_rx_de-skew", "cs1_dq15_tx_de-skew", "cs1_dqs1p_rx_de-skew", 211 "cs1_dqs1p_tx_de-skew", "cs1_dqs1n_tx_de-skew", "cs1_dqs0n_rx_de-skew", "cs1_dqs1n_rx_de-skew", 212 }; 213 214 static const char *const rk1808_dts_cs1_b_timing[] = { 215 "cs1_dm2_rx_de-skew", "cs1_dm2_tx_de-skew", "cs1_dq16_rx_de-skew", "cs1_dq16_tx_de-skew", 216 "cs1_dq17_rx_de-skew", "cs1_dq17_tx_de-skew", "cs1_dq18_rx_de-skew", "cs1_dq18_tx_de-skew", 217 "cs1_dq19_rx_de-skew", "cs1_dq19_tx_de-skew", "cs1_dq20_rx_de-skew", "cs1_dq20_tx_de-skew", 218 "cs1_dq21_rx_de-skew", "cs1_dq21_tx_de-skew", "cs1_dq22_rx_de-skew", "cs1_dq22_tx_de-skew", 219 "cs1_dq23_rx_de-skew", "cs1_dq23_tx_de-skew", "cs1_dqs2p_rx_de-skew", "cs1_dqs2p_tx_de-skew", 220 "cs1_dqs2n_tx_de-skew", "cs1_dm3_rx_de-skew", "cs1_dm3_tx_de-skew", "cs1_dq24_rx_de-skew", 221 "cs1_dq24_tx_de-skew", "cs1_dq25_rx_de-skew", "cs1_dq25_tx_de-skew", "cs1_dq26_rx_de-skew", 222 "cs1_dq26_tx_de-skew", "cs1_dq27_rx_de-skew", "cs1_dq27_tx_de-skew", "cs1_dq28_rx_de-skew", 223 "cs1_dq28_tx_de-skew", "cs1_dq29_rx_de-skew", "cs1_dq29_tx_de-skew", "cs1_dq30_rx_de-skew", 224 "cs1_dq30_tx_de-skew", "cs1_dq31_rx_de-skew", "cs1_dq31_tx_de-skew", "cs1_dqs3p_rx_de-skew", 225 "cs1_dqs3p_tx_de-skew", "cs1_dqs3n_tx_de-skew", "cs1_dqs2n_rx_de-skew", "cs1_dqs3n_rx_de-skew", 226 }; 227 228 struct rk1808_ddr_dts_config_timing { 229 unsigned int ddr2_speed_bin; 230 unsigned int ddr3_speed_bin; 231 unsigned int ddr4_speed_bin; 232 unsigned int pd_idle; 233 unsigned int sr_idle; 234 unsigned int sr_mc_gate_idle; 235 unsigned int srpd_lite_idle; 236 unsigned int standby_idle; 237 238 unsigned int auto_pd_dis_freq; 239 unsigned int auto_sr_dis_freq; 240 /* for ddr2 only */ 241 unsigned int ddr2_dll_dis_freq; 242 /* for ddr3 only */ 243 unsigned int ddr3_dll_dis_freq; 244 /* for ddr4 only */ 245 unsigned int ddr4_dll_dis_freq; 246 unsigned int phy_dll_dis_freq; 247 248 unsigned int ddr2_odt_dis_freq; 249 unsigned int phy_ddr2_odt_dis_freq; 250 unsigned int ddr2_drv; 251 unsigned int ddr2_odt; 252 unsigned int phy_ddr2_ca_drv; 253 unsigned int phy_ddr2_ck_drv; 254 unsigned int phy_ddr2_dq_drv; 255 unsigned int phy_ddr2_odt; 256 257 unsigned int ddr3_odt_dis_freq; 258 unsigned int phy_ddr3_odt_dis_freq; 259 unsigned int ddr3_drv; 260 unsigned int ddr3_odt; 261 unsigned int phy_ddr3_ca_drv; 262 unsigned int phy_ddr3_ck_drv; 263 unsigned int phy_ddr3_dq_drv; 264 unsigned int phy_ddr3_odt; 265 266 unsigned int phy_lpddr2_odt_dis_freq; 267 unsigned int lpddr2_drv; 268 unsigned int phy_lpddr2_ca_drv; 269 unsigned int phy_lpddr2_ck_drv; 270 unsigned int phy_lpddr2_dq_drv; 271 unsigned int phy_lpddr2_odt; 272 273 unsigned int lpddr3_odt_dis_freq; 274 unsigned int phy_lpddr3_odt_dis_freq; 275 unsigned int lpddr3_drv; 276 unsigned int lpddr3_odt; 277 unsigned int phy_lpddr3_ca_drv; 278 unsigned int phy_lpddr3_ck_drv; 279 unsigned int phy_lpddr3_dq_drv; 280 unsigned int phy_lpddr3_odt; 281 282 unsigned int lpddr4_odt_dis_freq; 283 unsigned int phy_lpddr4_odt_dis_freq; 284 unsigned int lpddr4_drv; 285 unsigned int lpddr4_dq_odt; 286 unsigned int lpddr4_ca_odt; 287 unsigned int phy_lpddr4_ca_drv; 288 unsigned int phy_lpddr4_ck_cs_drv; 289 unsigned int phy_lpddr4_dq_drv; 290 unsigned int phy_lpddr4_odt; 291 292 unsigned int ddr4_odt_dis_freq; 293 unsigned int phy_ddr4_odt_dis_freq; 294 unsigned int ddr4_drv; 295 unsigned int ddr4_odt; 296 unsigned int phy_ddr4_ca_drv; 297 unsigned int phy_ddr4_ck_drv; 298 unsigned int phy_ddr4_dq_drv; 299 unsigned int phy_ddr4_odt; 300 301 unsigned int ca_de_skew[31]; 302 unsigned int cs0_a_de_skew[44]; 303 unsigned int cs0_b_de_skew[44]; 304 unsigned int cs1_a_de_skew[44]; 305 unsigned int cs1_b_de_skew[44]; 306 307 unsigned int available; 308 }; 309 310 static const char *const rk3128_dts_timing[] = { 311 "ddr3_speed_bin", 312 "pd_idle", 313 "sr_idle", 314 "auto_pd_dis_freq", 315 "auto_sr_dis_freq", 316 "ddr3_dll_dis_freq", 317 "lpddr2_dll_dis_freq", 318 "phy_dll_dis_freq", 319 "ddr3_odt_dis_freq", 320 "phy_ddr3_odt_disb_freq", 321 "ddr3_drv", 322 "ddr3_odt", 323 "phy_ddr3_clk_drv", 324 "phy_ddr3_cmd_drv", 325 "phy_ddr3_dqs_drv", 326 "phy_ddr3_odt", 327 "lpddr2_drv", 328 "phy_lpddr2_clk_drv", 329 "phy_lpddr2_cmd_drv", 330 "phy_lpddr2_dqs_drv", 331 "ddr_2t", 332 }; 333 334 struct rk3128_ddr_dts_config_timing { 335 u32 ddr3_speed_bin; 336 u32 pd_idle; 337 u32 sr_idle; 338 u32 auto_pd_dis_freq; 339 u32 auto_sr_dis_freq; 340 u32 ddr3_dll_dis_freq; 341 u32 lpddr2_dll_dis_freq; 342 u32 phy_dll_dis_freq; 343 u32 ddr3_odt_dis_freq; 344 u32 phy_ddr3_odt_disb_freq; 345 u32 ddr3_drv; 346 u32 ddr3_odt; 347 u32 phy_ddr3_clk_drv; 348 u32 phy_ddr3_cmd_drv; 349 u32 phy_ddr3_dqs_drv; 350 u32 phy_ddr3_odt; 351 u32 lpddr2_drv; 352 u32 phy_lpddr2_clk_drv; 353 u32 phy_lpddr2_cmd_drv; 354 u32 phy_lpddr2_dqs_drv; 355 u32 ddr_2t; 356 u32 available; 357 }; 358 359 static const char *const rk3228_dts_timing[] = { 360 "dram_spd_bin", "sr_idle", "pd_idle", "dram_dll_disb_freq", "phy_dll_disb_freq", 361 "dram_odt_disb_freq", "phy_odt_disb_freq", "ddr3_drv", "ddr3_odt", "lpddr3_drv", 362 "lpddr3_odt", "lpddr2_drv", "phy_ddr3_clk_drv", "phy_ddr3_cmd_drv", "phy_ddr3_dqs_drv", 363 "phy_ddr3_odt", "phy_lp23_clk_drv", "phy_lp23_cmd_drv", "phy_lp23_dqs_drv", "phy_lp3_odt"}; 364 365 struct rk3228_ddr_dts_config_timing { 366 u32 dram_spd_bin; 367 u32 sr_idle; 368 u32 pd_idle; 369 u32 dram_dll_dis_freq; 370 u32 phy_dll_dis_freq; 371 u32 dram_odt_dis_freq; 372 u32 phy_odt_dis_freq; 373 u32 ddr3_drv; 374 u32 ddr3_odt; 375 u32 lpddr3_drv; 376 u32 lpddr3_odt; 377 u32 lpddr2_drv; 378 u32 phy_ddr3_clk_drv; 379 u32 phy_ddr3_cmd_drv; 380 u32 phy_ddr3_dqs_drv; 381 u32 phy_ddr3_odt; 382 u32 phy_lp23_clk_drv; 383 u32 phy_lp23_cmd_drv; 384 u32 phy_lp23_dqs_drv; 385 u32 phy_lp3_odt; 386 }; 387 388 static const char *const rk3288_dts_timing[] = { 389 "ddr3_speed_bin", "pd_idle", "sr_idle", 390 391 "auto_pd_dis_freq", "auto_sr_dis_freq", 392 /* for ddr3 only */ 393 "ddr3_dll_dis_freq", "phy_dll_dis_freq", 394 395 "ddr3_odt_dis_freq", "phy_ddr3_odt_dis_freq", "ddr3_drv", "ddr3_odt", "phy_ddr3_drv", "phy_ddr3_odt", 396 397 "lpddr2_drv", "phy_lpddr2_drv", 398 399 "lpddr3_odt_dis_freq", "phy_lpddr3_odt_dis_freq", "lpddr3_drv", "lpddr3_odt", "phy_lpddr3_drv", "phy_lpddr3_odt"}; 400 401 struct rk3288_ddr_dts_config_timing { 402 unsigned int ddr3_speed_bin; 403 unsigned int pd_idle; 404 unsigned int sr_idle; 405 406 unsigned int auto_pd_dis_freq; 407 unsigned int auto_sr_dis_freq; 408 /* for ddr3 only */ 409 unsigned int ddr3_dll_dis_freq; 410 unsigned int phy_dll_dis_freq; 411 412 unsigned int ddr3_odt_dis_freq; 413 unsigned int phy_ddr3_odt_dis_freq; 414 unsigned int ddr3_drv; 415 unsigned int ddr3_odt; 416 unsigned int phy_ddr3_drv; 417 unsigned int phy_ddr3_odt; 418 419 unsigned int lpddr2_drv; 420 unsigned int phy_lpddr2_drv; 421 422 unsigned int lpddr3_odt_dis_freq; 423 unsigned int phy_lpddr3_odt_dis_freq; 424 unsigned int lpddr3_drv; 425 unsigned int lpddr3_odt; 426 unsigned int phy_lpddr3_drv; 427 unsigned int phy_lpddr3_odt; 428 429 unsigned int available; 430 }; 431 432 /* hope this define can adapt all future platfor */ 433 static const char *const rk3328_dts_timing[] = { 434 "ddr3_speed_bin", 435 "ddr4_speed_bin", 436 "pd_idle", 437 "sr_idle", 438 "sr_mc_gate_idle", 439 "srpd_lite_idle", 440 "standby_idle", 441 442 "auto_pd_dis_freq", 443 "auto_sr_dis_freq", 444 "ddr3_dll_dis_freq", 445 "ddr4_dll_dis_freq", 446 "phy_dll_dis_freq", 447 448 "ddr3_odt_dis_freq", 449 "phy_ddr3_odt_dis_freq", 450 "ddr3_drv", 451 "ddr3_odt", 452 "phy_ddr3_ca_drv", 453 "phy_ddr3_ck_drv", 454 "phy_ddr3_dq_drv", 455 "phy_ddr3_odt", 456 457 "lpddr3_odt_dis_freq", 458 "phy_lpddr3_odt_dis_freq", 459 "lpddr3_drv", 460 "lpddr3_odt", 461 "phy_lpddr3_ca_drv", 462 "phy_lpddr3_ck_drv", 463 "phy_lpddr3_dq_drv", 464 "phy_lpddr3_odt", 465 466 "lpddr4_odt_dis_freq", 467 "phy_lpddr4_odt_dis_freq", 468 "lpddr4_drv", 469 "lpddr4_dq_odt", 470 "lpddr4_ca_odt", 471 "phy_lpddr4_ca_drv", 472 "phy_lpddr4_ck_cs_drv", 473 "phy_lpddr4_dq_drv", 474 "phy_lpddr4_odt", 475 476 "ddr4_odt_dis_freq", 477 "phy_ddr4_odt_dis_freq", 478 "ddr4_drv", 479 "ddr4_odt", 480 "phy_ddr4_ca_drv", 481 "phy_ddr4_ck_drv", 482 "phy_ddr4_dq_drv", 483 "phy_ddr4_odt", 484 }; 485 486 static const char *const rk3328_dts_ca_timing[] = { 487 "ddr3a1_ddr4a9_de-skew", "ddr3a0_ddr4a10_de-skew", "ddr3a3_ddr4a6_de-skew", "ddr3a2_ddr4a4_de-skew", 488 "ddr3a5_ddr4a8_de-skew", "ddr3a4_ddr4a5_de-skew", "ddr3a7_ddr4a11_de-skew", "ddr3a6_ddr4a7_de-skew", 489 "ddr3a9_ddr4a0_de-skew", "ddr3a8_ddr4a13_de-skew", "ddr3a11_ddr4a3_de-skew", "ddr3a10_ddr4cs0_de-skew", 490 "ddr3a13_ddr4a2_de-skew", "ddr3a12_ddr4ba1_de-skew", "ddr3a15_ddr4odt0_de-skew", "ddr3a14_ddr4a1_de-skew", 491 "ddr3ba1_ddr4a15_de-skew", "ddr3ba0_ddr4bg0_de-skew", "ddr3ras_ddr4cke_de-skew", "ddr3ba2_ddr4ba0_de-skew", 492 "ddr3we_ddr4bg1_de-skew", "ddr3cas_ddr4a12_de-skew", "ddr3ckn_ddr4ckn_de-skew", "ddr3ckp_ddr4ckp_de-skew", 493 "ddr3cke_ddr4a16_de-skew", "ddr3odt0_ddr4a14_de-skew", "ddr3cs0_ddr4act_de-skew", "ddr3reset_ddr4reset_de-skew", 494 "ddr3cs1_ddr4cs1_de-skew", "ddr3odt1_ddr4odt1_de-skew", 495 }; 496 497 static const char *const rk3328_dts_cs0_timing[] = { 498 "cs0_dm0_rx_de-skew", "cs0_dm0_tx_de-skew", "cs0_dq0_rx_de-skew", "cs0_dq0_tx_de-skew", "cs0_dq1_rx_de-skew", 499 "cs0_dq1_tx_de-skew", "cs0_dq2_rx_de-skew", "cs0_dq2_tx_de-skew", "cs0_dq3_rx_de-skew", "cs0_dq3_tx_de-skew", 500 "cs0_dq4_rx_de-skew", "cs0_dq4_tx_de-skew", "cs0_dq5_rx_de-skew", "cs0_dq5_tx_de-skew", "cs0_dq6_rx_de-skew", 501 "cs0_dq6_tx_de-skew", "cs0_dq7_rx_de-skew", "cs0_dq7_tx_de-skew", "cs0_dqs0_rx_de-skew", "cs0_dqs0p_tx_de-skew", 502 "cs0_dqs0n_tx_de-skew", 503 504 "cs0_dm1_rx_de-skew", "cs0_dm1_tx_de-skew", "cs0_dq8_rx_de-skew", "cs0_dq8_tx_de-skew", "cs0_dq9_rx_de-skew", 505 "cs0_dq9_tx_de-skew", "cs0_dq10_rx_de-skew", "cs0_dq10_tx_de-skew", "cs0_dq11_rx_de-skew", "cs0_dq11_tx_de-skew", 506 "cs0_dq12_rx_de-skew", "cs0_dq12_tx_de-skew", "cs0_dq13_rx_de-skew", "cs0_dq13_tx_de-skew", "cs0_dq14_rx_de-skew", 507 "cs0_dq14_tx_de-skew", "cs0_dq15_rx_de-skew", "cs0_dq15_tx_de-skew", "cs0_dqs1_rx_de-skew", "cs0_dqs1p_tx_de-skew", 508 "cs0_dqs1n_tx_de-skew", 509 510 "cs0_dm2_rx_de-skew", "cs0_dm2_tx_de-skew", "cs0_dq16_rx_de-skew", "cs0_dq16_tx_de-skew", "cs0_dq17_rx_de-skew", 511 "cs0_dq17_tx_de-skew", "cs0_dq18_rx_de-skew", "cs0_dq18_tx_de-skew", "cs0_dq19_rx_de-skew", "cs0_dq19_tx_de-skew", 512 "cs0_dq20_rx_de-skew", "cs0_dq20_tx_de-skew", "cs0_dq21_rx_de-skew", "cs0_dq21_tx_de-skew", "cs0_dq22_rx_de-skew", 513 "cs0_dq22_tx_de-skew", "cs0_dq23_rx_de-skew", "cs0_dq23_tx_de-skew", "cs0_dqs2_rx_de-skew", "cs0_dqs2p_tx_de-skew", 514 "cs0_dqs2n_tx_de-skew", 515 516 "cs0_dm3_rx_de-skew", "cs0_dm3_tx_de-skew", "cs0_dq24_rx_de-skew", "cs0_dq24_tx_de-skew", "cs0_dq25_rx_de-skew", 517 "cs0_dq25_tx_de-skew", "cs0_dq26_rx_de-skew", "cs0_dq26_tx_de-skew", "cs0_dq27_rx_de-skew", "cs0_dq27_tx_de-skew", 518 "cs0_dq28_rx_de-skew", "cs0_dq28_tx_de-skew", "cs0_dq29_rx_de-skew", "cs0_dq29_tx_de-skew", "cs0_dq30_rx_de-skew", 519 "cs0_dq30_tx_de-skew", "cs0_dq31_rx_de-skew", "cs0_dq31_tx_de-skew", "cs0_dqs3_rx_de-skew", "cs0_dqs3p_tx_de-skew", 520 "cs0_dqs3n_tx_de-skew", 521 }; 522 523 static const char *const rk3328_dts_cs1_timing[] = { 524 "cs1_dm0_rx_de-skew", "cs1_dm0_tx_de-skew", "cs1_dq0_rx_de-skew", "cs1_dq0_tx_de-skew", "cs1_dq1_rx_de-skew", 525 "cs1_dq1_tx_de-skew", "cs1_dq2_rx_de-skew", "cs1_dq2_tx_de-skew", "cs1_dq3_rx_de-skew", "cs1_dq3_tx_de-skew", 526 "cs1_dq4_rx_de-skew", "cs1_dq4_tx_de-skew", "cs1_dq5_rx_de-skew", "cs1_dq5_tx_de-skew", "cs1_dq6_rx_de-skew", 527 "cs1_dq6_tx_de-skew", "cs1_dq7_rx_de-skew", "cs1_dq7_tx_de-skew", "cs1_dqs0_rx_de-skew", "cs1_dqs0p_tx_de-skew", 528 "cs1_dqs0n_tx_de-skew", 529 530 "cs1_dm1_rx_de-skew", "cs1_dm1_tx_de-skew", "cs1_dq8_rx_de-skew", "cs1_dq8_tx_de-skew", "cs1_dq9_rx_de-skew", 531 "cs1_dq9_tx_de-skew", "cs1_dq10_rx_de-skew", "cs1_dq10_tx_de-skew", "cs1_dq11_rx_de-skew", "cs1_dq11_tx_de-skew", 532 "cs1_dq12_rx_de-skew", "cs1_dq12_tx_de-skew", "cs1_dq13_rx_de-skew", "cs1_dq13_tx_de-skew", "cs1_dq14_rx_de-skew", 533 "cs1_dq14_tx_de-skew", "cs1_dq15_rx_de-skew", "cs1_dq15_tx_de-skew", "cs1_dqs1_rx_de-skew", "cs1_dqs1p_tx_de-skew", 534 "cs1_dqs1n_tx_de-skew", 535 536 "cs1_dm2_rx_de-skew", "cs1_dm2_tx_de-skew", "cs1_dq16_rx_de-skew", "cs1_dq16_tx_de-skew", "cs1_dq17_rx_de-skew", 537 "cs1_dq17_tx_de-skew", "cs1_dq18_rx_de-skew", "cs1_dq18_tx_de-skew", "cs1_dq19_rx_de-skew", "cs1_dq19_tx_de-skew", 538 "cs1_dq20_rx_de-skew", "cs1_dq20_tx_de-skew", "cs1_dq21_rx_de-skew", "cs1_dq21_tx_de-skew", "cs1_dq22_rx_de-skew", 539 "cs1_dq22_tx_de-skew", "cs1_dq23_rx_de-skew", "cs1_dq23_tx_de-skew", "cs1_dqs2_rx_de-skew", "cs1_dqs2p_tx_de-skew", 540 "cs1_dqs2n_tx_de-skew", 541 542 "cs1_dm3_rx_de-skew", "cs1_dm3_tx_de-skew", "cs1_dq24_rx_de-skew", "cs1_dq24_tx_de-skew", "cs1_dq25_rx_de-skew", 543 "cs1_dq25_tx_de-skew", "cs1_dq26_rx_de-skew", "cs1_dq26_tx_de-skew", "cs1_dq27_rx_de-skew", "cs1_dq27_tx_de-skew", 544 "cs1_dq28_rx_de-skew", "cs1_dq28_tx_de-skew", "cs1_dq29_rx_de-skew", "cs1_dq29_tx_de-skew", "cs1_dq30_rx_de-skew", 545 "cs1_dq30_tx_de-skew", "cs1_dq31_rx_de-skew", "cs1_dq31_tx_de-skew", "cs1_dqs3_rx_de-skew", "cs1_dqs3p_tx_de-skew", 546 "cs1_dqs3n_tx_de-skew", 547 }; 548 549 struct rk3328_ddr_dts_config_timing { 550 unsigned int ddr3_speed_bin; 551 unsigned int ddr4_speed_bin; 552 unsigned int pd_idle; 553 unsigned int sr_idle; 554 unsigned int sr_mc_gate_idle; 555 unsigned int srpd_lite_idle; 556 unsigned int standby_idle; 557 558 unsigned int auto_pd_dis_freq; 559 unsigned int auto_sr_dis_freq; 560 /* for ddr3 only */ 561 unsigned int ddr3_dll_dis_freq; 562 /* for ddr4 only */ 563 unsigned int ddr4_dll_dis_freq; 564 unsigned int phy_dll_dis_freq; 565 566 unsigned int ddr3_odt_dis_freq; 567 unsigned int phy_ddr3_odt_dis_freq; 568 unsigned int ddr3_drv; 569 unsigned int ddr3_odt; 570 unsigned int phy_ddr3_ca_drv; 571 unsigned int phy_ddr3_ck_drv; 572 unsigned int phy_ddr3_dq_drv; 573 unsigned int phy_ddr3_odt; 574 575 unsigned int lpddr3_odt_dis_freq; 576 unsigned int phy_lpddr3_odt_dis_freq; 577 unsigned int lpddr3_drv; 578 unsigned int lpddr3_odt; 579 unsigned int phy_lpddr3_ca_drv; 580 unsigned int phy_lpddr3_ck_drv; 581 unsigned int phy_lpddr3_dq_drv; 582 unsigned int phy_lpddr3_odt; 583 584 unsigned int lpddr4_odt_dis_freq; 585 unsigned int phy_lpddr4_odt_dis_freq; 586 unsigned int lpddr4_drv; 587 unsigned int lpddr4_dq_odt; 588 unsigned int lpddr4_ca_odt; 589 unsigned int phy_lpddr4_ca_drv; 590 unsigned int phy_lpddr4_ck_cs_drv; 591 unsigned int phy_lpddr4_dq_drv; 592 unsigned int phy_lpddr4_odt; 593 594 unsigned int ddr4_odt_dis_freq; 595 unsigned int phy_ddr4_odt_dis_freq; 596 unsigned int ddr4_drv; 597 unsigned int ddr4_odt; 598 unsigned int phy_ddr4_ca_drv; 599 unsigned int phy_ddr4_ck_drv; 600 unsigned int phy_ddr4_dq_drv; 601 unsigned int phy_ddr4_odt; 602 603 unsigned int ca_skew[15]; 604 unsigned int cs0_skew[44]; 605 unsigned int cs1_skew[44]; 606 607 unsigned int available; 608 }; 609 610 struct rk3328_ddr_de_skew_setting { 611 unsigned int ca_de_skew[30]; 612 unsigned int cs0_de_skew[84]; 613 unsigned int cs1_de_skew[84]; 614 }; 615 616 struct rk3368_dram_timing { 617 u32 dram_spd_bin; 618 u32 sr_idle; 619 u32 pd_idle; 620 u32 dram_dll_dis_freq; 621 u32 phy_dll_dis_freq; 622 u32 dram_odt_dis_freq; 623 u32 phy_odt_dis_freq; 624 u32 ddr3_drv; 625 u32 ddr3_odt; 626 u32 lpddr3_drv; 627 u32 lpddr3_odt; 628 u32 lpddr2_drv; 629 u32 phy_clk_drv; 630 u32 phy_cmd_drv; 631 u32 phy_dqs_drv; 632 u32 phy_odt; 633 u32 ddr_2t; 634 }; 635 636 struct rk3399_dram_timing { 637 unsigned int ddr3_speed_bin; 638 unsigned int pd_idle; 639 unsigned int sr_idle; 640 unsigned int sr_mc_gate_idle; 641 unsigned int srpd_lite_idle; 642 unsigned int standby_idle; 643 unsigned int auto_lp_dis_freq; 644 unsigned int ddr3_dll_dis_freq; 645 unsigned int phy_dll_dis_freq; 646 unsigned int ddr3_odt_dis_freq; 647 unsigned int ddr3_drv; 648 unsigned int ddr3_odt; 649 unsigned int phy_ddr3_ca_drv; 650 unsigned int phy_ddr3_dq_drv; 651 unsigned int phy_ddr3_odt; 652 unsigned int lpddr3_odt_dis_freq; 653 unsigned int lpddr3_drv; 654 unsigned int lpddr3_odt; 655 unsigned int phy_lpddr3_ca_drv; 656 unsigned int phy_lpddr3_dq_drv; 657 unsigned int phy_lpddr3_odt; 658 unsigned int lpddr4_odt_dis_freq; 659 unsigned int lpddr4_drv; 660 unsigned int lpddr4_dq_odt; 661 unsigned int lpddr4_ca_odt; 662 unsigned int phy_lpddr4_ca_drv; 663 unsigned int phy_lpddr4_ck_cs_drv; 664 unsigned int phy_lpddr4_dq_drv; 665 unsigned int phy_lpddr4_odt; 666 }; 667 668 struct rk3568_ddr_dts_config_timing { 669 unsigned int ddr2_speed_bin; 670 unsigned int ddr3_speed_bin; 671 unsigned int ddr4_speed_bin; 672 unsigned int pd_idle; 673 unsigned int sr_idle; 674 unsigned int sr_mc_gate_idle; 675 unsigned int srpd_lite_idle; 676 unsigned int standby_idle; 677 678 unsigned int auto_pd_dis_freq; 679 unsigned int auto_sr_dis_freq; 680 /* for ddr2 only */ 681 unsigned int ddr2_dll_dis_freq; 682 /* for ddr3 only */ 683 unsigned int ddr3_dll_dis_freq; 684 /* for ddr4 only */ 685 unsigned int ddr4_dll_dis_freq; 686 unsigned int phy_dll_dis_freq; 687 688 unsigned int ddr2_odt_dis_freq; 689 unsigned int phy_ddr2_odt_dis_freq; 690 unsigned int ddr2_drv; 691 unsigned int ddr2_odt; 692 unsigned int phy_ddr2_ca_drv; 693 unsigned int phy_ddr2_ck_drv; 694 unsigned int phy_ddr2_dq_drv; 695 unsigned int phy_ddr2_odt; 696 697 unsigned int ddr3_odt_dis_freq; 698 unsigned int phy_ddr3_odt_dis_freq; 699 unsigned int ddr3_drv; 700 unsigned int ddr3_odt; 701 unsigned int phy_ddr3_ca_drv; 702 unsigned int phy_ddr3_ck_drv; 703 unsigned int phy_ddr3_dq_drv; 704 unsigned int phy_ddr3_odt; 705 706 unsigned int phy_lpddr2_odt_dis_freq; 707 unsigned int lpddr2_drv; 708 unsigned int phy_lpddr2_ca_drv; 709 unsigned int phy_lpddr2_ck_drv; 710 unsigned int phy_lpddr2_dq_drv; 711 unsigned int phy_lpddr2_odt; 712 713 unsigned int lpddr3_odt_dis_freq; 714 unsigned int phy_lpddr3_odt_dis_freq; 715 unsigned int lpddr3_drv; 716 unsigned int lpddr3_odt; 717 unsigned int phy_lpddr3_ca_drv; 718 unsigned int phy_lpddr3_ck_drv; 719 unsigned int phy_lpddr3_dq_drv; 720 unsigned int phy_lpddr3_odt; 721 722 unsigned int lpddr4_odt_dis_freq; 723 unsigned int phy_lpddr4_odt_dis_freq; 724 unsigned int lpddr4_drv; 725 unsigned int lpddr4_dq_odt; 726 unsigned int lpddr4_ca_odt; 727 unsigned int phy_lpddr4_ca_drv; 728 unsigned int phy_lpddr4_ck_cs_drv; 729 unsigned int phy_lpddr4_dq_drv; 730 unsigned int phy_lpddr4_odt; 731 732 unsigned int ddr4_odt_dis_freq; 733 unsigned int phy_ddr4_odt_dis_freq; 734 unsigned int ddr4_drv; 735 unsigned int ddr4_odt; 736 unsigned int phy_ddr4_ca_drv; 737 unsigned int phy_ddr4_ck_drv; 738 unsigned int phy_ddr4_dq_drv; 739 unsigned int phy_ddr4_odt; 740 741 unsigned int available; 742 }; 743 744 /* name rule: ddr4(pad_name)_ddr3_lpddr3_lpddr4_de-skew */ 745 static const char *const rv1126_dts_ca_timing[] = { 746 "a0_a3_a3_cke1-a_de-skew", "a1_ba1_null_cke0-b_de-skew", 747 "a2_a9_a9_a4-a_de-skew", "a3_a15_null_a5-b_de-skew", 748 "a4_a6_a6_ck-a_de-skew", "a5_a12_null_odt0-b_de-skew", 749 "a6_ba2_null_a0-a_de-skew", "a7_a4_a4_odt0-a_de-skew", 750 "a8_a1_a1_cke0-a_de-skew", "a9_a5_a5_a5-a_de-skew", 751 "a10_a8_a8_clkb-a_de-skew", "a11_a7_a7_ca2-a_de-skew", 752 "a12_rasn_null_ca1-a_de-skew", "a13_a13_null_ca3-a_de-skew", 753 "a14_a14_null_csb1-b_de-skew", "a15_a10_null_ca0-b_de-skew", 754 "a16_a11_null_csb0-b_de-skew", "a17_null_null_null_de-skew", 755 "ba0_csb1_csb1_csb0-a_de-skew", "ba1_wen_null_cke1-b_de-skew", 756 "bg0_odt1_odt1_csb1-a_de-skew", "bg1_a2_a2_odt1-a_de-skew", 757 "cke0_casb_null_ca1-b_de-skew", "ck_ck_ck_ck-b_de-skew", 758 "ckb_ckb_ckb_ckb-b_de-skew", "csb0_odt0_odt0_ca2-b_de-skew", 759 "odt0_csb0_csb0_ca4-b_de-skew", "resetn_resetn_null-resetn_de-skew", 760 "actn_cke_cke_ca3-b_de-skew", "cke1_null_null_null_de-skew", 761 "csb1_ba0_null_null_de-skew", "odt1_a0_a0_odt1-b_de-skew", 762 }; 763 764 static const char *const rv1126_dts_cs0_a_timing[] = { 765 "cs0_dm0_rx_de-skew", "cs0_dq0_rx_de-skew", "cs0_dq1_rx_de-skew", "cs0_dq2_rx_de-skew", 766 "cs0_dq3_rx_de-skew", "cs0_dq4_rx_de-skew", "cs0_dq5_rx_de-skew", "cs0_dq6_rx_de-skew", 767 "cs0_dq7_rx_de-skew", "cs0_dqs0p_rx_de-skew", "cs0_dqs0n_rx_de-skew", "cs0_dm1_rx_de-skew", 768 "cs0_dq8_rx_de-skew", "cs0_dq9_rx_de-skew", "cs0_dq10_rx_de-skew", "cs0_dq11_rx_de-skew", 769 "cs0_dq12_rx_de-skew", "cs0_dq13_rx_de-skew", "cs0_dq14_rx_de-skew", "cs0_dq15_rx_de-skew", 770 "cs0_dqs1p_rx_de-skew", "cs0_dqs1n_rx_de-skew", "cs0_dm0_tx_de-skew", "cs0_dq0_tx_de-skew", 771 "cs0_dq1_tx_de-skew", "cs0_dq2_tx_de-skew", "cs0_dq3_tx_de-skew", "cs0_dq4_tx_de-skew", 772 "cs0_dq5_tx_de-skew", "cs0_dq6_tx_de-skew", "cs0_dq7_tx_de-skew", "cs0_dqs0p_tx_de-skew", 773 "cs0_dqs0n_tx_de-skew", "cs0_dm1_tx_de-skew", "cs0_dq8_tx_de-skew", "cs0_dq9_tx_de-skew", 774 "cs0_dq10_tx_de-skew", "cs0_dq11_tx_de-skew", "cs0_dq12_tx_de-skew", "cs0_dq13_tx_de-skew", 775 "cs0_dq14_tx_de-skew", "cs0_dq15_tx_de-skew", "cs0_dqs1p_tx_de-skew", "cs0_dqs1n_tx_de-skew", 776 }; 777 778 static const char *const rv1126_dts_cs0_b_timing[] = { 779 "cs0_dm2_rx_de-skew", "cs0_dq16_rx_de-skew", "cs0_dq17_rx_de-skew", "cs0_dq18_rx_de-skew", 780 "cs0_dq19_rx_de-skew", "cs0_dq20_rx_de-skew", "cs0_dq21_rx_de-skew", "cs0_dq22_rx_de-skew", 781 "cs0_dq23_rx_de-skew", "cs0_dqs2p_rx_de-skew", "cs0_dqs2n_rx_de-skew", "cs0_dm3_rx_de-skew", 782 "cs0_dq24_rx_de-skew", "cs0_dq25_rx_de-skew", "cs0_dq26_rx_de-skew", "cs0_dq27_rx_de-skew", 783 "cs0_dq28_rx_de-skew", "cs0_dq29_rx_de-skew", "cs0_dq30_rx_de-skew", "cs0_dq31_rx_de-skew", 784 "cs0_dqs3p_rx_de-skew", "cs0_dqs3n_rx_de-skew", "cs0_dm2_tx_de-skew", "cs0_dq16_tx_de-skew", 785 "cs0_dq17_tx_de-skew", "cs0_dq18_tx_de-skew", "cs0_dq19_tx_de-skew", "cs0_dq20_tx_de-skew", 786 "cs0_dq21_tx_de-skew", "cs0_dq22_tx_de-skew", "cs0_dq23_tx_de-skew", "cs0_dqs2p_tx_de-skew", 787 "cs0_dqs2n_tx_de-skew", "cs0_dm3_tx_de-skew", "cs0_dq24_tx_de-skew", "cs0_dq25_tx_de-skew", 788 "cs0_dq26_tx_de-skew", "cs0_dq27_tx_de-skew", "cs0_dq28_tx_de-skew", "cs0_dq29_tx_de-skew", 789 "cs0_dq30_tx_de-skew", "cs0_dq31_tx_de-skew", "cs0_dqs3p_tx_de-skew", "cs0_dqs3n_tx_de-skew", 790 }; 791 792 static const char *const rv1126_dts_cs1_a_timing[] = { 793 "cs1_dm0_rx_de-skew", "cs1_dq0_rx_de-skew", "cs1_dq1_rx_de-skew", "cs1_dq2_rx_de-skew", 794 "cs1_dq3_rx_de-skew", "cs1_dq4_rx_de-skew", "cs1_dq5_rx_de-skew", "cs1_dq6_rx_de-skew", 795 "cs1_dq7_rx_de-skew", "cs1_dqs0p_rx_de-skew", "cs1_dqs0n_rx_de-skew", "cs1_dm1_rx_de-skew", 796 "cs1_dq8_rx_de-skew", "cs1_dq9_rx_de-skew", "cs1_dq10_rx_de-skew", "cs1_dq11_rx_de-skew", 797 "cs1_dq12_rx_de-skew", "cs1_dq13_rx_de-skew", "cs1_dq14_rx_de-skew", "cs1_dq15_rx_de-skew", 798 "cs1_dqs1p_rx_de-skew", "cs1_dqs1n_rx_de-skew", "cs1_dm0_tx_de-skew", "cs1_dq0_tx_de-skew", 799 "cs1_dq1_tx_de-skew", "cs1_dq2_tx_de-skew", "cs1_dq3_tx_de-skew", "cs1_dq4_tx_de-skew", 800 "cs1_dq5_tx_de-skew", "cs1_dq6_tx_de-skew", "cs1_dq7_tx_de-skew", "cs1_dqs0p_tx_de-skew", 801 "cs1_dqs0n_tx_de-skew", "cs1_dm1_tx_de-skew", "cs1_dq8_tx_de-skew", "cs1_dq9_tx_de-skew", 802 "cs1_dq10_tx_de-skew", "cs1_dq11_tx_de-skew", "cs1_dq12_tx_de-skew", "cs1_dq13_tx_de-skew", 803 "cs1_dq14_tx_de-skew", "cs1_dq15_tx_de-skew", "cs1_dqs1p_tx_de-skew", "cs1_dqs1n_tx_de-skew", 804 }; 805 806 static const char *const rv1126_dts_cs1_b_timing[] = { 807 "cs1_dm2_rx_de-skew", "cs1_dq16_rx_de-skew", "cs1_dq17_rx_de-skew", "cs1_dq18_rx_de-skew", 808 "cs1_dq19_rx_de-skew", "cs1_dq20_rx_de-skew", "cs1_dq21_rx_de-skew", "cs1_dq22_rx_de-skew", 809 "cs1_dq23_rx_de-skew", "cs1_dqs2p_rx_de-skew", "cs1_dqs2n_rx_de-skew", "cs1_dm3_rx_de-skew", 810 "cs1_dq24_rx_de-skew", "cs1_dq25_rx_de-skew", "cs1_dq26_rx_de-skew", "cs1_dq27_rx_de-skew", 811 "cs1_dq28_rx_de-skew", "cs1_dq29_rx_de-skew", "cs1_dq30_rx_de-skew", "cs1_dq31_rx_de-skew", 812 "cs1_dqs3p_rx_de-skew", "cs1_dqs3n_rx_de-skew", "cs1_dm2_tx_de-skew", "cs1_dq16_tx_de-skew", 813 "cs1_dq17_tx_de-skew", "cs1_dq18_tx_de-skew", "cs1_dq19_tx_de-skew", "cs1_dq20_tx_de-skew", 814 "cs1_dq21_tx_de-skew", "cs1_dq22_tx_de-skew", "cs1_dq23_tx_de-skew", "cs1_dqs2p_tx_de-skew", 815 "cs1_dqs2n_tx_de-skew", "cs1_dm3_tx_de-skew", "cs1_dq24_tx_de-skew", "cs1_dq25_tx_de-skew", 816 "cs1_dq26_tx_de-skew", "cs1_dq27_tx_de-skew", "cs1_dq28_tx_de-skew", "cs1_dq29_tx_de-skew", 817 "cs1_dq30_tx_de-skew", "cs1_dq31_tx_de-skew", "cs1_dqs3p_tx_de-skew", "cs1_dqs3n_tx_de-skew", 818 }; 819 820 #endif /* __ROCKCHIP_DMC_TIMING_H__ */ 821