1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2022 Rockchip Electronics Co. Ltd. 4 * Author: Sugar Zhang <sugar.zhang@rock-chips.com> 5 */ 6 7 #ifndef DW_HDMI_QP_AUDIO_H 8 #define DW_HDMI_QP_AUDIO_H 9 10 struct dw_hdmi_qp; 11 12 struct dw_hdmi_qp_audio_data { 13 phys_addr_t phys; 14 void __iomem *base; 15 int irq; 16 struct dw_hdmi_qp *hdmi; 17 u8 *eld; 18 }; 19 20 struct dw_hdmi_qp_i2s_audio_data { 21 struct dw_hdmi_qp *hdmi; 22 u8 *eld; 23 24 void (*write)(struct dw_hdmi_qp *hdmi, u32 val, int offset); 25 u32 (*read)(struct dw_hdmi_qp *hdmi, int offset); 26 void (*mod)(struct dw_hdmi_qp *hdmi, u32 val, u32 mask, u32 reg); 27 }; 28 29 #endif 30