1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 #ifndef H_ROCKCHIP_PWM_REMOTECTL_H 4 #define H_ROCKCHIP_PWM_REMOTECTL_H 5 6 #define MAX_NUM_KEYS 60 7 #define PWM_PWR_KEY_CAPURURE_MAX 10 8 9 /* PWM0 registers */ 10 #define PWM_REG_CNTR 0x00 /* Counter Register */ 11 #define PWM_REG_HPR 0x04 /* Period Register */ 12 #define PWM_REG_LPR 0x08 /* Duty Cycle Register */ 13 #define PWM_REG_CTRL 0x0c /* Control Register */ 14 #define PWM3_REG_INTSTS 0x10 /* Interrupt Status Refister For Pwm3 */ 15 #define PWM2_REG_INTSTS 0x20 /* Interrupt Status Refister For Pwm2 */ 16 #define PWM1_REG_INTSTS 0x30 /* Interrupt Status Refister For Pwm1 */ 17 #define PWM0_REG_INTSTS 0x40 /* Interrupt Status Refister For Pwm0 */ 18 #define PWM3_REG_INT_EN 0x14 /* Interrupt Enable Refister For Pwm3 */ 19 #define PWM2_REG_INT_EN 0x24 /* Interrupt Enable Refister For Pwm2 */ 20 #define PWM1_REG_INT_EN 0x34 /* Interrupt Enable Refister For Pwm1 */ 21 #define PWM0_REG_INT_EN 0x44 /* Interrupt Enable Refister For Pwm0 */ 22 23 /* REG_CTRL bits definitions */ 24 #define PWM_ENABLE (1 << 0) 25 #define PWM_DISABLE (0 << 0) 26 27 /* operation mode */ 28 #define PWM_MODE_ONESHOT (0x00 << 1) 29 #define PWM_MODE_CONTINUMOUS (0x01 << 1) 30 #define PWM_MODE_CAPTURE (0x02 << 1) 31 32 /* duty cycle output polarity */ 33 #define PWM_DUTY_POSTIVE (0x01 << 3) 34 #define PWM_DUTY_NEGATIVE (0x00 << 3) 35 36 /* incative state output polarity */ 37 #define PWM_INACTIVE_POSTIVE (0x01 << 4) 38 #define PWM_INACTIVE_NEGATIVE (0x00 << 4) 39 40 /* clock source select */ 41 #define PWM_CLK_SCALE (1 << 9) 42 #define PWM_CLK_NON_SCALE (0 << 9) 43 44 #define PWM_CH0_INT (1 << 0) 45 #define PWM_CH1_INT (1 << 1) 46 #define PWM_CH2_INT (1 << 2) 47 #define PWM_CH3_INT (1 << 3) 48 #define PWM_PWR_KEY_INT (1 << 7) 49 50 #define PWM_CH0_POL (1 << 8) 51 #define PWM_CH1_POL (1 << 9) 52 #define PWM_CH2_POL (1 << 10) 53 #define PWM_CH3_POL (1 << 11) 54 55 #define PWM_CH0_INT_ENABLE (1 << 0) 56 #define PWM_CH0_INT_DISABLE (0 << 0) 57 58 #define PWM_CH1_INT_ENABLE (1 << 1) 59 #define PWM_CH1_INT_DISABLE (0 << 1) 60 61 #define PWM_CH2_INT_ENABLE (1 << 2) 62 #define PWM_CH2_INT_DISABLE (0 << 2) 63 64 #define PWM_CH3_INT_ENABLE (1 << 3) 65 #define PWM_CH3_INT_DISABLE (0 << 3) 66 67 #define PWM_INT_ENABLE 1 68 #define PWM_INT_DISABLE 0 69 70 /* prescale factor */ 71 #define PWMCR_MIN_PRESCALE 0x00 72 #define PWMCR_MAX_PRESCALE 0x07 73 74 #define PWMDCR_MIN_DUTY 0x0001 75 #define PWMDCR_MAX_DUTY 0xFFFF 76 77 #define PWMPCR_MIN_PERIOD 0x0001 78 #define PWMPCR_MAX_PERIOD 0xFFFF 79 80 #define PWMPCR_MIN_PERIOD 0x0001 81 #define PWMPCR_MAX_PERIOD 0xFFFF 82 83 enum pwm_div { 84 PWM_DIV1 = (0x0 << 12), 85 PWM_DIV2 = (0x1 << 12), 86 PWM_DIV4 = (0x2 << 12), 87 PWM_DIV8 = (0x3 << 12), 88 PWM_DIV16 = (0x4 << 12), 89 PWM_DIV32 = (0x5 << 12), 90 PWM_DIV64 = (0x6 << 12), 91 PWM_DIV128 = (0x7 << 12), 92 }; 93 94 /* NEC Protocol */ 95 #define RK_PWM_TIME_PRE_MIN 4000 96 #define RK_PWM_TIME_PRE_MAX 5000 97 98 #define RK_PWM_TIME_PRE_MIN_LOW 8000 99 #define RK_PWM_TIME_PRE_MAX_LOW 10000 100 101 #define RK_PWM_TIME_BIT0_MIN 390 102 #define RK_PWM_TIME_BIT0_MAX 730 103 104 #define RK_PWM_TIME_BIT1_MIN 1300 105 #define RK_PWM_TIME_BIT1_MAX 2000 106 107 #define RK_PWM_TIME_BIT_MIN_LOW 390 108 #define RK_PWM_TIME_BIT_MAX_LOW 730 109 110 #define RK_PWM_TIME_RPT_MIN 2000 111 #define RK_PWM_TIME_RPT_MAX 2500 112 113 #define RK_PWM_TIME_SEQ1_MIN 95000 114 #define RK_PWM_TIME_SEQ1_MAX 98000 115 116 #define RK_PWM_TIME_SEQ2_MIN 30000 117 #define RK_PWM_TIME_SEQ2_MAX 55000 118 119 #define PWM_REG_INTSTS(n) ((3 - (n)) * 0x10 + 0x10) 120 #define PWM_REG_INT_EN(n) ((3 - (n)) * 0x10 + 0x14) 121 #define RK_PWM_VERSION_ID(n) ((3 - (n)) * 0x10 + 0x2c) 122 #define PWM_REG_PWRMATCH_CTRL(n) ((3 - (n)) * 0x10 + 0x50) 123 #define PWM_REG_PWRMATCH_LPRE(n) ((3 - (n)) * 0x10 + 0x54) 124 #define PWM_REG_PWRMATCH_HPRE(n) ((3 - (n)) * 0x10 + 0x58) 125 #define PWM_REG_PWRMATCH_LD(n) ((3 - (n)) * 0x10 + 0x5C) 126 #define PWM_REG_PWRMATCH_HD_ZERO(n) ((3 - (n)) * 0x10 + 0x60) 127 #define PWM_REG_PWRMATCH_HD_ONE(n) ((3 - (n)) * 0x10 + 0x64) 128 #define PWM_PWRMATCH_VALUE(n) ((3 - (n)) * 0x10 + 0x68) 129 #define PWM_PWRCAPTURE_VALUE(n) ((3 - (n)) * 0x10 + 0x9c) 130 131 #define PWM_CH_INT(n) BIT(n) 132 #define PWM_CH_POL(n) BIT((n) + 8) 133 134 #define PWM_CH_INT_ENABLE(n) BIT(n) 135 #define PWM_PWR_INT_ENABLE BIT(7) 136 #define CH3_PWRKEY_ENABLE BIT(3) 137 138 typedef enum _RMC_STATE { 139 RMC_IDLE, 140 RMC_PRELOAD, 141 RMC_USERCODE, 142 RMC_GETDATA, 143 RMC_SEQUENCE, 144 } eRMC_STATE; 145 146 struct RKxx_remotectl_platform_data { 147 int nbuttons; 148 int rep; 149 int timer; 150 int wakeup; 151 }; 152 153 #endif 154