1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Rockchip MIPI CSI2 DPHY driver 4 * 5 * Copyright (C) 2020 Rockchip Electronics Co., Ltd. 6 */ 7 8 #ifndef _PHY_ROCKCHIP_CSI2_DPHY_COMMON_H_ 9 #define _PHY_ROCKCHIP_CSI2_DPHY_COMMON_H_ 10 11 #define PHY_MAX 16 12 #define MAX_DEV_NAME_LEN 32 13 14 /* add new chip id in tail by time order */ 15 enum csi2_dphy_chip_id { 16 CHIP_ID_RK3568 = 0x0, 17 CHIP_ID_RK3588 = 0x1, 18 CHIP_ID_RK3588_DCPHY = 0x2, 19 }; 20 21 enum csi2_dphy_rx_pads { 22 CSI2_DPHY_RX_PAD_SINK = 0, 23 CSI2_DPHY_RX_PAD_SOURCE, 24 CSI2_DPHY_RX_PADS_NUM, 25 }; 26 27 enum csi2_dphy_lane_mode { 28 LANE_MODE_UNDEF = 0x0, 29 LANE_MODE_FULL, 30 LANE_MODE_SPLIT, 31 }; 32 33 struct grf_reg { 34 u32 offset; 35 u32 mask; 36 u32 shift; 37 }; 38 39 struct csi2dphy_reg { 40 u32 offset; 41 }; 42 43 #define MAX_DPHY_SENSORS (2) 44 #define MAX_NUM_CSI2_DPHY (0x2) 45 46 struct csi2_sensor { 47 struct v4l2_subdev *sd; 48 struct v4l2_mbus_config mbus; 49 struct v4l2_mbus_framefmt format; 50 int lanes; 51 }; 52 53 struct csi2_dphy_hw; 54 55 struct dphy_drv_data { 56 const char dev_name[MAX_DEV_NAME_LEN]; 57 }; 58 59 struct csi2_dphy { 60 struct device *dev; 61 struct list_head list; 62 struct csi2_dphy_hw *dphy_hw; 63 struct v4l2_async_notifier notifier; 64 struct v4l2_subdev sd; 65 struct mutex mutex; /* lock for updating protection */ 66 struct media_pad pads[CSI2_DPHY_RX_PADS_NUM]; 67 struct csi2_sensor sensors[MAX_DPHY_SENSORS]; 68 u64 data_rate_mbps; 69 int num_sensors; 70 int phy_index; 71 bool is_streaming; 72 enum csi2_dphy_lane_mode lane_mode; 73 const struct dphy_drv_data *drv_data; 74 }; 75 76 struct dphy_hw_drv_data { 77 const struct hsfreq_range *hsfreq_ranges; 78 int num_hsfreq_ranges; 79 const struct hsfreq_range *hsfreq_ranges_cphy; 80 int num_hsfreq_ranges_cphy; 81 const struct grf_reg *grf_regs; 82 const struct txrx_reg *txrx_regs; 83 const struct csi2dphy_reg *csi2dphy_regs; 84 void (*individual_init)(struct csi2_dphy_hw *hw); 85 int (*stream_on)(struct csi2_dphy *dphy, struct v4l2_subdev *sd); 86 int (*stream_off)(struct csi2_dphy *dphy, struct v4l2_subdev *sd); 87 enum csi2_dphy_chip_id chip_id; 88 }; 89 90 struct csi2_dphy_hw { 91 struct device *dev; 92 struct regmap *regmap_grf; 93 struct regmap *regmap_sys_grf; 94 const struct grf_reg *grf_regs; 95 const struct txrx_reg *txrx_regs; 96 const struct csi2dphy_reg *csi2dphy_regs; 97 const struct dphy_hw_drv_data *drv_data; 98 void __iomem *hw_base_addr; 99 struct clk_bulk_data *clks_bulk; 100 struct reset_control *rsts_bulk; 101 struct csi2_dphy *dphy_dev[MAX_NUM_CSI2_DPHY]; 102 struct v4l2_subdev sd; 103 struct mutex mutex; /* lock for updating protection */ 104 atomic_t stream_cnt; 105 int num_clks; 106 int num_sensors; 107 int dphy_dev_num; 108 enum csi2_dphy_lane_mode lane_mode; 109 110 int (*stream_on)(struct csi2_dphy *dphy, struct v4l2_subdev *sd); 111 int (*stream_off)(struct csi2_dphy *dphy, struct v4l2_subdev *sd); 112 }; 113 114 #endif 115