1 /* 2 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef __VPU_H__ 17 #define __VPU_H__ 18 19 #include "rk_type.h" 20 21 #ifdef __cplusplus 22 extern "C" { 23 #endif 24 25 #define VPU_SUCCESS (0) 26 #define VPU_FAILURE (-1) 27 28 #define VPU_HW_WAIT_OK VPU_SUCCESS 29 #define VPU_HW_WAIT_ERROR VPU_FAILURE 30 #define VPU_HW_WAIT_TIMEOUT 1 31 32 // vpu decoder 60 registers, size 240B 33 #define VPU_REG_NUM_DEC (60) 34 // vpu post processor 41 registers, size 164B 35 #define VPU_REG_NUM_PP (41) 36 // vpu decoder + post processor 101 registers, size 404B 37 #define VPU_REG_NUM_DEC_PP (VPU_REG_NUM_DEC+VPU_REG_NUM_PP) 38 // vpu encoder 96 registers, size 384B 39 #define VPU_REG_NUM_ENC (96) 40 41 typedef enum { 42 VPU_ENC = 0x0, 43 VPU_DEC = 0x1, 44 VPU_PP = 0x2, 45 VPU_DEC_PP = 0x3, 46 VPU_DEC_HEVC = 0x4, 47 VPU_DEC_RKV = 0x5, 48 VPU_ENC_RKV = 0x6, 49 VPU_DEC_AVS = 0x7, 50 VPU_ENC_VEPU22 = 0x8, 51 VPU_TYPE_BUTT, 52 } VPU_CLIENT_TYPE; 53 54 /* Hardware decoder configuration description */ 55 56 typedef struct VPUHwDecConfig { 57 RK_U32 maxDecPicWidth; /* Maximum video decoding width supported */ 58 RK_U32 maxPpOutPicWidth; /* Maximum output width of Post-Processor */ 59 RK_U32 h264Support; /* HW supports h.264 */ 60 RK_U32 jpegSupport; /* HW supports JPEG */ 61 RK_U32 mpeg4Support; /* HW supports MPEG-4 */ 62 RK_U32 customMpeg4Support; /* HW supports custom MPEG-4 features */ 63 RK_U32 vc1Support; /* HW supports VC-1 Simple */ 64 RK_U32 mpeg2Support; /* HW supports MPEG-2 */ 65 RK_U32 ppSupport; /* HW supports post-processor */ 66 RK_U32 ppConfig; /* HW post-processor functions bitmask */ 67 RK_U32 sorensonSparkSupport; /* HW supports Sorenson Spark */ 68 RK_U32 refBufSupport; /* HW supports reference picture buffering */ 69 RK_U32 vp6Support; /* HW supports VP6 */ 70 RK_U32 vp7Support; /* HW supports VP7 */ 71 RK_U32 vp8Support; /* HW supports VP8 */ 72 RK_U32 avsSupport; /* HW supports AVS */ 73 RK_U32 jpegESupport; /* HW supports JPEG extensions */ 74 RK_U32 rvSupport; /* HW supports REAL */ 75 RK_U32 mvcSupport; /* HW supports H264 MVC extension */ 76 } VPUHwDecConfig_t; 77 78 /* Hardware encoder configuration description */ 79 80 typedef struct VPUHwEndConfig { 81 RK_U32 maxEncodedWidth; /* Maximum supported width for video encoding (not JPEG) */ 82 RK_U32 h264Enabled; /* HW supports H.264 */ 83 RK_U32 jpegEnabled; /* HW supports JPEG */ 84 RK_U32 mpeg4Enabled; /* HW supports MPEG-4 */ 85 RK_U32 vsEnabled; /* HW supports video stabilization */ 86 RK_U32 rgbEnabled; /* HW supports RGB input */ 87 RK_U32 reg_size; /* HW bus type in use */ 88 RK_U32 reserv[2]; 89 } VPUHwEncConfig_t; 90 91 typedef enum { 92 // common command 93 VPU_CMD_REGISTER, 94 VPU_CMD_REGISTER_ACK_OK, 95 VPU_CMD_REGISTER_ACK_FAIL, 96 VPU_CMD_UNREGISTER, 97 98 VPU_SEND_CONFIG, 99 VPU_SEND_CONFIG_ACK_OK, 100 VPU_SEND_CONFIG_ACK_FAIL, 101 102 VPU_GET_HW_INFO, 103 VPU_GET_HW_INFO_ACK_OK, 104 VPU_GET_HW_INFO_ACK_FAIL, 105 106 VPU_CMD_BUTT, 107 } VPU_CMD_TYPE; 108 109 int VPUClientInit(VPU_CLIENT_TYPE type); 110 RK_S32 VPUClientRelease(int socket); 111 RK_S32 VPUClientSendReg(int socket, RK_U32 *regs, RK_U32 nregs); 112 RK_S32 VPUClientSendReg2(RK_S32 socket, RK_S32 offset, RK_S32 size, void *param); 113 RK_S32 VPUClientWaitResult(int socket, RK_U32 *regs, RK_U32 nregs, VPU_CMD_TYPE *cmd, RK_S32 *len); 114 RK_S32 VPUClientGetHwCfg(int socket, RK_U32 *cfg, RK_U32 cfg_size); 115 RK_S32 VPUClientGetIOMMUStatus(void); 116 RK_U32 VPUCheckSupportWidth(void); 117 118 #ifdef __cplusplus 119 } 120 #endif 121 122 #endif /* __VPU_H__ */ 123