1 /* 2 * 3 * Copyright 2010 Rockchip Electronics S.LSI Co. LTD 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 */ 17 18 #ifndef __VPU_H__ 19 #define __VPU_H__ 20 21 #ifdef __cplusplus 22 extern "C" 23 { 24 #endif 25 26 #include "vpu_type.h" 27 28 #define VPU_SUCCESS (0) 29 #define VPU_FAILURE (-1) 30 31 #define VPU_HW_WAIT_OK VPU_SUCCESS 32 #define VPU_HW_WAIT_ERROR VPU_FAILURE 33 #define VPU_HW_WAIT_TIMEOUT 1 34 35 // ��������60 ���Ĵ�������С 240B 36 #define VPU_REG_NUM_DEC (159) 37 // ������41 ���Ĵ�������С 164B 38 #define VPU_REG_NUM_PP (42) 39 // �������Ӻ�����101 ���Ĵ�������С 404B 40 #define VPU_REG_NUM_DEC_PP (159) 41 // ��������96 ���Ĵ�������С 384B 42 #define VPU_REG_NUM_ENC (184) 43 44 typedef enum { 45 VPU_ENC = 0x0, 46 VPU_DEC = 0x1, 47 VPU_PP = 0x2, 48 VPU_DEC_PP = 0x3, 49 VPU_DEC_HEVC = 0x4, 50 VPU_TYPE_BUTT, 51 } VPU_CLIENT_TYPE; 52 53 /* Hardware decoder configuration description */ 54 55 typedef struct VPUHwDecConfig { 56 RK_U32 maxDecPicWidth; /* Maximum video decoding width supported */ 57 RK_U32 maxPpOutPicWidth; /* Maximum output width of Post-Processor */ 58 RK_U32 h264Support; /* HW supports h.264 */ 59 RK_U32 jpegSupport; /* HW supports JPEG */ 60 RK_U32 mpeg4Support; /* HW supports MPEG-4 */ 61 RK_U32 customMpeg4Support; /* HW supports custom MPEG-4 features */ 62 RK_U32 vc1Support; /* HW supports VC-1 Simple */ 63 RK_U32 mpeg2Support; /* HW supports MPEG-2 */ 64 RK_U32 ppSupport; /* HW supports post-processor */ 65 RK_U32 ppConfig; /* HW post-processor functions bitmask */ 66 RK_U32 resv3Support; 67 RK_U32 refBufSupport; /* HW supports reference picture buffering */ 68 RK_U32 resv2Support; 69 RK_U32 vp7Support; /* HW supports VP7 */ 70 RK_U32 vp8Support; /* HW supports VP8 */ 71 RK_U32 avsSupport; /* HW supports AVS */ 72 RK_U32 jpegESupport; /* HW supports JPEG extensions */ 73 RK_U32 resv0Support; 74 RK_U32 mvcSupport; /* HW supports H264 MVC extension */ 75 } VPUHwDecConfig_t; 76 77 /* Hardware encoder configuration description */ 78 79 typedef struct VPUHwEndConfig { 80 RK_U32 maxEncodedWidth; /* Maximum supported width for video encoding (not JPEG) */ 81 RK_U32 h264Enabled; /* HW supports H.264 */ 82 RK_U32 jpegEnabled; /* HW supports JPEG */ 83 RK_U32 mpeg4Enabled; /* HW supports MPEG-4 */ 84 RK_U32 vsEnabled; /* HW supports video stabilization */ 85 RK_U32 rgbEnabled; /* HW supports RGB input */ 86 RK_U32 reg_size; /* HW bus type in use */ 87 RK_U32 reserv[2]; 88 } VPUHwEncConfig_t; 89 90 typedef enum { 91 // common command 92 VPU_CMD_REGISTER, 93 VPU_CMD_REGISTER_ACK_OK, 94 VPU_CMD_REGISTER_ACK_FAIL, 95 VPU_CMD_UNREGISTER, 96 VPU_SEND_CONFIG, 97 VPU_SEND_CONFIG_ACK_OK, // �����óɹ���Ӳ���Զ���λ 98 VPU_SEND_CONFIG_ACK_FAIL, // ������ʧ�ܣ�Ӳ�����ش���Ӳ���Զ���λ 99 VPU_GET_HW_INFO, 100 VPU_GET_HW_INFO_ACK_OK, 101 VPU_GET_HW_INFO_ACK_FAIL, 102 VPU_CMD_BUTT, 103 } VPU_CMD_TYPE; 104 105 int VPUClientInit(VPU_CLIENT_TYPE type); 106 RK_S32 VPUClientRelease(int socket); 107 RK_S32 VPUClientSendReg(int socket, RK_U32 *regs, RK_U32 nregs); 108 RK_S32 VPUClientWaitResult(int socket, RK_U32 *regs, RK_U32 nregs, VPU_CMD_TYPE *cmd, RK_S32 *len); 109 RK_S32 VPUClientGetHwCfg(int socket, RK_U32 *cfg, RK_U32 cfg_size); 110 RK_S32 VPUClientGetIOMMUStatus(void); 111 RK_U32 VPUCheckSupportWidth(void); 112 113 void *vpu_service(void *); 114 115 #ifdef __cplusplus 116 } 117 118 #endif 119 120 #endif /* __VPU_H__ */