1 /* 2 * Copyright 2015 Rockchip Electronics Co. LTD 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __RK_VENC_CMD_H__ 18 #define __RK_VENC_CMD_H__ 19 20 #include "mpp_frame.h" 21 #include "rk_venc_rc.h" 22 23 /* 24 * Configure of encoder is very complicated. So we divide configures into 25 * four parts: 26 * 27 * 1. Rate control parameter 28 * This is quality and bitrate request from user. 29 * 30 * 2. Data source MppFrame parameter 31 * This is data source buffer information. 32 * Now it is PreP config 33 * PreP : Encoder Preprocess configuration 34 * 35 * 3. Video codec infomation 36 * This is user custormized stream information. 37 * including: 38 * H.264 / H.265 / vp8 / mjpeg 39 * 40 * 4. Misc parameter 41 * including: 42 * Split : Slice split configuration 43 * GopRef: Reference gop configuration 44 * ROI : Region Of Interest 45 * OSD : On Screen Display 46 * MD : Motion Detection 47 * 48 * The module transcation flow is as follows: 49 * 50 * + + 51 * User | Mpi/Mpp | EncImpl 52 * | | Hal 53 * | | 54 * +----------+ | +---------+ | +-----------+ 55 * | | | | +-----RcCfg-----> | 56 * | RcCfg +---------> | | | EncImpl | 57 * | | | | | +-Frame-----> | 58 * +----------+ | | | | | +--+-----^--+ 59 * | | | | | | | 60 * | | | | | | | 61 * +----------+ | | | | | syntax | 62 * | | | | | | | | | 63 * | MppFrame +---------> MppEnc +---+ | | result 64 * | | | | | | | | | 65 * +----------+ | | | | | | | 66 * | | | | | +--v-----+--+ 67 * | | | +-Frame-----> | 68 * +----------+ | | | | | | 69 * | | | | +---CodecCfg----> Hal | 70 * | CodecCfg +---------> | | | | 71 * | | | | <-----Extra-----> | 72 * +----------+ | +---------+ | +-----------+ 73 * | | 74 * | | 75 * + + 76 * 77 * The function call flow is shown below: 78 * 79 * mpi mpp_enc controller hal 80 * + + + + 81 * | | | | 82 * | | | | 83 * +----------init------------> | | 84 * | | | | 85 * | | | | 86 * | PrepCfg | | | 87 * +---------control----------> PrepCfg | | 88 * | +-----control-----> | 89 * | | | PrepCfg | 90 * | +--------------------------control--------> 91 * | | | allocate 92 * | | | buffer 93 * | | | | 94 * | RcCfg | | | 95 * +---------control----------> RcCfg | | 96 * | +-----control-----> | 97 * | | rc_init | 98 * | | | | 99 * | | | | 100 * | CodecCfg | | | 101 * +---------control----------> | CodecCfg | 102 * | +--------------------------control--------> 103 * | | | generate 104 * | | | sps/pps 105 * | | | Get extra info | 106 * | +--------------------------control--------> 107 * | Get extra info | | | 108 * +---------control----------> | | 109 * | | | | 110 * | | | | 111 * | ROICfg | | | 112 * +---------control----------> | ROICfg | 113 * | +--------------------------control--------> 114 * | | | | 115 * | OSDCfg | | | 116 * +---------control----------> | OSDCfg | 117 * | +--------------------------control--------> 118 * | | | | 119 * | MDCfg | | | 120 * +---------control----------> | MDCfg | 121 * | +--------------------------control--------> 122 * | | | | 123 * | Set extra info | | | 124 * +---------control----------> | Set extra info | 125 * | +--------------------------control--------> 126 * | | | | 127 * | task | | | 128 * +----------encode----------> task | | 129 * | +-----encode------> | 130 * | | encode | 131 * | | | syntax | 132 * | +--------------------------gen_reg--------> 133 * | | | | 134 * | | | | 135 * | +---------------------------start---------> 136 * | | | | 137 * | | | | 138 * | +---------------------------wait----------> 139 * | | | | 140 * | | callback | | 141 * | +-----------------> | 142 * +--OSD-MD--encode----------> | | 143 * | . | | | 144 * | . | | | 145 * | . | | | 146 * +--OSD-MD--encode----------> | | 147 * | | | | 148 * +----------deinit----------> | | 149 * + + + + 150 */ 151 152 /* 153 * encoder query interface is only for debug usage 154 */ 155 #define MPP_ENC_QUERY_STATUS (0x00000001) 156 #define MPP_ENC_QUERY_WAIT (0x00000002) 157 #define MPP_ENC_QUERY_FPS (0x00000004) 158 #define MPP_ENC_QUERY_BPS (0x00000008) 159 #define MPP_ENC_QUERY_ENC_IN_FRM (0x00000010) 160 #define MPP_ENC_QUERY_ENC_WORK (0x00000020) 161 #define MPP_ENC_QUERY_ENC_OUT_PKT (0x00000040) 162 163 #define MPP_ENC_QUERY_ALL (MPP_ENC_QUERY_STATUS | \ 164 MPP_ENC_QUERY_WAIT | \ 165 MPP_ENC_QUERY_FPS | \ 166 MPP_ENC_QUERY_BPS | \ 167 MPP_ENC_QUERY_ENC_IN_FRM | \ 168 MPP_ENC_QUERY_ENC_WORK | \ 169 MPP_ENC_QUERY_ENC_OUT_PKT) 170 171 typedef struct MppEncQueryCfg_t { 172 /* 173 * 32 bit query flag for query data check 174 * Each bit represent a query data switch. 175 * bit 0 - for querying encoder runtime status 176 * bit 1 - for querying encoder runtime waiting status 177 * bit 2 - for querying encoder realtime encode fps 178 * bit 3 - for querying encoder realtime output bps 179 * bit 4 - for querying encoder input frame count 180 * bit 5 - for querying encoder start hardware times 181 * bit 6 - for querying encoder output packet count 182 */ 183 RK_U32 query_flag; 184 185 /* 64 bit query data output */ 186 RK_U32 rt_status; 187 RK_U32 rt_wait; 188 RK_U32 rt_fps; 189 RK_U32 rt_bps; 190 RK_U32 enc_in_frm_cnt; 191 RK_U32 enc_hw_run_cnt; 192 RK_U32 enc_out_pkt_cnt; 193 } MppEncQueryCfg; 194 195 /* 196 * base working mode parameter 197 */ 198 typedef enum MppEncBaseCfgChange_e { 199 MPP_ENC_BASE_CFG_CHANGE_LOW_DELAY = (1 << 0), 200 MPP_ENC_BASE_CFG_CHANGE_ALL = (0xFFFFFFFF), 201 } MppEncBaseCfgChange; 202 203 typedef struct MppEncBaseCfg_t { 204 RK_U32 change; 205 206 RK_S32 low_delay; 207 } MppEncBaseCfg; 208 209 /* 210 * Rate control parameter 211 */ 212 typedef enum MppEncRcCfgChange_e { 213 MPP_ENC_RC_CFG_CHANGE_RC_MODE = (1 << 0), 214 MPP_ENC_RC_CFG_CHANGE_QUALITY = (1 << 1), 215 MPP_ENC_RC_CFG_CHANGE_BPS = (1 << 2), /* change on bps target / max / min */ 216 MPP_ENC_RC_CFG_CHANGE_FPS_IN = (1 << 5), /* change on fps in flex / numerator / denorminator */ 217 MPP_ENC_RC_CFG_CHANGE_FPS_OUT = (1 << 6), /* change on fps out flex / numerator / denorminator */ 218 MPP_ENC_RC_CFG_CHANGE_GOP = (1 << 7), 219 MPP_ENC_RC_CFG_CHANGE_SKIP_CNT = (1 << 8), 220 MPP_ENC_RC_CFG_CHANGE_MAX_REENC = (1 << 9), 221 MPP_ENC_RC_CFG_CHANGE_DROP_FRM = (1 << 10), 222 MPP_ENC_RC_CFG_CHANGE_MAX_I_PROP = (1 << 11), 223 MPP_ENC_RC_CFG_CHANGE_MIN_I_PROP = (1 << 12), 224 MPP_ENC_RC_CFG_CHANGE_INIT_IP_RATIO = (1 << 13), 225 MPP_ENC_RC_CFG_CHANGE_PRIORITY = (1 << 14), 226 MPP_ENC_RC_CFG_CHANGE_SUPER_FRM = (1 << 15), 227 /* qp related change flag */ 228 MPP_ENC_RC_CFG_CHANGE_QP_INIT = (1 << 16), 229 MPP_ENC_RC_CFG_CHANGE_QP_RANGE = (1 << 17), 230 MPP_ENC_RC_CFG_CHANGE_QP_RANGE_I = (1 << 18), 231 MPP_ENC_RC_CFG_CHANGE_QP_MAX_STEP = (1 << 19), 232 MPP_ENC_RC_CFG_CHANGE_QP_IP = (1 << 20), 233 MPP_ENC_RC_CFG_CHANGE_QP_VI = (1 << 21), 234 MPP_ENC_RC_CFG_CHANGE_QP_ROW = (1 << 22), 235 MPP_ENC_RC_CFG_CHANGE_QP_ROW_I = (1 << 23), 236 MPP_ENC_RC_CFG_CHANGE_DEBREATH = (1 << 24), 237 MPP_ENC_RC_CFG_CHANGE_HIER_QP = (1 << 25), 238 MPP_ENC_RC_CFG_CHANGE_ST_TIME = (1 << 26), 239 MPP_ENC_RC_CFG_CHANGE_ALL = (0xFFFFFFFF), 240 } MppEncRcCfgChange; 241 242 typedef enum MppEncRcQuality_e { 243 MPP_ENC_RC_QUALITY_WORST, 244 MPP_ENC_RC_QUALITY_WORSE, 245 MPP_ENC_RC_QUALITY_MEDIUM, 246 MPP_ENC_RC_QUALITY_BETTER, 247 MPP_ENC_RC_QUALITY_BEST, 248 MPP_ENC_RC_QUALITY_CQP, 249 MPP_ENC_RC_QUALITY_AQ_ONLY, 250 MPP_ENC_RC_QUALITY_BUTT 251 } MppEncRcQuality; 252 253 typedef struct MppEncRcCfg_t { 254 RK_U32 change; 255 256 /* 257 * rc_mode - rate control mode 258 * 259 * mpp provide two rate control mode: 260 * 261 * Constant Bit Rate (CBR) mode 262 * - paramter 'bps*' define target bps 263 * - paramter quality and qp will not take effect 264 * 265 * Variable Bit Rate (VBR) mode 266 * - paramter 'quality' define 5 quality levels 267 * - paramter 'bps*' is used as reference but not strict condition 268 * - special Constant QP (CQP) mode is under VBR mode 269 * CQP mode will work with qp in CodecCfg. But only use for test 270 * 271 * default: CBR 272 */ 273 MppEncRcMode rc_mode; 274 275 /* 276 * quality - quality parameter, only takes effect in VBR mode 277 * 278 * Mpp does not give the direct parameter in different protocol. 279 * 280 * Mpp provide total 5 quality level: 281 * Worst - worse - Medium - better - best 282 * 283 * extra CQP level means special constant-qp (CQP) mode 284 * 285 * default value: Medium 286 */ 287 MppEncRcQuality quality; 288 289 /* 290 * bit rate parameters 291 * mpp gives three bit rate control parameter for control 292 * bps_target - target bit rate, unit: bit per second 293 * bps_max - maximun bit rate, unit: bit per second 294 * bps_min - minimun bit rate, unit: bit per second 295 * if user need constant bit rate set parameters to the similar value 296 * if user need variable bit rate set parameters as they need 297 */ 298 RK_S32 bps_target; 299 RK_S32 bps_max; 300 RK_S32 bps_min; 301 302 /* 303 * frame rate parameters have great effect on rate control 304 * 305 * fps_in_flex 306 * 0 - fix input frame rate 307 * 1 - variable input frame rate 308 * 309 * fps_in_num 310 * input frame rate numerator, if 0 then default 30 311 * 312 * fps_in_denorm 313 * input frame rate denorminator, if 0 then default 1 314 * 315 * fps_out_flex 316 * 0 - fix output frame rate 317 * 1 - variable output frame rate 318 * 319 * fps_out_num 320 * output frame rate numerator, if 0 then default 30 321 * 322 * fps_out_denorm 323 * output frame rate denorminator, if 0 then default 1 324 */ 325 RK_S32 fps_in_flex; 326 RK_S32 fps_in_num; 327 RK_S32 fps_in_denorm; 328 RK_S32 fps_out_flex; 329 RK_S32 fps_out_num; 330 RK_S32 fps_out_denorm; 331 332 /* 333 * gop - group of picture, gap between Intra frame 334 * 0 for only 1 I frame the rest are all P frames 335 * 1 for all I frame 336 * 2 for I P I P I P 337 * 3 for I P P I P P 338 * etc... 339 */ 340 RK_S32 gop; 341 342 /* 343 * skip_cnt - max continuous frame skip count 344 * 0 - frame skip is not allow 345 */ 346 RK_S32 skip_cnt; 347 348 /* 349 * max_reenc_times - max reencode time for one frame 350 * 0 - reencode is not allowed 351 * 1~3 max reencode time is limited to 3 352 */ 353 RK_U32 max_reenc_times; 354 355 /* 356 * stats_time - the time of bitrate statistics 357 */ 358 RK_S32 stats_time; 359 360 /* 361 * drop frame parameters 362 * used on bitrate is far over the max bitrate 363 * 364 * drop_mode 365 * 366 * MPP_ENC_RC_DROP_FRM_DISABLED 367 * - do not drop frame when bitrate overflow. 368 * MPP_ENC_RC_DROP_FRM_NORMAL 369 * - do not encode the dropped frame when bitrate overflow. 370 * MPP_ENC_RC_DROP_FRM_PSKIP 371 * - encode a all skip frame when bitrate overflow. 372 * 373 * drop_threshold 374 * 375 * The percentage threshold over max_bitrate for trigger frame drop. 376 * 377 * drop_gap 378 * The max continuous frame drop number 379 */ 380 MppEncRcDropFrmMode drop_mode; 381 RK_U32 drop_threshold; 382 RK_U32 drop_gap; 383 384 MppEncRcSuperFrameMode super_mode; 385 RK_U32 super_i_thd; 386 RK_U32 super_p_thd; 387 388 MppEncRcPriority rc_priority; 389 390 RK_U32 debreath_en; 391 RK_U32 debre_strength; 392 RK_S32 max_i_prop; 393 RK_S32 min_i_prop; 394 RK_S32 init_ip_ratio; 395 396 /* general qp control */ 397 RK_S32 qp_init; 398 RK_S32 qp_max; 399 RK_S32 qp_max_i; 400 RK_S32 qp_min; 401 RK_S32 qp_min_i; 402 RK_S32 qp_max_step; /* delta qp between each two P frame */ 403 RK_S32 qp_delta_ip; /* delta qp between I and P */ 404 RK_S32 qp_delta_vi; /* delta qp between vi and P */ 405 406 RK_S32 hier_qp_en; 407 RK_S32 hier_qp_delta[4]; 408 RK_S32 hier_frame_num[4]; 409 } MppEncRcCfg; 410 411 412 typedef enum MppEncHwCfgChange_e { 413 /* qp related hardware config flag */ 414 MPP_ENC_HW_CFG_CHANGE_QP_ROW = (1 << 0), 415 MPP_ENC_HW_CFG_CHANGE_QP_ROW_I = (1 << 1), 416 MPP_ENC_HW_CFG_CHANGE_AQ_THRD_I = (1 << 2), 417 MPP_ENC_HW_CFG_CHANGE_AQ_THRD_P = (1 << 3), 418 MPP_ENC_HW_CFG_CHANGE_AQ_STEP_I = (1 << 4), 419 MPP_ENC_HW_CFG_CHANGE_AQ_STEP_P = (1 << 5), 420 MPP_ENC_HW_CFG_CHANGE_MB_RC = (1 << 6), 421 MPP_ENC_HW_CFG_CHANGE_CU_MODE_BIAS = (1 << 8), 422 MPP_ENC_HW_CFG_CHANGE_CU_SKIP_BIAS = (1 << 9), 423 MPP_ENC_HW_CFG_CHANGE_ALL = (0xFFFFFFFF), 424 } MppEncHwCfgChange; 425 426 /* 427 * Hardware related rate control config 428 * 429 * This config will open some detail feature to external user to control 430 * hardware behavior directly. 431 */ 432 typedef struct MppEncHwCfg_t { 433 RK_U32 change; 434 435 /* vepu541/vepu540 */ 436 RK_S32 qp_delta_row; /* delta qp between two row in P frame */ 437 RK_S32 qp_delta_row_i; /* delta qp between two row in I frame */ 438 RK_U32 aq_thrd_i[16]; 439 RK_U32 aq_thrd_p[16]; 440 RK_S32 aq_step_i[16]; 441 RK_S32 aq_step_p[16]; 442 443 /* vepu1/2 */ 444 RK_S32 mb_rc_disable; 445 446 /* vepu580 */ 447 RK_S32 extra_buf; 448 449 /* 450 * block mode decision bias config 451 * 0 - intra32x32 452 * 1 - intra16x16 453 * 2 - intra8x8 454 * 3 - intra4x4 455 * 4 - inter64x64 456 * 5 - inter32x32 457 * 6 - inter16x16 458 * 7 - inter8x8 459 * value range 0 ~ 15, default : 8 460 * If the value is smaller then encoder will be more likely to encode corresponding block mode. 461 */ 462 RK_S32 mode_bias[8]; 463 464 /* 465 * skip mode bias config 466 * skip_bias_en - enable flag for skip bias config 467 * skip_sad - sad threshold for skip / non-skip 468 * skip_bias - tendency for skip, value range 0 ~ 15, default : 8 469 * If the value is smaller then encoder will be more likely to encode skip block. 470 */ 471 RK_S32 skip_bias_en; 472 RK_S32 skip_sad; 473 RK_S32 skip_bias; 474 } MppEncHwCfg; 475 476 /* 477 * Mpp preprocess parameter 478 */ 479 typedef enum MppEncPrepCfgChange_e { 480 MPP_ENC_PREP_CFG_CHANGE_INPUT = (1 << 0), /* change on input config */ 481 MPP_ENC_PREP_CFG_CHANGE_FORMAT = (1 << 2), /* change on format */ 482 /* transform parameter */ 483 MPP_ENC_PREP_CFG_CHANGE_ROTATION = (1 << 4), /* change on ration */ 484 MPP_ENC_PREP_CFG_CHANGE_MIRRORING = (1 << 5), /* change on mirroring */ 485 /* enhancement parameter */ 486 MPP_ENC_PREP_CFG_CHANGE_DENOISE = (1 << 8), /* change on denoise */ 487 MPP_ENC_PREP_CFG_CHANGE_SHARPEN = (1 << 9), /* change on denoise */ 488 /* color related parameter */ 489 MPP_ENC_PREP_CFG_CHANGE_COLOR_RANGE = (1 << 16), /* change on color range */ 490 MPP_ENC_PREP_CFG_CHANGE_COLOR_SPACE = (1 << 17), /* change on color range */ 491 MPP_ENC_PREP_CFG_CHANGE_COLOR_PRIME = (1 << 18), /* change on color primaries */ 492 MPP_ENC_PREP_CFG_CHANGE_COLOR_TRC = (1 << 19), /* change on color transfer */ 493 494 MPP_ENC_PREP_CFG_CHANGE_ALL = (0xFFFFFFFF), 495 } MppEncPrepCfgChange; 496 497 /* 498 * Preprocess sharpen parameter 499 * 500 * 5x5 sharpen core 501 * 502 * enable_y - enable luma sharpen 503 * enable_uv - enable chroma sharpen 504 */ 505 typedef struct { 506 RK_U32 enable_y; 507 RK_U32 enable_uv; 508 RK_S32 coef[5]; 509 RK_S32 div; 510 RK_S32 threshold; 511 } MppEncPrepSharpenCfg; 512 513 /* 514 * input frame rotation parameter 515 * 0 - disable rotation 516 * 1 - 90 degree 517 * 2 - 180 degree 518 * 3 - 270 degree 519 */ 520 typedef enum MppEncRotationCfg_e { 521 MPP_ENC_ROT_0, 522 MPP_ENC_ROT_90, 523 MPP_ENC_ROT_180, 524 MPP_ENC_ROT_270, 525 MPP_ENC_ROT_BUTT 526 } MppEncRotationCfg; 527 528 typedef struct MppEncPrepCfg_t { 529 RK_U32 change; 530 531 /* 532 * Mpp encoder input data dimension config 533 * 534 * width / height / hor_stride / ver_stride / format 535 * These information will be used for buffer allocation and rc config init 536 * The output format is always YUV420. So if input is RGB then color 537 * conversion will be done internally 538 */ 539 RK_S32 width; 540 RK_S32 height; 541 RK_S32 hor_stride; 542 RK_S32 ver_stride; 543 544 /* 545 * Mpp encoder input data format config 546 */ 547 MppFrameFormat format; 548 MppFrameColorSpace color; 549 MppFrameColorPrimaries colorprim; 550 MppFrameColorTransferCharacteristic colortrc; 551 MppFrameColorRange range; 552 553 MppEncRotationCfg rotation; 554 555 /* 556 * input frame mirroring parameter 557 * 0 - disable mirroring 558 * 1 - horizontal mirroring 559 * 2 - vertical mirroring 560 */ 561 RK_S32 mirroring; 562 563 /* 564 * TODO: 565 */ 566 RK_S32 denoise; 567 568 MppEncPrepSharpenCfg sharpen; 569 } MppEncPrepCfg; 570 571 /* 572 * Mpp Motion Detection parameter 573 * 574 * Mpp can output Motion Detection infomation for each frame. 575 * If user euqueue a encode task with KEY_MOTION_INFO by following function 576 * then encoder will output Motion Detection information to the buffer. 577 * 578 * mpp_task_meta_set_buffer(task, KEY_MOTION_INFO, buffer); 579 * 580 * Motion Detection information will be organized in this way: 581 * 1. Each 16x16 block will have a 32 bit block information which contains 582 * 15 bit SAD(Sum of Abstract Difference value 583 * 9 bit signed horizontal motion vector 584 * 8 bit signed vertical motion vector 585 * 2. The sequence of MD information in the buffer is corresponding to the 586 * block position in the frame, left-to right, top-to-bottom. 587 * 3. If the width of the frame is not a multiple of 256 pixels (16 macro 588 * blocks), DMA would extend the frame to a multiple of 256 pixels and 589 * the extended blocks' MD information are 32'h0000_0000. 590 * 4. Buffer must be ion buffer and 1024 byte aligned. 591 */ 592 typedef struct MppEncMDBlkInfo_t { 593 RK_U32 sad : 15; /* bit 0~14 - SAD */ 594 RK_S32 mvx : 9; /* bit 15~23 - signed horizontal mv */ 595 RK_S32 mvy : 8; /* bit 24~31 - signed vertical mv */ 596 } MppEncMDBlkInfo; 597 598 typedef enum MppEncHeaderMode_e { 599 /* default mode: attach vps/sps/pps only on first frame */ 600 MPP_ENC_HEADER_MODE_DEFAULT, 601 /* IDR mode: attach vps/sps/pps on each IDR frame */ 602 MPP_ENC_HEADER_MODE_EACH_IDR, 603 MPP_ENC_HEADER_MODE_BUTT, 604 } MppEncHeaderMode; 605 606 typedef enum MppEncSeiMode_e { 607 MPP_ENC_SEI_MODE_DISABLE, /* default mode, SEI writing is disabled */ 608 MPP_ENC_SEI_MODE_ONE_SEQ, /* one sequence has only one SEI */ 609 MPP_ENC_SEI_MODE_ONE_FRAME /* one frame may have one SEI, if SEI info has changed */ 610 } MppEncSeiMode; 611 612 /* 613 * Mpp codec parameter 614 * parameter is defined from here 615 */ 616 617 /* 618 * H.264 configurable parameter 619 */ 620 typedef enum MppEncH264CfgChange_e { 621 /* change on stream type */ 622 MPP_ENC_H264_CFG_STREAM_TYPE = (1 << 0), 623 /* change on svc / profile / level */ 624 MPP_ENC_H264_CFG_CHANGE_PROFILE = (1 << 1), 625 /* change on entropy_coding_mode / cabac_init_idc */ 626 MPP_ENC_H264_CFG_CHANGE_ENTROPY = (1 << 2), 627 628 /* change on transform8x8_mode */ 629 MPP_ENC_H264_CFG_CHANGE_TRANS_8x8 = (1 << 4), 630 /* change on constrained_intra_pred_mode */ 631 MPP_ENC_H264_CFG_CHANGE_CONST_INTRA = (1 << 5), 632 /* change on chroma_cb_qp_offset/ chroma_cr_qp_offset */ 633 MPP_ENC_H264_CFG_CHANGE_CHROMA_QP = (1 << 6), 634 /* change on deblock_disable / deblock_offset_alpha / deblock_offset_beta */ 635 MPP_ENC_H264_CFG_CHANGE_DEBLOCKING = (1 << 7), 636 /* change on use_longterm */ 637 MPP_ENC_H264_CFG_CHANGE_LONG_TERM = (1 << 8), 638 /* change on scaling_list_mode */ 639 MPP_ENC_H264_CFG_CHANGE_SCALING_LIST = (1 << 9), 640 /* change on poc type */ 641 MPP_ENC_H264_CFG_CHANGE_POC_TYPE = (1 << 10), 642 /* change on log2 max poc lsb minus 4 */ 643 MPP_ENC_H264_CFG_CHANGE_MAX_POC_LSB = (1 << 11), 644 /* change on log2 max frame number minus 4 */ 645 MPP_ENC_H264_CFG_CHANGE_MAX_FRM_NUM = (1 << 12), 646 /* change on gaps_in_frame_num_value_allowed_flag */ 647 MPP_ENC_H264_CFG_CHANGE_GAPS_IN_FRM_NUM = (1 << 13), 648 649 /* change on max_qp / min_qp */ 650 MPP_ENC_H264_CFG_CHANGE_QP_LIMIT = (1 << 16), 651 /* change on max_qp_i / min_qp_i */ 652 MPP_ENC_H264_CFG_CHANGE_QP_LIMIT_I = (1 << 17), 653 /* change on max_qp_step */ 654 MPP_ENC_H264_CFG_CHANGE_MAX_QP_STEP = (1 << 18), 655 /* change on qp_delta_ip */ 656 MPP_ENC_H264_CFG_CHANGE_QP_DELTA = (1 << 19), 657 /* change on intra_refresh_mode / intra_refresh_arg */ 658 MPP_ENC_H264_CFG_CHANGE_INTRA_REFRESH = (1 << 20), 659 /* change on max long-term reference frame count */ 660 MPP_ENC_H264_CFG_CHANGE_MAX_LTR = (1 << 21), 661 /* change on max temporal id */ 662 MPP_ENC_H264_CFG_CHANGE_MAX_TID = (1 << 22), 663 /* change on adding prefix nal */ 664 MPP_ENC_H264_CFG_CHANGE_ADD_PREFIX = (1 << 23), 665 /* change on base layer priority id */ 666 MPP_ENC_H264_CFG_CHANGE_BASE_LAYER_PID = (1 << 24), 667 668 /* change on vui */ 669 MPP_ENC_H264_CFG_CHANGE_VUI = (1 << 28), 670 MPP_ENC_H264_CFG_CHANGE_ALL = (0xFFFFFFFF), 671 } MppEncH264CfgChange; 672 673 typedef struct MppEncH264Cfg_t { 674 RK_U32 change; 675 676 /* 677 * H.264 stream format 678 * 0 - H.264 Annex B: NAL unit starts with '00 00 00 01' 679 * 1 - Plain NAL units without startcode 680 */ 681 RK_S32 stream_type; 682 683 /* 684 * H.264 codec syntax config 685 * 686 * do NOT setup the three option below unless you are familiar with encoder detail 687 * poc_type - picture order count type 0 ~ 2 688 * log2_max_poc_lsb - used in sps with poc_type 0, 689 * log2_max_frame_num - used in sps 690 */ 691 RK_U32 poc_type; 692 RK_U32 log2_max_poc_lsb; 693 RK_U32 log2_max_frame_num; 694 RK_U32 gaps_not_allowed; 695 696 /* 697 * H.264 profile_idc parameter 698 * 66 - Baseline profile 699 * 77 - Main profile 700 * 100 - High profile 701 */ 702 RK_S32 profile; 703 704 /* 705 * H.264 level_idc parameter 706 * 10 / 11 / 12 / 13 - qcif@15fps / cif@7.5fps / cif@15fps / cif@30fps 707 * 20 / 21 / 22 - cif@30fps / half-D1@@25fps / D1@12.5fps 708 * 30 / 31 / 32 - D1@25fps / 720p@30fps / 720p@60fps 709 * 40 / 41 / 42 - 1080p@30fps / 1080p@30fps / 1080p@60fps 710 * 50 / 51 / 52 - 4K@30fps 711 */ 712 RK_S32 level; 713 714 /* 715 * H.264 entropy coding method 716 * 0 - CAVLC 717 * 1 - CABAC 718 * When CABAC is select cabac_init_idc can be range 0~2 719 */ 720 RK_S32 entropy_coding_mode; 721 RK_S32 cabac_init_idc; 722 723 /* 724 * 8x8 intra prediction and 8x8 transform enable flag 725 * This flag can only be enable under High profile 726 * 0 : disable (BP/MP) 727 * 1 : enable (HP) 728 */ 729 RK_S32 transform8x8_mode; 730 731 /* 732 * 0 : disable 733 * 1 : enable 734 */ 735 RK_S32 constrained_intra_pred_mode; 736 737 /* 738 * 0 : flat scaling list 739 * 1 : default scaling list for all cases 740 * 2 : customized scaling list (not supported) 741 */ 742 RK_S32 scaling_list_mode; 743 744 /* 745 * chroma qp offset (-12 - 12) 746 */ 747 RK_S32 chroma_cb_qp_offset; 748 RK_S32 chroma_cr_qp_offset; 749 750 /* 751 * H.264 deblock filter mode flag 752 * 0 : enable 753 * 1 : disable 754 * 2 : disable deblocking filter at slice boundaries 755 * 756 * deblock filter offset alpha (-6 - 6) 757 * deblock filter offset beta (-6 - 6) 758 */ 759 RK_S32 deblock_disable; 760 RK_S32 deblock_offset_alpha; 761 RK_S32 deblock_offset_beta; 762 763 /* 764 * H.264 long term reference picture enable flag 765 * 0 - disable 766 * 1 - enable 767 */ 768 RK_S32 use_longterm; 769 770 /* 771 * quality config 772 * qp_max - 8 ~ 51 773 * qp_max_i - 10 ~ 40 774 * qp_min - 8 ~ 48 775 * qp_min_i - 10 ~ 40 776 * qp_max_step - max delta qp step between two frames 777 */ 778 RK_S32 qp_init; 779 RK_S16 qp_max; 780 RK_S16 qp_max_i; 781 RK_S16 qp_min; 782 RK_S16 qp_min_i; 783 RK_S16 qp_max_step; 784 RK_S16 qp_delta_ip; 785 786 /* 787 * intra fresh config 788 * 789 * intra_refresh_mode 790 * 0 - no intra refresh 791 * 1 - intra refresh by MB row 792 * 2 - intra refresh by MB column 793 * 3 - intra refresh by MB gap 794 * 795 * intra_refresh_arg 796 * mode 0 - no effect 797 * mode 1 - refresh MB row number 798 * mode 2 - refresh MB colmn number 799 * mode 3 - refresh MB gap count 800 */ 801 RK_S32 intra_refresh_mode; 802 RK_S32 intra_refresh_arg; 803 804 /* extra mode config */ 805 RK_S32 max_ltr_frames; 806 RK_S32 max_tid; 807 RK_S32 prefix_mode; 808 RK_S32 base_layer_pid; 809 } MppEncH264Cfg; 810 811 #define H265E_MAX_ROI_NUMBER 64 812 813 typedef struct H265eRect_t { 814 RK_S32 left; 815 RK_S32 right; 816 RK_S32 top; 817 RK_S32 bottom; 818 } H265eRect; 819 820 typedef struct H265eRoi_Region_t { 821 RK_U8 level; 822 H265eRect rect; 823 } H265eRoiRegion; 824 825 /* 826 * roi region only can be setting when rc_enable = 1 827 */ 828 typedef struct MppEncH265RoiCfg_t { 829 /* 830 * the value is defined by H265eCtuMethod 831 */ 832 833 RK_U8 method; 834 /* 835 * the number of roi,the value must less than H265E_MAX_ROI_NUMBER 836 */ 837 RK_S32 num; 838 839 /* delat qp using in roi region*/ 840 RK_U32 delta_qp; 841 842 /* roi region */ 843 H265eRoiRegion region[H265E_MAX_ROI_NUMBER]; 844 } MppEncH265RoiCfg; 845 846 typedef struct H265eCtuQp_t { 847 /* the qp value using in ctu region */ 848 RK_U32 qp; 849 850 /* 851 * define the ctu region 852 * method = H265E_METHOD_CUT_SIZE, the value of rect is in ctu size 853 * method = H264E_METHOD_COORDINATE,the value of rect is in coordinates 854 */ 855 H265eRect rect; 856 } H265eCtu; 857 858 typedef struct H265eCtuRegion_t { 859 /* 860 * the value is defined by H265eCtuMethod 861 */ 862 RK_U8 method; 863 864 /* 865 * the number of ctu,the value must less than H265E_MAX_ROI_NUMBER 866 */ 867 RK_S32 num; 868 869 /* ctu region */ 870 H265eCtu ctu[H265E_MAX_ROI_NUMBER]; 871 } MppEncH265CtuCfg; 872 873 /* 874 * define the method when set CTU/ROI parameters 875 * this value is using by method in H265eCtuRegion or H265eRoi struct 876 */ 877 typedef enum { 878 H265E_METHOD_CTU_SIZE, 879 H264E_METHOD_COORDINATE, 880 } H265eCtuMethod; 881 882 /* 883 * H.265 configurable parameter 884 */ 885 typedef struct MppEncH265VuiCfg_t { 886 RK_U32 change; 887 RK_S32 vui_present; 888 RK_S32 vui_aspect_ratio; 889 RK_S32 vui_sar_size; 890 RK_S32 full_range; 891 RK_S32 time_scale; 892 } MppEncH265VuiCfg; 893 894 typedef enum MppEncH265CfgChange_e { 895 /* change on stream type */ 896 MPP_ENC_H265_CFG_PROFILE_LEVEL_TILER_CHANGE = (1 << 0), 897 MPP_ENC_H265_CFG_INTRA_QP_CHANGE = (1 << 1), 898 MPP_ENC_H265_CFG_FRAME_RATE_CHANGE = (1 << 2), 899 MPP_ENC_H265_CFG_BITRATE_CHANGE = (1 << 3), 900 MPP_ENC_H265_CFG_GOP_SIZE = (1 << 4), 901 MPP_ENC_H265_CFG_RC_QP_CHANGE = (1 << 5), 902 MPP_ENC_H265_CFG_INTRA_REFRESH_CHANGE = (1 << 6), 903 MPP_ENC_H265_CFG_INDEPEND_SLICE_CHANGE = (1 << 7), 904 MPP_ENC_H265_CFG_DEPEND_SLICE_CHANGE = (1 << 8), 905 MPP_ENC_H265_CFG_CTU_CHANGE = (1 << 9), 906 MPP_ENC_H265_CFG_ROI_CHANGE = (1 << 10), 907 MPP_ENC_H265_CFG_CU_CHANGE = (1 << 11), 908 MPP_ENC_H265_CFG_DBLK_CHANGE = (1 << 12), 909 MPP_ENC_H265_CFG_SAO_CHANGE = (1 << 13), 910 MPP_ENC_H265_CFG_TRANS_CHANGE = (1 << 14), 911 MPP_ENC_H265_CFG_SLICE_CHANGE = (1 << 15), 912 MPP_ENC_H265_CFG_ENTROPY_CHANGE = (1 << 16), 913 MPP_ENC_H265_CFG_MERGE_CHANGE = (1 << 17), 914 MPP_ENC_H265_CFG_CHANGE_VUI = (1 << 18), 915 MPP_ENC_H265_CFG_RC_I_QP_CHANGE = (1 << 19), 916 MPP_ENC_H265_CFG_RC_MAX_QP_STEP_CHANGE = (1 << 21), 917 MPP_ENC_H265_CFG_RC_IP_DELTA_QP_CHANGE = (1 << 20), 918 MPP_ENC_H265_CFG_CHANGE_ALL = (0xFFFFFFFF), 919 } MppEncH265CfgChange; 920 921 typedef struct MppEncH265SliceCfg_t { 922 /* default value: 0, means no slice split*/ 923 RK_U32 split_enable; 924 925 /* 0: by bits number; 1: by lcu line number*/ 926 RK_U32 split_mode; 927 928 /* 929 * when splitmode is 0, this value presents bits number, 930 * when splitmode is 1, this value presents lcu line number 931 */ 932 RK_U32 slice_size; 933 RK_U32 slice_out; 934 RK_U32 loop_filter_across_slices_enabled_flag; 935 } MppEncH265SliceCfg; 936 937 typedef struct MppEncH265CuCfg_t { 938 RK_U32 cu32x32_en; /*default: 1 */ 939 RK_U32 cu16x16_en; /*default: 1 */ 940 RK_U32 cu8x8_en; /*default: 1 */ 941 RK_U32 cu4x4_en; /*default: 1 */ 942 943 // intra pred 944 RK_U32 constrained_intra_pred_flag; /*default: 0 */ 945 RK_U32 strong_intra_smoothing_enabled_flag; /*INTRA_SMOOTH*/ 946 RK_U32 pcm_enabled_flag; /*default: 0, enable ipcm*/ 947 RK_U32 pcm_loop_filter_disabled_flag; 948 949 } MppEncH265CuCfg; 950 951 typedef struct MppEncH265RefCfg_t { 952 RK_U32 num_lt_ref_pic; /*default: 0*/ 953 } MppEncH265RefCfg; 954 955 956 typedef struct MppEncH265DblkCfg_t { 957 RK_U32 slice_deblocking_filter_disabled_flag; /* default value: 0. {0,1} */ 958 RK_S32 slice_beta_offset_div2; /* default value: 0. [-6,+6] */ 959 RK_S32 slice_tc_offset_div2; /* default value: 0. [-6,+6] */ 960 } MppEncH265DblkCfg_t; 961 962 typedef struct MppEncH265SaoCfg_t { 963 RK_U32 slice_sao_luma_disable; 964 RK_U32 slice_sao_chroma_disable; 965 } MppEncH265SaoCfg; 966 967 typedef struct MppEncH265TransCfg_t { 968 RK_U32 transquant_bypass_enabled_flag; 969 RK_U32 transform_skip_enabled_flag; 970 RK_U32 defalut_ScalingList_enable; /* default: 0 */ 971 RK_S32 cb_qp_offset; 972 RK_S32 cr_qp_offset; 973 } MppEncH265TransCfg; 974 975 typedef struct MppEncH265MergeCfg_t { 976 RK_U32 max_mrg_cnd; 977 RK_U32 merge_up_flag; 978 RK_U32 merge_left_flag; 979 } MppEncH265MergesCfg; 980 981 typedef struct MppEncH265EntropyCfg_t { 982 RK_U32 cabac_init_flag; /* default: 0 */ 983 } MppEncH265EntropyCfg; 984 985 typedef struct MppEncH265Cfg_t { 986 RK_U32 change; 987 988 /* H.265 codec syntax config */ 989 RK_S32 profile; 990 RK_S32 level; 991 RK_S32 tier; 992 993 /* constraint intra prediction flag */ 994 RK_S32 const_intra_pred; 995 RK_S32 ctu_size; 996 RK_S32 max_cu_size; 997 RK_S32 tmvp_enable; 998 RK_S32 amp_enable; 999 RK_S32 wpp_enable; 1000 RK_S32 merge_range; 1001 RK_S32 sao_enable; 1002 RK_U32 num_ref; 1003 1004 /* quality config */ 1005 RK_S32 max_qp; 1006 RK_S32 min_qp; 1007 RK_S32 max_i_qp; 1008 RK_S32 min_i_qp; 1009 RK_S32 ip_qp_delta; 1010 RK_S32 max_delta_qp; 1011 RK_S32 intra_qp; 1012 RK_S32 gop_delta_qp; 1013 RK_S32 qp_init; 1014 RK_S32 qp_max_step; 1015 RK_S32 raw_dealt_qp; 1016 RK_U8 qpmax_map[8]; 1017 RK_U8 qpmin_map[8]; 1018 RK_S32 qpmap_mode; 1019 1020 /* intra fresh config */ 1021 RK_S32 intra_refresh_mode; 1022 RK_S32 intra_refresh_arg; 1023 1024 /* slice mode config */ 1025 RK_S32 independ_slice_mode; 1026 RK_S32 independ_slice_arg; 1027 RK_S32 depend_slice_mode; 1028 RK_S32 depend_slice_arg; 1029 1030 MppEncH265CuCfg cu_cfg; 1031 MppEncH265SliceCfg slice_cfg; 1032 MppEncH265EntropyCfg entropy_cfg; 1033 MppEncH265TransCfg trans_cfg; 1034 MppEncH265SaoCfg sao_cfg; 1035 MppEncH265DblkCfg_t dblk_cfg; 1036 MppEncH265RefCfg ref_cfg; 1037 MppEncH265MergesCfg merge_cfg; 1038 1039 /* extra info */ 1040 MppEncH265VuiCfg vui; 1041 1042 MppEncH265CtuCfg ctu; 1043 MppEncH265RoiCfg roi; 1044 } MppEncH265Cfg; 1045 1046 /* 1047 * motion jpeg configurable parameter 1048 */ 1049 typedef enum MppEncJpegCfgChange_e { 1050 /* change on quant parameter */ 1051 MPP_ENC_JPEG_CFG_CHANGE_QP = (1 << 0), 1052 MPP_ENC_JPEG_CFG_CHANGE_QTABLE = (1 << 1), 1053 MPP_ENC_JPEG_CFG_CHANGE_QFACTOR = (1 << 2), 1054 MPP_ENC_JPEG_CFG_CHANGE_ALL = (0xFFFFFFFF), 1055 } MppEncJpegCfgChange; 1056 1057 typedef struct MppEncJpegCfg_t { 1058 RK_U32 change; 1059 RK_S32 quant; 1060 /* 1061 * quality factor config 1062 * 1063 * q_factor - 1 ~ 99 1064 * qf_max - 1 ~ 99 1065 * qf_min - 1 ~ 99 1066 * qtable_y: qtable for luma 1067 * qtable_u: qtable for chroma 1068 * qtable_v: default equal qtable_u 1069 */ 1070 RK_S32 q_factor; 1071 RK_S32 qf_max; 1072 RK_S32 qf_min; 1073 RK_U8 *qtable_y; 1074 RK_U8 *qtable_u; 1075 RK_U8 *qtable_v; 1076 } MppEncJpegCfg; 1077 1078 /* 1079 * vp8 configurable parameter 1080 */ 1081 typedef enum MppEncVP8CfgChange_e { 1082 MPP_ENC_VP8_CFG_CHANGE_QP = (1 << 0), 1083 MPP_ENC_VP8_CFG_CHANGE_DIS_IVF = (1 << 1), 1084 MPP_ENC_VP8_CFG_CHANGE_ALL = (0xFFFFFFFF), 1085 } MppEncVP8CfgChange; 1086 1087 typedef struct MppEncVp8Cfg_t { 1088 RK_U32 change; 1089 RK_S32 quant; 1090 1091 RK_S32 qp_init; 1092 RK_S32 qp_max; 1093 RK_S32 qp_max_i; 1094 RK_S32 qp_min; 1095 RK_S32 qp_min_i; 1096 RK_S32 qp_max_step; 1097 RK_S32 disable_ivf; 1098 } MppEncVp8Cfg; 1099 1100 /** 1101 * @ingroup rk_mpi 1102 * @brief MPP encoder codec configuration parameters 1103 * @details The encoder codec configuration parameters are different for each 1104 * compression codings. For example, H.264 encoder can configure 1105 * profile, level, qp, etc. while jpeg encoder can configure qp 1106 * only. The detailed parameters can refer the corresponding data 1107 * structure such as MppEncH264Cfg and MppEncJpegCfg. This data 1108 * structure is associated with MPP_ENC_SET_CODEC_CFG command. 1109 */ 1110 typedef struct MppEncCodecCfg_t { 1111 MppCodingType coding; 1112 1113 union { 1114 RK_U32 change; 1115 MppEncH264Cfg h264; 1116 MppEncH265Cfg h265; 1117 MppEncJpegCfg jpeg; 1118 MppEncVp8Cfg vp8; 1119 }; 1120 } MppEncCodecCfg; 1121 1122 typedef enum MppEncSliceSplit_e { 1123 /* change on quant parameter */ 1124 MPP_ENC_SPLIT_CFG_CHANGE_MODE = (1 << 0), 1125 MPP_ENC_SPLIT_CFG_CHANGE_ARG = (1 << 1), 1126 MPP_ENC_SPLIT_CFG_CHANGE_OUTPUT = (1 << 2), 1127 MPP_ENC_SPLIT_CFG_CHANGE_ALL = (0xFFFFFFFF), 1128 } MppEncSliceSplitChange; 1129 1130 typedef enum MppEncSplitMode_e { 1131 MPP_ENC_SPLIT_NONE, 1132 MPP_ENC_SPLIT_BY_BYTE, 1133 MPP_ENC_SPLIT_BY_CTU, 1134 } MppEncSplitMode; 1135 1136 typedef enum MppEncSplitOutMode_e { 1137 MPP_ENC_SPLIT_OUT_LOWDELAY = (1 << 0), 1138 MPP_ENC_SPLIT_OUT_SEGMENT = (1 << 1), 1139 } MppEncSplitOutMode; 1140 1141 typedef struct MppEncSliceSplit_t { 1142 RK_U32 change; 1143 1144 /* 1145 * slice split mode 1146 * 1147 * MPP_ENC_SPLIT_NONE - No slice is split 1148 * MPP_ENC_SPLIT_BY_BYTE - Slice is split by byte number 1149 * MPP_ENC_SPLIT_BY_CTU - Slice is split by macroblock / ctu number 1150 */ 1151 RK_U32 split_mode; 1152 1153 /* 1154 * slice split size parameter 1155 * 1156 * When split by byte number this value is the max byte number for each 1157 * slice. 1158 * When split by macroblock / ctu number this value is the MB/CTU number 1159 * for each slice. 1160 */ 1161 RK_U32 split_arg; 1162 1163 /* 1164 * slice split output mode 1165 * 1166 * MPP_ENC_SPLIT_OUT_LOWDELAY 1167 * - When enabled encoder will lowdelay output each slice in a single packet 1168 * MPP_ENC_SPLIT_OUT_SEGMENT 1169 * - When enabled encoder will packet with segment info for each slice 1170 */ 1171 RK_U32 split_out; 1172 } MppEncSliceSplit; 1173 1174 /** 1175 * @brief Mpp ROI parameter 1176 * Region configure define a rectangle as ROI 1177 * @note x, y, w, h are calculated in pixels, which had better be 16-pixel aligned. 1178 * These parameters MUST retain in memory when encoder is running. 1179 * Both absolute qp and relative qp are supported in vepu541. 1180 * Only absolute qp is supported in rv1108 1181 */ 1182 typedef struct MppEncROIRegion_t { 1183 RK_U16 x; /**< horizontal position of top left corner */ 1184 RK_U16 y; /**< vertical position of top left corner */ 1185 RK_U16 w; /**< width of ROI rectangle */ 1186 RK_U16 h; /**< height of ROI rectangle */ 1187 RK_U16 intra; /**< flag of forced intra macroblock */ 1188 RK_S16 quality; /**< absolute / relative qp of macroblock */ 1189 RK_U16 qp_area_idx; /**< qp min max area select*/ 1190 RK_U8 area_map_en; /**< enable area map */ 1191 RK_U8 abs_qp_en; /**< absolute qp enable flag*/ 1192 } MppEncROIRegion; 1193 1194 /** 1195 * @brief MPP encoder's ROI configuration 1196 */ 1197 typedef struct MppEncROICfg_t { 1198 RK_U32 number; /**< ROI rectangle number */ 1199 MppEncROIRegion *regions; /**< ROI parameters */ 1200 } MppEncROICfg; 1201 1202 /** 1203 * @brief Mpp ROI parameter for vepu54x / vepu58x 1204 * @note These encoders have more complex roi configure structure. 1205 * User need to generate roi structure data for different soc. 1206 * And send buffers to encoder through metadata. 1207 */ 1208 typedef struct MppEncROICfg2_t { 1209 MppBuffer base_cfg_buf; 1210 MppBuffer qp_cfg_buf; 1211 MppBuffer amv_cfg_buf; 1212 MppBuffer mv_cfg_buf; 1213 1214 RK_U32 roi_qp_en : 1; 1215 RK_U32 roi_amv_en : 1; 1216 RK_U32 roi_mv_en : 1; 1217 RK_U32 reserve_bits : 29; 1218 RK_U32 reserve[3]; 1219 } MppEncROICfg2; 1220 1221 /* 1222 * Mpp OSD parameter 1223 * 1224 * Mpp OSD support total 8 regions 1225 * Mpp OSD support 256-color palette two mode palette: 1226 * 1. Configurable OSD palette 1227 * When palette is set. 1228 * 2. fixed OSD palette 1229 * When palette is NULL. 1230 * 1231 * if MppEncOSDPlt.buf != NULL , palette includes maximun 256 levels, 1232 * every level composed of 32 bits defined below: 1233 * Y : 8 bits 1234 * U : 8 bits 1235 * V : 8 bits 1236 * alpha : 8 bits 1237 */ 1238 #define MPP_ENC_OSD_PLT_WHITE ((255<<24)|(128<<16)|(128<<8)|235) 1239 #define MPP_ENC_OSD_PLT_YELLOW ((255<<24)|(146<<16)|( 16<<8)|210) 1240 #define MPP_ENC_OSD_PLT_CYAN ((255<<24)|( 16<<16)|(166<<8)|170) 1241 #define MPP_ENC_OSD_PLT_GREEN ((255<<24)|( 34<<16)|( 54<<8)|145) 1242 #define MPP_ENC_OSD_PLT_TRANS (( 0<<24)|(222<<16)|(202<<8)|106) 1243 #define MPP_ENC_OSD_PLT_RED ((255<<24)|(240<<16)|( 90<<8)| 81) 1244 #define MPP_ENC_OSD_PLT_BLUE ((255<<24)|(110<<16)|(240<<8)| 41) 1245 #define MPP_ENC_OSD_PLT_BLACK ((255<<24)|(128<<16)|(128<<8)| 16) 1246 1247 typedef enum MppEncOSDPltType_e { 1248 MPP_ENC_OSD_PLT_TYPE_DEFAULT, 1249 MPP_ENC_OSD_PLT_TYPE_USERDEF, 1250 MPP_ENC_OSD_PLT_TYPE_BUTT, 1251 } MppEncOSDPltType; 1252 1253 /* OSD palette value define */ 1254 typedef union MppEncOSDPltVal_u { 1255 struct { 1256 RK_U32 v : 8; 1257 RK_U32 u : 8; 1258 RK_U32 y : 8; 1259 RK_U32 alpha : 8; 1260 }; 1261 RK_U32 val; 1262 } MppEncOSDPltVal; 1263 1264 typedef struct MppEncOSDPlt_t { 1265 MppEncOSDPltVal data[256]; 1266 } MppEncOSDPlt; 1267 1268 typedef enum MppEncOSDPltCfgChange_e { 1269 MPP_ENC_OSD_PLT_CFG_CHANGE_MODE = (1 << 0), /* change osd plt type */ 1270 MPP_ENC_OSD_PLT_CFG_CHANGE_PLT_VAL = (1 << 1), /* change osd plt table value */ 1271 MPP_ENC_OSD_PLT_CFG_CHANGE_ALL = (0xFFFFFFFF), 1272 } MppEncOSDPltCfgChange; 1273 1274 typedef struct MppEncOSDPltCfg_t { 1275 RK_U32 change; 1276 MppEncOSDPltType type; 1277 MppEncOSDPlt *plt; 1278 } MppEncOSDPltCfg; 1279 1280 /* position info is unit in 16 pixels(one MB), and 1281 * x-directon range in pixels = (rd_pos_x - lt_pos_x + 1) * 16; 1282 * y-directon range in pixels = (rd_pos_y - lt_pos_y + 1) * 16; 1283 */ 1284 typedef struct MppEncOSDRegion_t { 1285 RK_U32 enable; 1286 RK_U32 inverse; 1287 RK_U32 start_mb_x; 1288 RK_U32 start_mb_y; 1289 RK_U32 num_mb_x; 1290 RK_U32 num_mb_y; 1291 RK_U32 buf_offset; 1292 } MppEncOSDRegion; 1293 1294 /* if num_region > 0 && region==NULL 1295 * use old osd data 1296 */ 1297 typedef struct MppEncOSDData_t { 1298 MppBuffer buf; 1299 RK_U32 num_region; 1300 MppEncOSDRegion region[8]; 1301 } MppEncOSDData; 1302 1303 typedef struct MppEncOSDRegion2_t { 1304 RK_U32 enable; 1305 RK_U32 inverse; 1306 RK_U32 start_mb_x; 1307 RK_U32 start_mb_y; 1308 RK_U32 num_mb_x; 1309 RK_U32 num_mb_y; 1310 RK_U32 buf_offset; 1311 MppBuffer buf; 1312 } MppEncOSDRegion2; 1313 1314 typedef struct MppEncOSDData2_t { 1315 RK_U32 num_region; 1316 MppEncOSDRegion2 region[8]; 1317 } MppEncOSDData2; 1318 1319 typedef struct MppEncUserData_t { 1320 RK_U32 len; 1321 void *pdata; 1322 } MppEncUserData; 1323 1324 typedef struct MppEncUserDataFull_t { 1325 RK_U32 len; 1326 RK_U8 *uuid; 1327 void *pdata; 1328 } MppEncUserDataFull; 1329 1330 typedef struct MppEncUserDataSet_t { 1331 RK_U32 count; 1332 MppEncUserDataFull *datas; 1333 } MppEncUserDataSet; 1334 1335 typedef enum MppEncSceneMode_e { 1336 MPP_ENC_SCENE_MODE_DEFAULT, 1337 MPP_ENC_SCENE_MODE_IPC, 1338 MPP_ENC_SCENE_MODE_BUTT, 1339 } MppEncSceneMode; 1340 1341 typedef enum MppEncFineTuneCfgChange_e { 1342 /* change on scene mode */ 1343 MPP_ENC_TUNE_CFG_CHANGE_SCENE_MODE = (1 << 0), 1344 } MppEncFineTuneCfgChange; 1345 1346 typedef struct MppEncFineTuneCfg_t { 1347 RK_U32 change; 1348 1349 MppEncSceneMode scene_mode; 1350 } MppEncFineTuneCfg; 1351 1352 #endif /*__RK_VENC_CMD_H__*/ 1353