1 /* 2 * Copyright 2015 Rockchip Electronics Co. LTD 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __VPU_H__ 18 #define __VPU_H__ 19 20 #ifdef __cplusplus 21 extern "C" { 22 #endif 23 24 #include "rk_type.h" 25 26 #define VPU_SUCCESS (0) 27 #define VPU_FAILURE (-1) 28 29 #define VPU_HW_WAIT_OK VPU_SUCCESS 30 #define VPU_HW_WAIT_ERROR VPU_FAILURE 31 #define VPU_HW_WAIT_TIMEOUT 1 32 33 // vpu decoder 60 registers, size 240B 34 #define VPU_REG_NUM_DEC (60) 35 // vpu post processor 41 registers, size 164B 36 #define VPU_REG_NUM_PP (41) 37 // vpu decoder + post processor 101 registers, size 404B 38 #define VPU_REG_NUM_DEC_PP (VPU_REG_NUM_DEC+VPU_REG_NUM_PP) 39 // vpu encoder 96 registers, size 384B 40 #define VPU_REG_NUM_ENC (96) 41 42 typedef enum { 43 VPU_ENC = 0x0, 44 VPU_DEC = 0x1, 45 VPU_PP = 0x2, 46 VPU_DEC_PP = 0x3, 47 VPU_DEC_HEVC = 0x4, 48 VPU_DEC_RKV = 0x5, 49 VPU_ENC_RKV = 0x6, 50 VPU_DEC_AVS = 0x7, 51 VPU_ENC_VEPU22 = 0x8, 52 VPU_TYPE_BUTT , 53 } VPU_CLIENT_TYPE; 54 55 /* Hardware decoder configuration description */ 56 57 typedef struct VPUHwDecConfig { 58 RK_U32 maxDecPicWidth; /* Maximum video decoding width supported */ 59 RK_U32 maxPpOutPicWidth; /* Maximum output width of Post-Processor */ 60 RK_U32 h264Support; /* HW supports h.264 */ 61 RK_U32 jpegSupport; /* HW supports JPEG */ 62 RK_U32 mpeg4Support; /* HW supports MPEG-4 */ 63 RK_U32 customMpeg4Support; /* HW supports custom MPEG-4 features */ 64 RK_U32 vc1Support; /* HW supports VC-1 Simple */ 65 RK_U32 mpeg2Support; /* HW supports MPEG-2 */ 66 RK_U32 ppSupport; /* HW supports post-processor */ 67 RK_U32 ppConfig; /* HW post-processor functions bitmask */ 68 RK_U32 sorensonSparkSupport; /* HW supports Sorenson Spark */ 69 RK_U32 refBufSupport; /* HW supports reference picture buffering */ 70 RK_U32 vp6Support; /* HW supports VP6 */ 71 RK_U32 vp7Support; /* HW supports VP7 */ 72 RK_U32 vp8Support; /* HW supports VP8 */ 73 RK_U32 avsSupport; /* HW supports AVS */ 74 RK_U32 jpegESupport; /* HW supports JPEG extensions */ 75 RK_U32 rvSupport; /* HW supports REAL */ 76 RK_U32 mvcSupport; /* HW supports H264 MVC extension */ 77 } VPUHwDecConfig_t; 78 79 /* Hardware encoder configuration description */ 80 81 typedef struct VPUHwEndConfig { 82 RK_U32 maxEncodedWidth; /* Maximum supported width for video encoding (not JPEG) */ 83 RK_U32 h264Enabled; /* HW supports H.264 */ 84 RK_U32 jpegEnabled; /* HW supports JPEG */ 85 RK_U32 mpeg4Enabled; /* HW supports MPEG-4 */ 86 RK_U32 vsEnabled; /* HW supports video stabilization */ 87 RK_U32 rgbEnabled; /* HW supports RGB input */ 88 RK_U32 reg_size; /* HW bus type in use */ 89 RK_U32 reserv[2]; 90 } VPUHwEncConfig_t; 91 92 typedef enum { 93 // common command 94 VPU_CMD_REGISTER , 95 VPU_CMD_REGISTER_ACK_OK , 96 VPU_CMD_REGISTER_ACK_FAIL , 97 VPU_CMD_UNREGISTER , 98 99 VPU_SEND_CONFIG , 100 VPU_SEND_CONFIG_ACK_OK , 101 VPU_SEND_CONFIG_ACK_FAIL , 102 103 VPU_GET_HW_INFO , 104 VPU_GET_HW_INFO_ACK_OK , 105 VPU_GET_HW_INFO_ACK_FAIL , 106 107 VPU_CMD_BUTT , 108 } VPU_CMD_TYPE; 109 110 int VPUClientInit(VPU_CLIENT_TYPE type); 111 RK_S32 VPUClientRelease(int socket); 112 RK_S32 VPUClientSendReg(int socket, RK_U32 *regs, RK_U32 nregs); 113 RK_S32 VPUClientSendReg2(RK_S32 socket, RK_S32 offset, RK_S32 size, void *param); 114 RK_S32 VPUClientWaitResult(int socket, RK_U32 *regs, RK_U32 nregs, VPU_CMD_TYPE *cmd, RK_S32 *len); 115 RK_S32 VPUClientGetHwCfg(int socket, RK_U32 *cfg, RK_U32 cfg_size); 116 RK_S32 VPUClientGetIOMMUStatus(); 117 RK_U32 VPUCheckSupportWidth(); 118 119 #ifdef __cplusplus 120 } 121 #endif 122 123 #endif /* __VPU_H__ */ 124