1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Author:Mark Yao <mark.yao@rock-chips.com>
5 *
6 * based on exynos_drm_drv.h
7 */
8
9 #ifndef _ROCKCHIP_DRM_DRV_H
10 #define _ROCKCHIP_DRM_DRV_H
11
12 #include <drm/drm_atomic_helper.h>
13 #include <drm/drm_dsc.h>
14 #include <drm/drm_fb_helper.h>
15 #include <drm/drm_fourcc.h>
16 #include <drm/drm_gem.h>
17 #include <uapi/drm/rockchip_drm.h>
18 #include <linux/module.h>
19 #include <linux/component.h>
20
21 #include <soc/rockchip/rockchip_dmc.h>
22
23 #include <drm/panel-simple.h>
24
25 #include <drm/rockchip_drm_debugfs.h>
26
27 #define ROCKCHIP_MAX_FB_BUFFER 3
28 #define ROCKCHIP_MAX_CONNECTOR 2
29 #define ROCKCHIP_MAX_CRTC 4
30 #define ROCKCHIP_MAX_LAYER 16
31
32
33 struct drm_device;
34 struct drm_connector;
35 struct iommu_domain;
36
37 #define VOP_OUTPUT_IF_RGB BIT(0)
38 #define VOP_OUTPUT_IF_BT1120 BIT(1)
39 #define VOP_OUTPUT_IF_BT656 BIT(2)
40 #define VOP_OUTPUT_IF_LVDS0 BIT(3)
41 #define VOP_OUTPUT_IF_LVDS1 BIT(4)
42 #define VOP_OUTPUT_IF_MIPI0 BIT(5)
43 #define VOP_OUTPUT_IF_MIPI1 BIT(6)
44 #define VOP_OUTPUT_IF_eDP0 BIT(7)
45 #define VOP_OUTPUT_IF_eDP1 BIT(8)
46 #define VOP_OUTPUT_IF_DP0 BIT(9)
47 #define VOP_OUTPUT_IF_DP1 BIT(10)
48 #define VOP_OUTPUT_IF_HDMI0 BIT(11)
49 #define VOP_OUTPUT_IF_HDMI1 BIT(12)
50
51 #ifndef DRM_FORMAT_NV20
52 #define DRM_FORMAT_NV20 fourcc_code('N', 'V', '2', '0') /* 2x1 subsampled Cr:Cb plane */
53 #endif
54
55 #ifndef DRM_FORMAT_NV30
56 #define DRM_FORMAT_NV30 fourcc_code('N', 'V', '3', '0') /* non-subsampled Cr:Cb plane */
57 #endif
58
59 struct rockchip_drm_sub_dev {
60 struct list_head list;
61 struct drm_connector *connector;
62 struct device_node *of_node;
63 void (*loader_protect)(struct drm_encoder *encoder, bool on);
64 void (*oob_hotplug_event)(struct drm_connector *connector);
65 };
66
67 struct rockchip_sdr2hdr_state {
68 int sdr2hdr_func;
69
70 bool bt1886eotf_pre_conv_en;
71 bool rgb2rgb_pre_conv_en;
72 bool rgb2rgb_pre_conv_mode;
73 bool st2084oetf_pre_conv_en;
74
75 bool bt1886eotf_post_conv_en;
76 bool rgb2rgb_post_conv_en;
77 bool rgb2rgb_post_conv_mode;
78 bool st2084oetf_post_conv_en;
79 };
80
81 struct rockchip_hdr_state {
82 bool pre_overlay;
83 bool hdr2sdr_en;
84 struct rockchip_sdr2hdr_state sdr2hdr_state;
85 };
86
87 struct rockchip_bcsh_state {
88 int brightness;
89 int contrast;
90 int saturation;
91 int sin_hue;
92 int cos_hue;
93 };
94
95 struct rockchip_crtc {
96 struct drm_crtc crtc;
97 #if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
98 /**
99 * @vop_dump_status the status of vop dump control
100 * @vop_dump_list_head the list head of vop dump list
101 * @vop_dump_list_init_flag init once
102 * @vop_dump_times control the dump times
103 * @frme_count the frame of dump buf
104 */
105 enum vop_dump_status vop_dump_status;
106 struct list_head vop_dump_list_head;
107 bool vop_dump_list_init_flag;
108 int vop_dump_times;
109 int frame_count;
110 #endif
111 };
112
113 struct rockchip_dsc_sink_cap {
114 /**
115 * @slice_width: the number of pixel columns that comprise the slice width
116 * @slice_height: the number of pixel rows that comprise the slice height
117 * @block_pred: Does block prediction
118 * @native_420: Does sink support DSC with 4:2:0 compression
119 * @bpc_supported: compressed bpc supported by sink : 10, 12 or 16 bpc
120 * @version_major: DSC major version
121 * @version_minor: DSC minor version
122 * @target_bits_per_pixel_x16: bits num after compress and multiply 16
123 */
124 u16 slice_width;
125 u16 slice_height;
126 bool block_pred;
127 bool native_420;
128 u8 bpc_supported;
129 u8 version_major;
130 u8 version_minor;
131 u16 target_bits_per_pixel_x16;
132 };
133
134 struct rockchip_crtc_state {
135 struct drm_crtc_state base;
136 int output_type;
137 int output_mode;
138 int output_bpc;
139 int output_flags;
140 bool enable_afbc;
141 /**
142 * @splice_mode: enabled when display a hdisplay > 4096 on rk3588
143 */
144 bool splice_mode;
145
146 /**
147 * @hold_mode: enabled when it's:
148 * (1) mcu hold mode
149 * (2) mipi dsi cmd mode
150 * (3) edp psr mode
151 */
152 bool hold_mode;
153
154 struct drm_tv_connector_state *tv_state;
155 int left_margin;
156 int right_margin;
157 int top_margin;
158 int bottom_margin;
159 int vdisplay;
160 int afbdc_win_format;
161 int afbdc_win_width;
162 int afbdc_win_height;
163 int afbdc_win_ptr;
164 int afbdc_win_id;
165 int afbdc_en;
166 int afbdc_win_vir_width;
167 int afbdc_win_xoffset;
168 int afbdc_win_yoffset;
169 int dsp_layer_sel;
170 u32 output_if;
171 u32 bus_format;
172 u32 bus_flags;
173 int yuv_overlay;
174 int post_r2y_en;
175 int post_y2r_en;
176 int post_csc_mode;
177 int bcsh_en;
178 int color_space;
179 int eotf;
180 u32 background;
181 u32 line_flag;
182 u8 mode_update;
183 u8 dsc_id;
184 u8 dsc_enable;
185
186 u8 dsc_slice_num;
187 u8 dsc_pixel_num;
188
189 u64 dsc_txp_clk_rate;
190 u64 dsc_pxl_clk_rate;
191 u64 dsc_cds_clk_rate;
192
193 struct drm_dsc_picture_parameter_set pps;
194 struct rockchip_dsc_sink_cap dsc_sink_cap;
195 struct rockchip_hdr_state hdr;
196 };
197
198 #define to_rockchip_crtc_state(s) \
199 container_of(s, struct rockchip_crtc_state, base)
200
201 struct rockchip_drm_vcnt {
202 struct drm_pending_vblank_event *event;
203 __u32 sequence;
204 int pipe;
205 };
206
207 struct rockchip_logo {
208 dma_addr_t dma_addr;
209 void *kvaddr;
210 phys_addr_t start;
211 phys_addr_t size;
212 int count;
213 };
214
215 struct loader_cubic_lut {
216 bool enable;
217 u32 offset;
218 };
219
220 struct rockchip_drm_dsc_cap {
221 bool v_1p2;
222 bool native_420;
223 bool all_bpp;
224 u8 bpc_supported;
225 u8 max_slices;
226 u8 max_lanes;
227 u8 max_frl_rate_per_lane;
228 u8 total_chunk_kbytes;
229 int clk_per_slice;
230 };
231
232 struct ver_26_v0 {
233 u8 yuv422_12bit;
234 u8 support_2160p_60;
235 u8 global_dimming;
236 u8 dm_major_ver;
237 u8 dm_minor_ver;
238 u16 t_min_pq;
239 u16 t_max_pq;
240 u16 rx;
241 u16 ry;
242 u16 gx;
243 u16 gy;
244 u16 bx;
245 u16 by;
246 u16 wx;
247 u16 wy;
248 } __packed;
249
250 struct ver_15_v1 {
251 u8 yuv422_12bit;
252 u8 support_2160p_60;
253 u8 global_dimming;
254 u8 dm_version;
255 u8 colorimetry;
256 u8 t_max_lum;
257 u8 t_min_lum;
258 u8 rx;
259 u8 ry;
260 u8 gx;
261 u8 gy;
262 u8 bx;
263 u8 by;
264 } __packed;
265
266 struct ver_12_v1 {
267 u8 yuv422_12bit;
268 u8 support_2160p_60;
269 u8 global_dimming;
270 u8 dm_version;
271 u8 colorimetry;
272 u8 low_latency;
273 u8 t_max_lum;
274 u8 t_min_lum;
275 u8 unique_rx;
276 u8 unique_ry;
277 u8 unique_gx;
278 u8 unique_gy;
279 u8 unique_bx;
280 u8 unique_by;
281 } __packed;
282
283 struct ver_12_v2 {
284 u8 yuv422_12bit;
285 u8 backlt_ctrl;
286 u8 global_dimming;
287 u8 dm_version;
288 u8 backlt_min_luma;
289 u8 interface;
290 u8 yuv444_10b_12b;
291 u8 t_min_pq_v2;
292 u8 t_max_pq_v2;
293 u8 unique_rx;
294 u8 unique_ry;
295 u8 unique_gx;
296 u8 unique_gy;
297 u8 unique_bx;
298 u8 unique_by;
299 } __packed;
300
301 struct next_hdr_sink_data {
302 u8 version;
303 struct ver_26_v0 ver_26_v0;
304 struct ver_15_v1 ver_15_v1;
305 struct ver_12_v1 ver_12_v1;
306 struct ver_12_v2 ver_12_v2;
307 } __packed;
308
309 /*
310 * Rockchip drm private crtc funcs.
311 * @loader_protect: protect loader logo crtc's power
312 * @enable_vblank: enable crtc vblank irq.
313 * @disable_vblank: disable crtc vblank irq.
314 * @bandwidth: report present crtc bandwidth consume.
315 */
316 struct rockchip_crtc_funcs {
317 int (*loader_protect)(struct drm_crtc *crtc, bool on);
318 int (*enable_vblank)(struct drm_crtc *crtc);
319 void (*disable_vblank)(struct drm_crtc *crtc);
320 size_t (*bandwidth)(struct drm_crtc *crtc,
321 struct drm_crtc_state *crtc_state,
322 struct dmcfreq_vop_info *vop_bw_info);
323 void (*cancel_pending_vblank)(struct drm_crtc *crtc,
324 struct drm_file *file_priv);
325 int (*debugfs_init)(struct drm_minor *minor, struct drm_crtc *crtc);
326 int (*debugfs_dump)(struct drm_crtc *crtc, struct seq_file *s);
327 void (*regs_dump)(struct drm_crtc *crtc, struct seq_file *s);
328 enum drm_mode_status (*mode_valid)(struct drm_crtc *crtc,
329 const struct drm_display_mode *mode,
330 int output_type);
331 void (*crtc_close)(struct drm_crtc *crtc);
332 void (*crtc_send_mcu_cmd)(struct drm_crtc *crtc, u32 type, u32 value);
333 void (*te_handler)(struct drm_crtc *crtc);
334 };
335
336 struct rockchip_dclk_pll {
337 struct clk *pll;
338 unsigned int use_count;
339 };
340
341 /*
342 * Rockchip drm private structure.
343 *
344 * @crtc: array of enabled CRTCs, used to map from "pipe" to drm_crtc.
345 * @num_pipe: number of pipes for this device.
346 * @mm_lock: protect drm_mm on multi-threads.
347 */
348 struct rockchip_drm_private {
349 struct rockchip_logo *logo;
350 struct drm_fb_helper *fbdev_helper;
351 struct drm_gem_object *fbdev_bo;
352 struct iommu_domain *domain;
353 struct gen_pool *secure_buffer_pool;
354 struct mutex mm_lock;
355 struct drm_mm mm;
356 struct list_head psr_list;
357 struct mutex psr_list_lock;
358 struct mutex commit_lock;
359
360 /* private crtc prop */
361 struct drm_property *soc_id_prop;
362 struct drm_property *port_id_prop;
363 struct drm_property *aclk_prop;
364 struct drm_property *bg_prop;
365 struct drm_property *line_flag_prop;
366
367 /* private plane prop */
368 struct drm_property *eotf_prop;
369 struct drm_property *color_space_prop;
370 struct drm_property *async_commit_prop;
371 struct drm_property *share_id_prop;
372
373 /* private connector prop */
374 struct drm_property *connector_id_prop;
375
376 const struct rockchip_crtc_funcs *crtc_funcs[ROCKCHIP_MAX_CRTC];
377
378 struct rockchip_dclk_pll default_pll;
379 struct rockchip_dclk_pll hdmi_pll;
380
381 /*
382 * protect some shared overlay resource
383 * OVL_LAYER_SEL/OVL_PORT_SEL
384 */
385 struct mutex ovl_lock;
386
387 struct rockchip_drm_vcnt vcnt[ROCKCHIP_MAX_CRTC];
388 /**
389 * @loader_protect
390 * ignore restore_fbdev_mode_atomic when in logo on state
391 */
392 bool loader_protect;
393
394 dma_addr_t cubic_lut_dma_addr;
395 void *cubic_lut_kvaddr;
396 struct loader_cubic_lut cubic_lut[ROCKCHIP_MAX_CRTC];
397 };
398
399 int rockchip_drm_dma_attach_device(struct drm_device *drm_dev,
400 struct device *dev);
401 void rockchip_drm_dma_detach_device(struct drm_device *drm_dev,
402 struct device *dev);
403 int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout);
404 int rockchip_register_crtc_funcs(struct drm_crtc *crtc,
405 const struct rockchip_crtc_funcs *crtc_funcs);
406 void rockchip_unregister_crtc_funcs(struct drm_crtc *crtc);
407
408 void rockchip_drm_register_sub_dev(struct rockchip_drm_sub_dev *sub_dev);
409 void rockchip_drm_unregister_sub_dev(struct rockchip_drm_sub_dev *sub_dev);
410 struct rockchip_drm_sub_dev *rockchip_drm_get_sub_dev(struct device_node *node);
411 int rockchip_drm_add_modes_noedid(struct drm_connector *connector);
412 void rockchip_drm_te_handle(struct drm_crtc *crtc);
413 void drm_mode_convert_to_split_mode(struct drm_display_mode *mode);
414 void drm_mode_convert_to_origin_mode(struct drm_display_mode *mode);
415 #if IS_ENABLED(CONFIG_DRM_ROCKCHIP)
416 int rockchip_drm_get_sub_dev_type(void);
417 #else
rockchip_drm_get_sub_dev_type(void)418 static inline int rockchip_drm_get_sub_dev_type(void)
419 {
420 return DRM_MODE_CONNECTOR_Unknown;
421 }
422 #endif
423
424 int rockchip_drm_endpoint_is_subdriver(struct device_node *ep);
425 uint32_t rockchip_drm_of_find_possible_crtcs(struct drm_device *dev,
426 struct device_node *port);
427 uint32_t rockchip_drm_get_bpp(const struct drm_format_info *info);
428 int rockchip_drm_get_yuv422_format(struct drm_connector *connector,
429 struct edid *edid);
430 int rockchip_drm_parse_cea_ext(struct rockchip_drm_dsc_cap *dsc_cap,
431 u8 *max_frl_rate_per_lane, u8 *max_lanes,
432 const struct edid *edid);
433 int rockchip_drm_parse_next_hdr(struct next_hdr_sink_data *sink_data,
434 const struct edid *edid);
435
436 extern struct platform_driver cdn_dp_driver;
437 extern struct platform_driver dw_hdmi_rockchip_pltfm_driver;
438 extern struct platform_driver dw_mipi_dsi_rockchip_driver;
439 extern struct platform_driver dw_mipi_dsi2_rockchip_driver;
440 extern struct platform_driver inno_hdmi_driver;
441 extern struct platform_driver rockchip_dp_driver;
442 extern struct platform_driver rockchip_lvds_driver;
443 extern struct platform_driver vop_platform_driver;
444 extern struct platform_driver vop2_platform_driver;
445 extern struct platform_driver rk3066_hdmi_driver;
446 extern struct platform_driver rockchip_rgb_driver;
447 extern struct platform_driver dw_dp_driver;
448 extern struct platform_driver vconn_platform_driver;
449 #endif /* _ROCKCHIP_DRM_DRV_H_ */
450