1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2013 MundoReader S.L.
4 * Author: Heiko Stuebner <heiko@sntech.de>
5 *
6 * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
7 */
8
9 #include <linux/bitops.h>
10 #include <linux/clk.h>
11 #include <linux/device.h>
12 #include <linux/err.h>
13 #include <linux/gpio/driver.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/module.h>
18 #include <linux/of.h>
19 #include <linux/of_address.h>
20 #include <linux/of_device.h>
21 #include <linux/of_irq.h>
22 #include <linux/regmap.h>
23
24 #include "../pinctrl/core.h"
25 #include "../pinctrl/pinctrl-rockchip.h"
26
27 #define GPIO_TYPE_V1 (0) /* GPIO Version ID reserved */
28 #define GPIO_TYPE_V2 (0x01000C2B) /* GPIO Version ID 0x01000C2B */
29 #define GPIO_TYPE_V2_1 (0x0101157C) /* GPIO Version ID 0x0101157C */
30
31 static const struct rockchip_gpio_regs gpio_regs_v1 = {
32 .port_dr = 0x00,
33 .port_ddr = 0x04,
34 .int_en = 0x30,
35 .int_mask = 0x34,
36 .int_type = 0x38,
37 .int_polarity = 0x3c,
38 .int_status = 0x40,
39 .int_rawstatus = 0x44,
40 .debounce = 0x48,
41 .port_eoi = 0x4c,
42 .ext_port = 0x50,
43 };
44
45 static const struct rockchip_gpio_regs gpio_regs_v2 = {
46 .port_dr = 0x00,
47 .port_ddr = 0x08,
48 .int_en = 0x10,
49 .int_mask = 0x18,
50 .int_type = 0x20,
51 .int_polarity = 0x28,
52 .int_bothedge = 0x30,
53 .int_status = 0x50,
54 .int_rawstatus = 0x58,
55 .debounce = 0x38,
56 .dbclk_div_en = 0x40,
57 .dbclk_div_con = 0x48,
58 .port_eoi = 0x60,
59 .ext_port = 0x70,
60 .version_id = 0x78,
61 };
62
gpio_writel_v2(u32 val,void __iomem * reg)63 static inline void gpio_writel_v2(u32 val, void __iomem *reg)
64 {
65 writel((val & 0xffff) | 0xffff0000, reg);
66 writel((val >> 16) | 0xffff0000, reg + 0x4);
67 }
68
gpio_readl_v2(void __iomem * reg)69 static inline u32 gpio_readl_v2(void __iomem *reg)
70 {
71 return readl(reg + 0x4) << 16 | readl(reg);
72 }
73
rockchip_gpio_writel(struct rockchip_pin_bank * bank,u32 value,unsigned int offset)74 static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank,
75 u32 value, unsigned int offset)
76 {
77 void __iomem *reg = bank->reg_base + offset;
78
79 if (bank->gpio_type == GPIO_TYPE_V2)
80 gpio_writel_v2(value, reg);
81 else
82 writel(value, reg);
83 }
84
rockchip_gpio_readl(struct rockchip_pin_bank * bank,unsigned int offset)85 static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank,
86 unsigned int offset)
87 {
88 void __iomem *reg = bank->reg_base + offset;
89 u32 value;
90
91 if (bank->gpio_type == GPIO_TYPE_V2)
92 value = gpio_readl_v2(reg);
93 else
94 value = readl(reg);
95
96 return value;
97 }
98
rockchip_gpio_writel_bit(struct rockchip_pin_bank * bank,u32 bit,u32 value,unsigned int offset)99 static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank,
100 u32 bit, u32 value,
101 unsigned int offset)
102 {
103 void __iomem *reg = bank->reg_base + offset;
104 u32 data;
105
106 if (bank->gpio_type == GPIO_TYPE_V2) {
107 if (value)
108 data = BIT(bit % 16) | BIT(bit % 16 + 16);
109 else
110 data = BIT(bit % 16 + 16);
111 writel(data, bit >= 16 ? reg + 0x4 : reg);
112 } else {
113 data = readl(reg);
114 data &= ~BIT(bit);
115 if (value)
116 data |= BIT(bit);
117 writel(data, reg);
118 }
119 }
120
rockchip_gpio_readl_bit(struct rockchip_pin_bank * bank,u32 bit,unsigned int offset)121 static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank,
122 u32 bit, unsigned int offset)
123 {
124 void __iomem *reg = bank->reg_base + offset;
125 u32 data;
126
127 if (bank->gpio_type == GPIO_TYPE_V2) {
128 data = readl(bit >= 16 ? reg + 0x4 : reg);
129 data >>= bit % 16;
130 } else {
131 data = readl(reg);
132 data >>= bit;
133 }
134
135 return data & (0x1);
136 }
137
rockchip_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)138 static int rockchip_gpio_get_direction(struct gpio_chip *chip,
139 unsigned int offset)
140 {
141 struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
142 u32 data;
143
144 data = rockchip_gpio_readl_bit(bank, offset, bank->gpio_regs->port_ddr);
145 if (data)
146 return GPIO_LINE_DIRECTION_OUT;
147
148 return GPIO_LINE_DIRECTION_IN;
149 }
150
rockchip_gpio_set_direction(struct gpio_chip * chip,unsigned int offset,bool input)151 static int rockchip_gpio_set_direction(struct gpio_chip *chip,
152 unsigned int offset, bool input)
153 {
154 struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
155 unsigned long flags;
156 u32 data = input ? 0 : 1;
157
158 raw_spin_lock_irqsave(&bank->slock, flags);
159 rockchip_gpio_writel_bit(bank, offset, data, bank->gpio_regs->port_ddr);
160 raw_spin_unlock_irqrestore(&bank->slock, flags);
161
162 return 0;
163 }
164
rockchip_gpio_set(struct gpio_chip * gc,unsigned int offset,int value)165 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned int offset,
166 int value)
167 {
168 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
169 unsigned long flags;
170
171 raw_spin_lock_irqsave(&bank->slock, flags);
172 rockchip_gpio_writel_bit(bank, offset, value, bank->gpio_regs->port_dr);
173 raw_spin_unlock_irqrestore(&bank->slock, flags);
174 }
175
rockchip_gpio_get(struct gpio_chip * gc,unsigned int offset)176 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned int offset)
177 {
178 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
179 u32 data;
180
181 data = readl(bank->reg_base + bank->gpio_regs->ext_port);
182 data >>= offset;
183 data &= 1;
184
185 return data;
186 }
187
rockchip_gpio_set_debounce(struct gpio_chip * gc,unsigned int offset,unsigned int debounce)188 static int rockchip_gpio_set_debounce(struct gpio_chip *gc,
189 unsigned int offset,
190 unsigned int debounce)
191 {
192 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
193 const struct rockchip_gpio_regs *reg = bank->gpio_regs;
194 unsigned long flags, div_reg, freq, max_debounce;
195 bool div_debounce_support;
196 unsigned int cur_div_reg;
197 u64 div;
198
199 if (bank->gpio_type == GPIO_TYPE_V2 && !IS_ERR(bank->db_clk)) {
200 div_debounce_support = true;
201 freq = clk_get_rate(bank->db_clk);
202 max_debounce = (GENMASK(23, 0) + 1) * 2 * 1000000 / freq;
203 if (debounce > max_debounce)
204 return -EINVAL;
205
206 div = debounce * freq;
207 div_reg = DIV_ROUND_CLOSEST_ULL(div, 2 * USEC_PER_SEC) - 1;
208 } else {
209 div_debounce_support = false;
210 }
211
212 raw_spin_lock_irqsave(&bank->slock, flags);
213
214 /* Only the v1 needs to configure div_en and div_con for dbclk */
215 if (debounce) {
216 if (div_debounce_support) {
217 /* Configure the max debounce from consumers */
218 cur_div_reg = readl(bank->reg_base +
219 reg->dbclk_div_con);
220 if (cur_div_reg < div_reg)
221 writel(div_reg, bank->reg_base +
222 reg->dbclk_div_con);
223 rockchip_gpio_writel_bit(bank, offset, 1,
224 reg->dbclk_div_en);
225 }
226
227 rockchip_gpio_writel_bit(bank, offset, 1, reg->debounce);
228 } else {
229 if (div_debounce_support)
230 rockchip_gpio_writel_bit(bank, offset, 0,
231 reg->dbclk_div_en);
232
233 rockchip_gpio_writel_bit(bank, offset, 0, reg->debounce);
234 }
235
236 raw_spin_unlock_irqrestore(&bank->slock, flags);
237
238 /* Enable or disable dbclk at last */
239 if (div_debounce_support) {
240 if (debounce)
241 clk_prepare_enable(bank->db_clk);
242 else
243 clk_disable_unprepare(bank->db_clk);
244 }
245
246 return 0;
247 }
248
rockchip_gpio_direction_input(struct gpio_chip * gc,unsigned int offset)249 static int rockchip_gpio_direction_input(struct gpio_chip *gc,
250 unsigned int offset)
251 {
252 return rockchip_gpio_set_direction(gc, offset, true);
253 }
254
rockchip_gpio_direction_output(struct gpio_chip * gc,unsigned int offset,int value)255 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
256 unsigned int offset, int value)
257 {
258 rockchip_gpio_set(gc, offset, value);
259
260 return rockchip_gpio_set_direction(gc, offset, false);
261 }
262
263 /*
264 * gpiolib set_config callback function. The setting of the pin
265 * mux function as 'gpio output' will be handled by the pinctrl subsystem
266 * interface.
267 */
rockchip_gpio_set_config(struct gpio_chip * gc,unsigned int offset,unsigned long config)268 static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
269 unsigned long config)
270 {
271 enum pin_config_param param = pinconf_to_config_param(config);
272 unsigned int debounce = pinconf_to_config_argument(config);
273 int ret = 0;
274
275 switch (param) {
276 case PIN_CONFIG_INPUT_DEBOUNCE:
277 /*
278 * Rockchip's gpio could only support up to one period
279 * of the debounce clock(pclk), which is far away from
280 * satisftying the requirement, as pclk is usually near
281 * 100MHz shared by all peripherals. So the fact is it
282 * has crippled debounce capability could only be useful
283 * to prevent any spurious glitches from waking up the system
284 * if the gpio is conguired as wakeup interrupt source. Let's
285 * still return -ENOTSUPP as before, to make sure the caller
286 * of gpiod_set_debounce won't change its behaviour.
287 */
288 rockchip_gpio_set_debounce(gc, offset, debounce);
289 ret = -ENOTSUPP;
290 break;
291 default:
292 ret = -ENOTSUPP;
293 break;
294 }
295
296 return ret;
297 }
298
299 /*
300 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
301 * and a virtual IRQ, if not already present.
302 */
rockchip_gpio_to_irq(struct gpio_chip * gc,unsigned int offset)303 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned int offset)
304 {
305 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
306 unsigned int virq;
307
308 if (!bank->domain)
309 return -ENXIO;
310
311 virq = irq_create_mapping(bank->domain, offset);
312
313 return (virq) ? : -ENXIO;
314 }
315
316 static const struct gpio_chip rockchip_gpiolib_chip = {
317 .request = gpiochip_generic_request,
318 .free = gpiochip_generic_free,
319 .set = rockchip_gpio_set,
320 .get = rockchip_gpio_get,
321 .get_direction = rockchip_gpio_get_direction,
322 .direction_input = rockchip_gpio_direction_input,
323 .direction_output = rockchip_gpio_direction_output,
324 .set_config = rockchip_gpio_set_config,
325 .to_irq = rockchip_gpio_to_irq,
326 .owner = THIS_MODULE,
327 };
328
rockchip_irq_demux(struct irq_desc * desc)329 static void rockchip_irq_demux(struct irq_desc *desc)
330 {
331 struct irq_chip *chip = irq_desc_get_chip(desc);
332 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
333 u32 pend;
334
335 dev_dbg(bank->dev, "got irq for bank %s\n", bank->name);
336
337 chained_irq_enter(chip, desc);
338
339 pend = readl_relaxed(bank->reg_base + bank->gpio_regs->int_status);
340
341 while (pend) {
342 unsigned int irq, virq;
343
344 irq = __ffs(pend);
345 pend &= ~BIT(irq);
346 virq = irq_find_mapping(bank->domain, irq);
347
348 if (!virq) {
349 dev_err(bank->dev, "unmapped irq %d\n", irq);
350 continue;
351 }
352
353 dev_dbg(bank->dev, "handling irq %d\n", irq);
354
355 /*
356 * Triggering IRQ on both rising and falling edge
357 * needs manual intervention.
358 */
359 if (bank->toggle_edge_mode & BIT(irq)) {
360 u32 data, data_old, polarity;
361 unsigned long flags;
362
363 data = readl_relaxed(bank->reg_base +
364 bank->gpio_regs->ext_port);
365 do {
366 raw_spin_lock_irqsave(&bank->slock, flags);
367
368 polarity = readl_relaxed(bank->reg_base +
369 bank->gpio_regs->int_polarity);
370 if (data & BIT(irq))
371 polarity &= ~BIT(irq);
372 else
373 polarity |= BIT(irq);
374 writel(polarity,
375 bank->reg_base +
376 bank->gpio_regs->int_polarity);
377
378 raw_spin_unlock_irqrestore(&bank->slock, flags);
379
380 data_old = data;
381 data = readl_relaxed(bank->reg_base +
382 bank->gpio_regs->ext_port);
383 } while ((data & BIT(irq)) != (data_old & BIT(irq)));
384 }
385
386 generic_handle_irq(virq);
387 }
388
389 chained_irq_exit(chip, desc);
390 }
391
rockchip_irq_set_type(struct irq_data * d,unsigned int type)392 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
393 {
394 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
395 struct rockchip_pin_bank *bank = gc->private;
396 u32 mask = BIT(d->hwirq);
397 u32 polarity;
398 u32 level;
399 u32 data;
400 unsigned long flags;
401 int ret = 0;
402
403 raw_spin_lock_irqsave(&bank->slock, flags);
404
405 rockchip_gpio_writel_bit(bank, d->hwirq, 0,
406 bank->gpio_regs->port_ddr);
407
408 raw_spin_unlock_irqrestore(&bank->slock, flags);
409
410 if (type & IRQ_TYPE_EDGE_BOTH)
411 irq_set_handler_locked(d, handle_edge_irq);
412 else
413 irq_set_handler_locked(d, handle_level_irq);
414
415 raw_spin_lock_irqsave(&bank->slock, flags);
416
417 level = rockchip_gpio_readl(bank, bank->gpio_regs->int_type);
418 polarity = rockchip_gpio_readl(bank, bank->gpio_regs->int_polarity);
419
420 switch (type) {
421 case IRQ_TYPE_EDGE_BOTH:
422 if (bank->gpio_type == GPIO_TYPE_V2) {
423 bank->toggle_edge_mode &= ~mask;
424 rockchip_gpio_writel_bit(bank, d->hwirq, 1,
425 bank->gpio_regs->int_bothedge);
426 goto out;
427 } else {
428 bank->toggle_edge_mode |= mask;
429 level |= mask;
430
431 /*
432 * Determine gpio state. If 1 next interrupt should be
433 * falling otherwise rising.
434 */
435 data = readl(bank->reg_base + bank->gpio_regs->ext_port);
436 if (data & mask)
437 polarity &= ~mask;
438 else
439 polarity |= mask;
440 }
441 break;
442 case IRQ_TYPE_EDGE_RISING:
443 bank->toggle_edge_mode &= ~mask;
444 level |= mask;
445 polarity |= mask;
446 break;
447 case IRQ_TYPE_EDGE_FALLING:
448 bank->toggle_edge_mode &= ~mask;
449 level |= mask;
450 polarity &= ~mask;
451 break;
452 case IRQ_TYPE_LEVEL_HIGH:
453 bank->toggle_edge_mode &= ~mask;
454 level &= ~mask;
455 polarity |= mask;
456 break;
457 case IRQ_TYPE_LEVEL_LOW:
458 bank->toggle_edge_mode &= ~mask;
459 level &= ~mask;
460 polarity &= ~mask;
461 break;
462 default:
463 ret = -EINVAL;
464 goto out;
465 }
466
467 rockchip_gpio_writel(bank, level, bank->gpio_regs->int_type);
468 rockchip_gpio_writel(bank, polarity, bank->gpio_regs->int_polarity);
469 out:
470 raw_spin_unlock_irqrestore(&bank->slock, flags);
471
472 return ret;
473 }
474
rockchip_irq_suspend(struct irq_data * d)475 static void rockchip_irq_suspend(struct irq_data *d)
476 {
477 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
478 struct rockchip_pin_bank *bank = gc->private;
479
480 bank->saved_masks = irq_reg_readl(gc, bank->gpio_regs->int_mask);
481 irq_reg_writel(gc, ~gc->wake_active, bank->gpio_regs->int_mask);
482 }
483
rockchip_irq_resume(struct irq_data * d)484 static void rockchip_irq_resume(struct irq_data *d)
485 {
486 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
487 struct rockchip_pin_bank *bank = gc->private;
488
489 irq_reg_writel(gc, bank->saved_masks, bank->gpio_regs->int_mask);
490 }
491
rockchip_irq_enable(struct irq_data * d)492 static void rockchip_irq_enable(struct irq_data *d)
493 {
494 irq_gc_mask_clr_bit(d);
495 }
496
rockchip_irq_disable(struct irq_data * d)497 static void rockchip_irq_disable(struct irq_data *d)
498 {
499 irq_gc_mask_set_bit(d);
500 }
501
rockchip_interrupts_register(struct rockchip_pin_bank * bank)502 static int rockchip_interrupts_register(struct rockchip_pin_bank *bank)
503 {
504 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
505 struct irq_chip_generic *gc;
506 int ret;
507
508 bank->domain = irq_domain_add_linear(bank->of_node, 32,
509 &irq_generic_chip_ops, NULL);
510 if (!bank->domain) {
511 dev_warn(bank->dev, "could not init irq domain for bank %s\n",
512 bank->name);
513 return -EINVAL;
514 }
515
516 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
517 "rockchip_gpio_irq",
518 handle_level_irq,
519 clr, 0, 0);
520 if (ret) {
521 dev_err(bank->dev, "could not alloc generic chips for bank %s\n",
522 bank->name);
523 irq_domain_remove(bank->domain);
524 return -EINVAL;
525 }
526
527 gc = irq_get_domain_generic_chip(bank->domain, 0);
528 if (bank->gpio_type == GPIO_TYPE_V2) {
529 gc->reg_writel = gpio_writel_v2;
530 gc->reg_readl = gpio_readl_v2;
531 }
532
533 gc->reg_base = bank->reg_base;
534 gc->private = bank;
535 gc->chip_types[0].regs.mask = bank->gpio_regs->int_mask;
536 gc->chip_types[0].regs.ack = bank->gpio_regs->port_eoi;
537 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
538 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
539 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
540 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
541 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
542 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
543 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
544 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
545 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
546 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
547
548 /*
549 * Linux assumes that all interrupts start out disabled/masked.
550 * Our driver only uses the concept of masked and always keeps
551 * things enabled, so for us that's all masked and all enabled.
552 */
553 rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_mask);
554 rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->port_eoi);
555 rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_en);
556 gc->mask_cache = 0xffffffff;
557
558 irq_set_chained_handler_and_data(bank->irq,
559 rockchip_irq_demux, bank);
560
561 return 0;
562 }
563
rockchip_gpiolib_register(struct rockchip_pin_bank * bank)564 static int rockchip_gpiolib_register(struct rockchip_pin_bank *bank)
565 {
566 struct gpio_chip *gc;
567 int ret;
568
569 bank->gpio_chip = rockchip_gpiolib_chip;
570
571 gc = &bank->gpio_chip;
572 gc->base = bank->pin_base;
573 gc->ngpio = bank->nr_pins;
574 gc->label = bank->name;
575 gc->parent = bank->dev;
576 #ifdef CONFIG_OF_GPIO
577 gc->of_node = of_node_get(bank->of_node);
578 #endif
579
580 ret = gpiochip_add_data(gc, bank);
581 if (ret) {
582 dev_err(bank->dev, "failed to add gpiochip %s, %d\n",
583 gc->label, ret);
584 return ret;
585 }
586
587 /*
588 * For DeviceTree-supported systems, the gpio core checks the
589 * pinctrl's device node for the "gpio-ranges" property.
590 * If it is present, it takes care of adding the pin ranges
591 * for the driver. In this case the driver can skip ahead.
592 *
593 * In order to remain compatible with older, existing DeviceTree
594 * files which don't set the "gpio-ranges" property or systems that
595 * utilize ACPI the driver has to call gpiochip_add_pin_range().
596 */
597 if (!of_property_read_bool(bank->of_node, "gpio-ranges")) {
598 struct device_node *pctlnp = of_get_parent(bank->of_node);
599 struct pinctrl_dev *pctldev = NULL;
600
601 if (!pctlnp)
602 return -ENODATA;
603
604 pctldev = of_pinctrl_get(pctlnp);
605 if (!pctldev)
606 return -ENODEV;
607
608 ret = gpiochip_add_pin_range(gc, dev_name(pctldev->dev), 0,
609 gc->base, gc->ngpio);
610 if (ret) {
611 dev_err(bank->dev, "Failed to add pin range\n");
612 goto fail;
613 }
614 }
615
616 ret = rockchip_interrupts_register(bank);
617 if (ret) {
618 dev_err(bank->dev, "failed to register interrupt, %d\n", ret);
619 goto fail;
620 }
621
622 return 0;
623
624 fail:
625 gpiochip_remove(&bank->gpio_chip);
626
627 return ret;
628 }
629
rockchip_get_bank_data(struct rockchip_pin_bank * bank)630 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank)
631 {
632 struct resource res;
633 int id = 0;
634
635 if (of_address_to_resource(bank->of_node, 0, &res)) {
636 dev_err(bank->dev, "cannot find IO resource for bank\n");
637 return -ENOENT;
638 }
639
640 bank->reg_base = devm_ioremap_resource(bank->dev, &res);
641 if (IS_ERR(bank->reg_base))
642 return PTR_ERR(bank->reg_base);
643
644 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
645 if (!bank->irq)
646 return -EINVAL;
647
648 bank->clk = of_clk_get(bank->of_node, 0);
649 if (IS_ERR(bank->clk))
650 return PTR_ERR(bank->clk);
651
652 clk_prepare_enable(bank->clk);
653 id = readl(bank->reg_base + gpio_regs_v2.version_id);
654
655 /* If not gpio v2, that is default to v1. */
656 if (id == GPIO_TYPE_V2 || id == GPIO_TYPE_V2_1) {
657 bank->gpio_regs = &gpio_regs_v2;
658 bank->gpio_type = GPIO_TYPE_V2;
659 bank->db_clk = of_clk_get(bank->of_node, 1);
660 if (IS_ERR(bank->db_clk)) {
661 dev_err(bank->dev, "cannot find debounce clk\n");
662 clk_disable_unprepare(bank->clk);
663 return -EINVAL;
664 }
665 } else {
666 bank->gpio_regs = &gpio_regs_v1;
667 bank->gpio_type = GPIO_TYPE_V1;
668 }
669
670 return 0;
671 }
672
673 static struct rockchip_pin_bank *
rockchip_gpio_find_bank(struct pinctrl_dev * pctldev,int id)674 rockchip_gpio_find_bank(struct pinctrl_dev *pctldev, int id)
675 {
676 struct rockchip_pinctrl *info;
677 struct rockchip_pin_bank *bank;
678 int i, found = 0;
679
680 info = pinctrl_dev_get_drvdata(pctldev);
681 bank = info->ctrl->pin_banks;
682 for (i = 0; i < info->ctrl->nr_banks; i++, bank++) {
683 if (bank->bank_num == id) {
684 found = 1;
685 break;
686 }
687 }
688
689 return found ? bank : NULL;
690 }
691
rockchip_gpio_probe(struct platform_device * pdev)692 static int rockchip_gpio_probe(struct platform_device *pdev)
693 {
694 struct device *dev = &pdev->dev;
695 struct device_node *np = dev->of_node;
696 struct device_node *pctlnp = of_get_parent(np);
697 struct pinctrl_dev *pctldev = NULL;
698 struct rockchip_pin_bank *bank = NULL;
699 struct rockchip_pin_output_deferred *cfg;
700 static int gpio;
701 int id, ret;
702
703 if (!np || !pctlnp)
704 return -ENODEV;
705
706 pctldev = of_pinctrl_get(pctlnp);
707 if (!pctldev)
708 return -EPROBE_DEFER;
709
710 id = of_alias_get_id(np, "gpio");
711 if (id < 0)
712 id = gpio++;
713
714 bank = rockchip_gpio_find_bank(pctldev, id);
715 if (!bank)
716 return -EINVAL;
717
718 bank->dev = dev;
719 bank->of_node = np;
720
721 raw_spin_lock_init(&bank->slock);
722
723 ret = rockchip_get_bank_data(bank);
724 if (ret)
725 return ret;
726
727 /*
728 * Prevent clashes with a deferred output setting
729 * being added right at this moment.
730 */
731 mutex_lock(&bank->deferred_lock);
732
733 ret = rockchip_gpiolib_register(bank);
734 if (ret) {
735 clk_disable_unprepare(bank->clk);
736 mutex_unlock(&bank->deferred_lock);
737 return ret;
738 }
739
740 while (!list_empty(&bank->deferred_output)) {
741 cfg = list_first_entry(&bank->deferred_output,
742 struct rockchip_pin_output_deferred, head);
743 list_del(&cfg->head);
744
745 ret = rockchip_gpio_direction_output(&bank->gpio_chip, cfg->pin, cfg->arg);
746 if (ret)
747 dev_warn(dev, "setting output pin %u to %u failed\n", cfg->pin, cfg->arg);
748
749 kfree(cfg);
750 }
751
752 mutex_unlock(&bank->deferred_lock);
753
754 platform_set_drvdata(pdev, bank);
755 dev_info(dev, "probed %pOF\n", np);
756
757 return 0;
758 }
759
rockchip_gpio_remove(struct platform_device * pdev)760 static int rockchip_gpio_remove(struct platform_device *pdev)
761 {
762 struct rockchip_pin_bank *bank = platform_get_drvdata(pdev);
763
764 clk_disable_unprepare(bank->clk);
765 gpiochip_remove(&bank->gpio_chip);
766
767 return 0;
768 }
769
770 static const struct of_device_id rockchip_gpio_match[] = {
771 { .compatible = "rockchip,gpio-bank", },
772 { .compatible = "rockchip,rk3188-gpio-bank0" },
773 { },
774 };
775
776 static struct platform_driver rockchip_gpio_driver = {
777 .probe = rockchip_gpio_probe,
778 .remove = rockchip_gpio_remove,
779 .driver = {
780 .name = "rockchip-gpio",
781 .of_match_table = rockchip_gpio_match,
782 },
783 };
784
rockchip_gpio_init(void)785 static int __init rockchip_gpio_init(void)
786 {
787 return platform_driver_register(&rockchip_gpio_driver);
788 }
789 postcore_initcall(rockchip_gpio_init);
790
rockchip_gpio_exit(void)791 static void __exit rockchip_gpio_exit(void)
792 {
793 platform_driver_unregister(&rockchip_gpio_driver);
794 }
795 module_exit(rockchip_gpio_exit);
796
797 MODULE_DESCRIPTION("Rockchip gpio driver");
798 MODULE_ALIAS("platform:rockchip-gpio");
799 MODULE_LICENSE("GPL v2");
800 MODULE_DEVICE_TABLE(of, rockchip_gpio_match);
801