1 /* 2 * Synopsys DesignWare Multimedia Card Interface driver 3 * (Based on NXP driver for lpc 31xx) 4 * 5 * Copyright (C) 2009 NXP Semiconductors 6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 7 * 8 * Copyright (C) 2014 Fuzhou Rockchip Electronics Co.Ltd. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 */ 15 16 #ifndef _DW_MMC_H_ 17 #define _DW_MMC_H_ 18 #include "rk_sdmmc_dbg.h" 19 20 #define DW_MMC_240A 0x240a 21 #define DW_MMC_270A 0x270a 22 23 #define SDMMC_CTRL 0x000 24 #define SDMMC_PWREN 0x004 25 #define SDMMC_CLKDIV 0x008 26 #define SDMMC_CLKSRC 0x00c 27 #define SDMMC_CLKENA 0x010 28 #define SDMMC_TMOUT 0x014 29 #define SDMMC_CTYPE 0x018 30 #define SDMMC_BLKSIZ 0x01c 31 #define SDMMC_BYTCNT 0x020 32 #define SDMMC_INTMASK 0x024 33 #define SDMMC_CMDARG 0x028 34 #define SDMMC_CMD 0x02c 35 #define SDMMC_RESP0 0x030 36 #define SDMMC_RESP1 0x034 37 #define SDMMC_RESP2 0x038 38 #define SDMMC_RESP3 0x03c 39 #define SDMMC_MINTSTS 0x040 40 #define SDMMC_RINTSTS 0x044 41 #define SDMMC_STATUS 0x048 42 #define SDMMC_FIFOTH 0x04c 43 #define SDMMC_CDETECT 0x050 44 #define SDMMC_WRTPRT 0x054 45 #define SDMMC_GPIO 0x058 46 #define SDMMC_TCBCNT 0x05c 47 #define SDMMC_TBBCNT 0x060 48 #define SDMMC_DEBNCE 0x064 49 #define SDMMC_USRID 0x068 50 #define SDMMC_VERID 0x06c 51 #define SDMMC_HCON 0x070 52 #define SDMMC_UHS_REG 0x074 53 #define SDMMC_RST_N 0x078 54 #define SDMMC_BMOD 0x080 55 #define SDMMC_PLDMND 0x084 56 #define SDMMC_DBADDR 0x088 57 #define SDMMC_IDSTS 0x08c 58 #define SDMMC_IDINTEN 0x090 59 #define SDMMC_DSCADDR 0x094 60 #define SDMMC_BUFADDR 0x098 61 #define SDMMC_CDTHRCTL 0x100 62 #define SDMMC_DATA(x) (x) 63 64 65 static const u8 tuning_blk_pattern_4bit[] = { 66 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc, 67 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef, 68 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb, 69 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef, 70 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c, 71 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee, 72 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff, 73 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde, 74 }; 75 76 static const u8 tuning_blk_pattern_8bit[] = { 77 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00, 78 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc, 79 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff, 80 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff, 81 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd, 82 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb, 83 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff, 84 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff, 85 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 86 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 87 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 88 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 89 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 90 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 91 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 92 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 93 }; 94 95 /* 96 * Data offset is difference according to Version 97 * Lower than 2.40a : data register offest is 0x100 98 */ 99 #define DATA_OFFSET 0x100 100 #define DATA_240A_OFFSET 0x200 101 102 /* shift bit field */ 103 #define _SBF(f, v) ((v) << (f)) 104 105 106 struct sdmmc_reg { 107 u32 addr; 108 char *name; 109 }; 110 111 static const struct sdmmc_reg dw_mci_regs[] = { 112 { 0x0000, "CTRL" }, 113 { 0x0004, "PWREN" }, 114 { 0x0008, "CLKDIV" }, 115 { 0x000C, "CLKSRC" }, 116 { 0x0010, "CLKENA" }, 117 { 0x0014, "TMOUT" }, 118 { 0x0018, "CTYPE" }, 119 { 0x001C, "BLKSIZ" }, 120 { 0x0020, "BYTCNT" }, 121 { 0x0024, "INTMASK" }, 122 { 0x0028, "CMDARG" }, 123 { 0x002C, "CMD" }, 124 { 0x0030, "RESP0" }, 125 { 0x0034, "RESP1" }, 126 { 0x0038, "RESP2" }, 127 { 0x003C, "RESP3" }, 128 { 0x0040, "MINSTS" }, 129 { 0x0044, "RINTSTS" }, 130 { 0x0048, "STATUS" }, 131 { 0x004C, "FIFOTH" }, 132 { 0x0050, "CDETECT" }, 133 { 0x0054, "WRTPRT" }, 134 { 0x0058, "GPIO" }, 135 { 0x005C, "TCBCNT" }, 136 { 0x0060, "TBBCNT" }, 137 { 0x0064, "DEBNCE" }, 138 { 0x0068, "USRID" }, 139 { 0x006C, "VERID" }, 140 { 0x0070, "HCON" }, 141 { 0x0074, "UHS_REG" }, 142 { 0x0078, "RST_n" }, 143 { 0x0080, "BMOD" }, 144 { 0x0084, "PLDMND" }, 145 { 0x0088, "DBADDR" }, 146 { 0x008C, "IDSTS" }, 147 { 0x0090, "IDINTEN" }, 148 { 0x0094, "DSCADDR" }, 149 { 0x0098, "BUFADDR" }, 150 { 0x0100, "CARDTHRCTL" }, 151 { 0x0104, "BackEndPwr" }, 152 { 0, 0 } 153 }; 154 155 156 /* Control register defines */ 157 #define SDMMC_CTRL_USE_IDMAC BIT(25) 158 #define SDMMC_CTRL_CEATA_INT_EN BIT(11) 159 #define SDMMC_CTRL_SEND_AS_CCSD BIT(10) 160 #define SDMMC_CTRL_SEND_CCSD BIT(9) 161 #define SDMMC_CTRL_ABRT_READ_DATA BIT(8) 162 #define SDMMC_CTRL_SEND_IRQ_RESP BIT(7) 163 #define SDMMC_CTRL_READ_WAIT BIT(6) 164 #define SDMMC_CTRL_DMA_ENABLE BIT(5) 165 #define SDMMC_CTRL_INT_ENABLE BIT(4) 166 #define SDMMC_CTRL_DMA_RESET BIT(2) 167 #define SDMMC_CTRL_FIFO_RESET BIT(1) 168 #define SDMMC_CTRL_RESET BIT(0) 169 /* Clock Enable register defines */ 170 #define SDMMC_CLKEN_LOW_PWR BIT(16) 171 #define SDMMC_CLKEN_ENABLE BIT(0) 172 /* time-out register defines */ 173 #define SDMMC_TMOUT_DATA(n) _SBF(8, (n)) 174 #define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00 175 #define SDMMC_TMOUT_RESP(n) ((n) & 0xFF) 176 #define SDMMC_TMOUT_RESP_MSK 0xFF 177 /* card-type register defines */ 178 #define SDMMC_CTYPE_8BIT BIT(16) 179 #define SDMMC_CTYPE_4BIT BIT(0) 180 #define SDMMC_CTYPE_1BIT 0 181 /* Interrupt status & mask register defines */ 182 #define SDMMC_INT_SDIO(n) BIT(16 + (n)) 183 #define SDMMC_INT_EBE BIT(15) 184 #define SDMMC_INT_ACD BIT(14) 185 #define SDMMC_INT_SBE BIT(13) 186 #define SDMMC_INT_HLE BIT(12) 187 #define SDMMC_INT_FRUN BIT(11) 188 #define SDMMC_INT_HTO BIT(10) 189 #define SDMMC_INT_VSI SDMMC_INT_HTO 190 #define SDMMC_INT_DRTO BIT(9) 191 #define SDMMC_INT_RTO BIT(8) 192 #define SDMMC_INT_DCRC BIT(7) 193 #define SDMMC_INT_RCRC BIT(6) 194 #define SDMMC_INT_RXDR BIT(5) 195 #define SDMMC_INT_TXDR BIT(4) 196 #define SDMMC_INT_DATA_OVER BIT(3) 197 #define SDMMC_INT_CMD_DONE BIT(2) 198 #define SDMMC_INT_RESP_ERR BIT(1) 199 #define SDMMC_INT_CD BIT(0) 200 #define SDMMC_INT_ERROR 0xbfc2 201 /* Command register defines */ 202 #define SDMMC_CMD_START BIT(31) 203 #define SDMMC_CMD_USE_HOLD_REG BIT(29) 204 #define SDMMC_CMD_VOLT_SWITCH BIT(28) 205 #define SDMMC_CMD_BOOT_MODE BIT(27) 206 #define SDMMC_CMD_DISABLE_BOOT BIT(26) 207 #define SDMMC_CMD_EXPECT_BOOT_ACK BIT(25) 208 #define SDMMC_CMD_ENABLE_BOOT BIT(24) 209 #define SDMMC_CMD_CCS_EXP BIT(23) 210 #define SDMMC_CMD_CEATA_RD BIT(22) 211 #define SDMMC_CMD_UPD_CLK BIT(21) 212 #define SDMMC_CMD_INIT BIT(15) 213 #define SDMMC_CMD_STOP BIT(14) 214 #define SDMMC_CMD_PRV_DAT_WAIT BIT(13) 215 #define SDMMC_CMD_SEND_STOP BIT(12) 216 #define SDMMC_CMD_STRM_MODE BIT(11) 217 #define SDMMC_CMD_DAT_WR BIT(10) 218 #define SDMMC_CMD_DAT_EXP BIT(9) 219 #define SDMMC_CMD_RESP_CRC BIT(8) 220 #define SDMMC_CMD_RESP_LONG BIT(7) 221 #define SDMMC_CMD_RESP_EXP BIT(6) 222 #define SDMMC_CMD_INDX(n) ((n) & 0x1F) 223 /* Status register defines */ 224 #define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF) 225 #define SDMMC_STAUTS_MC_BUSY BIT(10) 226 #define SDMMC_STAUTS_DATA_BUSY BIT(9) 227 #define SDMMC_CMD_FSM_MASK (0x0F << 4) 228 #define SDMMC_CMD_FSM_IDLE (0x00) 229 #define SDMMC_STAUTS_FIFO_FULL BIT(3) 230 #define SDMMC_STAUTS_FIFO_EMPTY BIT(2) 231 232 /* Control SDMMC_UHS_REG defines (base+ 0x74)*/ 233 #define SDMMC_UHS_DDR_MODE BIT(16) 234 #define SDMMC_UHS_VOLT_REG_18 BIT(0) 235 236 /* FIFOTH register defines */ 237 #define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \ 238 ((r) & 0xFFF) << 16 | \ 239 ((t) & 0xFFF)) 240 /* Internal DMAC interrupt defines */ 241 #define SDMMC_IDMAC_INT_AI BIT(9) 242 #define SDMMC_IDMAC_INT_NI BIT(8) 243 #define SDMMC_IDMAC_INT_CES BIT(5) 244 #define SDMMC_IDMAC_INT_DU BIT(4) 245 #define SDMMC_IDMAC_INT_FBE BIT(2) 246 #define SDMMC_IDMAC_INT_RI BIT(1) 247 #define SDMMC_IDMAC_INT_TI BIT(0) 248 /* Internal DMAC bus mode bits */ 249 #define SDMMC_IDMAC_ENABLE BIT(7) 250 #define SDMMC_IDMAC_FB BIT(1) 251 #define SDMMC_IDMAC_SWRESET BIT(0) 252 /* Version ID register define */ 253 #define SDMMC_GET_VERID(x) ((x) & 0xFFFF) 254 /* Card read threshold */ 255 #define SDMMC_SET_RD_THLD(v, x) (((v) & 0xFFF) << 16 | (x)) 256 257 /* Register access macros */ 258 #define mci_readl(dev, reg) \ 259 __raw_readl((dev)->regs + SDMMC_##reg) 260 #define mci_writel(dev, reg, value) \ 261 __raw_writel((value), (dev)->regs + SDMMC_##reg) 262 #define mci_readreg(dev, addr) \ 263 __raw_readl((dev)->regs + addr) 264 #define mci_writereg(dev, addr, value) \ 265 __raw_writel((value), (dev)->regs + addr) 266 267 268 /* 16-bit FIFO access macros */ 269 #define mci_readw(dev, reg) \ 270 __raw_readw((dev)->regs + SDMMC_##reg) 271 #define mci_writew(dev, reg, value) \ 272 __raw_writew((value), (dev)->regs + SDMMC_##reg) 273 274 /* 64-bit FIFO access macros */ 275 #ifdef readq 276 #define mci_readq(dev, reg) \ 277 __raw_readq((dev)->regs + SDMMC_##reg) 278 #define mci_writeq(dev, reg, value) \ 279 __raw_writeq((value), (dev)->regs + SDMMC_##reg) 280 #else 281 /* 282 * Dummy readq implementation for architectures that don't define it. 283 * 284 * We would assume that none of these architectures would configure 285 * the IP block with a 64bit FIFO width, so this code will never be 286 * executed on those machines. Defining these macros here keeps the 287 * rest of the code free from ifdefs. 288 */ 289 #define mci_readq(dev, reg) \ 290 (*(u64 __force *)((dev)->regs + SDMMC_##reg)) 291 #define mci_writeq(dev, reg, value) \ 292 (*(u64 __force *)((dev)->regs + SDMMC_##reg) = (value)) 293 #endif 294 #ifdef CONFIG_PM 295 extern int dw_mci_suspend(struct dw_mci *host); 296 extern int dw_mci_resume(struct dw_mci *host); 297 #endif 298 static const struct dw_mci_rst_ops dw_mci_pdrst_ops; 299 300 /** 301 * struct dw_mci_slot - MMC slot state 302 * @mmc: The mmc_host representing this slot. 303 * @host: The MMC controller this slot is using. 304 * @quirks: Slot-level quirks (DW_MCI_SLOT_QUIRK_XXX) 305 * @wp_gpio: If gpio_is_valid() we'll use this to read write protect. 306 * @ctype: Card type for this slot. 307 * @mrq: mmc_request currently being processed or waiting to be 308 * processed, or NULL when the slot is idle. 309 * @queue_node: List node for placing this node in the @queue list of 310 * &struct dw_mci. 311 * @clock: Clock rate configured by set_ios(). Protected by host->lock. 312 * @__clk_old: The last updated clock with reflecting clock divider. 313 * Keeping track of this helps us to avoid spamming the console 314 * with CONFIG_MMC_CLKGATE. 315 * @flags: Random state bits associated with the slot. 316 * @id: Number of this slot. 317 * @last_detect_state: Most recently observed card detect state. 318 */ 319 struct dw_mci_slot { 320 struct mmc_host *mmc; 321 struct dw_mci *host; 322 int quirks; 323 int wp_gpio; 324 int cd_gpio; 325 int pwr_en_gpio; 326 u32 ctype; 327 u32 pre_ctype; 328 329 struct mmc_request *mrq; 330 struct list_head queue_node; 331 332 unsigned int clock; 333 unsigned int __clk_old; 334 335 unsigned long flags; 336 #define DW_MMC_CARD_PRESENT 0 337 #define DW_MMC_CARD_NEED_INIT 1 338 int id; 339 int last_detect_state; 340 }; 341 342 struct dw_mci_tuning_data { 343 const u8 *blk_pattern; 344 unsigned int blksz; 345 }; 346 347 /** 348 * dw_mci driver data - dw-mshc implementation specific driver data. 349 * @caps: mmc subsystem specified capabilities of the controller(s). 350 * @hold_reg_flag: Fixed the value of HOLG_REG 351 * @init: early implementation specific initialization. 352 * @setup_clock: implementation specific clock configuration. 353 * @prepare_command: handle CMD register extensions. 354 * @set_ios: handle bus specific extensions. 355 * @parse_dt: parse implementation specific device tree properties. 356 * 357 * Provide controller implementation specific extensions. The usage of this 358 * data structure is fully optional and usage of each member in this structure 359 * is optional as well. 360 */ 361 362 struct dw_mci_drv_data { 363 unsigned long *caps; 364 unsigned int *hold_reg_flag; 365 366 int (*init)(struct dw_mci *host); 367 int (*setup_clock)(struct dw_mci *host); 368 void (*prepare_command)(struct dw_mci *host, u32 *cmdr); 369 void (*set_ios)(struct dw_mci *host, struct mmc_ios *ios); 370 int (*parse_dt)(struct dw_mci *host); 371 int (*execute_tuning)(struct dw_mci_slot *slot, 372 u32 opcode, 373 struct dw_mci_tuning_data 374 *tuning_data); 375 }; 376 377 /* Variations in Rockchip specific dw-mshc controller */ 378 enum dw_mci_rockchip_type { 379 DW_MCI_TYPE_RK3188, 380 DW_MCI_TYPE_RK3288, 381 DW_MCI_TYPE_RK3036, 382 DW_MCI_TYPE_RK312X, 383 DW_MCI_TYPE_RK3368, 384 DW_MCI_TYPE_RK3228, 385 }; 386 387 #endif /* _DW_MMC_H_ */ 388