1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2018 Rockchip Electronics Co., Ltd. 4 */ 5 #ifndef __SOC_ROCKCHIP_PCIE_DMA_TRX_H 6 #define __SOC_ROCKCHIP_PCIE_DMA_TRX_H 7 8 #include <linux/debugfs.h> 9 10 #define PCIE_DMA_TABLE_NUM 32 11 12 #define PCIE_DMA_TRX_TYPE_NUM 3 13 14 #define PCIE_DMA_CHN0 0x0 15 #define PCIE_DMA_CHN1 0x1 16 #define PCIE_DMA_DEFAULT_CHN PCIE_DMA_CHN0 17 18 #define PCIE_DMA_DATA_SND_TABLE_OFFSET 0x0 19 #define PCIE_DMA_DATA_RCV_ACK_TABLE_OFFSET 0x8 20 #define PCIE_DMA_DATA_FREE_ACK_TABLE_OFFSET 0x10 21 #define PCIE_DMA_DATA_READ_REMOTE_TABLE_OFFSET 0x18 22 23 enum dma_dir { 24 DMA_FROM_BUS, 25 DMA_TO_BUS, 26 }; 27 28 /** 29 * The Channel Control Register for read and write. 30 */ 31 union chan_ctrl_lo { 32 struct { 33 u32 cb :1; // 0 34 u32 tcb :1; // 1 35 u32 llp :1; // 2 36 u32 lie :1; // 3 37 u32 rie :1; // 4 38 u32 cs :2; // 5:6 39 u32 rsvd1 :1; // 7 40 u32 ccs :1; // 8 41 u32 llen :1; // 9 42 u32 b_64s :1; // 10 43 u32 b_64d :1; // 11 44 u32 pf :5; // 12:16 45 u32 rsvd2 :7; // 17:23 46 u32 sn :1; // 24 47 u32 ro :1; // 25 48 u32 td :1; // 26 49 u32 tc :3; // 27:29 50 u32 at :2; // 30:31 51 }; 52 u32 asdword; 53 }; 54 55 /** 56 * The Channel Control Register high part for read and write. 57 */ 58 union chan_ctrl_hi { 59 struct { 60 u32 vfenb :1; // 0 61 u32 vfunc :8; // 1-8 62 u32 rsvd0 :23; // 9-31 63 }; 64 u32 asdword; 65 }; 66 67 /** 68 * The Channel Weight Register. 69 */ 70 union weight { 71 struct { 72 u32 weight0 :5; // 0:4 73 u32 weight1 :5; // 5:9 74 u32 weight2 :5; // 10:14 75 u32 weight3 :5; // 15:19 76 u32 rsvd :12; // 20:31 77 }; 78 u32 asdword; 79 }; 80 81 /** 82 * The Doorbell Register for read and write. 83 */ 84 union db { 85 struct { 86 u32 chnl :3; // 0 87 u32 reserved0 :28; // 3:30 88 u32 stop :1; // 31 89 }; 90 u32 asdword; 91 }; 92 93 /** 94 * The Context Registers for read and write. 95 */ 96 struct ctx_regs { 97 union chan_ctrl_lo ctrllo; 98 union chan_ctrl_hi ctrlhi; 99 u32 xfersize; 100 u32 sarptrlo; 101 u32 sarptrhi; 102 u32 darptrlo; 103 u32 darptrhi; 104 }; 105 106 /** 107 * The Enable Register for read and write. 108 */ 109 union enb { 110 struct { 111 u32 enb :1; // 0 112 u32 reserved0 :31; // 1:31 113 }; 114 u32 asdword; 115 }; 116 117 /** 118 * The Interrupt Status Register for read and write. 119 */ 120 union int_status { 121 struct { 122 u32 donesta :8; 123 u32 rsvd0 :8; 124 u32 abortsta :8; 125 u32 rsvd1 :8; 126 }; 127 u32 asdword; 128 }; 129 130 /** 131 * The Interrupt Clear Register for read and write. 132 */ 133 union int_clear { 134 struct { 135 u32 doneclr :8; 136 u32 rsvd0 :8; 137 u32 abortclr :8; 138 u32 rsvd1 :8; 139 }; 140 u32 asdword; 141 }; 142 143 struct dma_table { 144 u32 *descs; 145 int chn; 146 phys_addr_t phys_descs; 147 u32 dir; 148 u32 type; 149 struct list_head tbl_node; 150 union enb enb; 151 struct ctx_regs ctx_reg; 152 union weight weilo; 153 union weight weihi; 154 union db start; 155 phys_addr_t local; 156 phys_addr_t bus; 157 size_t buf_size; 158 }; 159 160 struct dma_trx_obj { 161 struct device *dev; 162 int loop_count; 163 int loop_count_threshold; 164 void *local_mem_base; 165 phys_addr_t local_mem_start; 166 size_t local_mem_size; 167 phys_addr_t remote_mem_start; 168 void *region_base; 169 phys_addr_t region_start; 170 size_t region_size; 171 int dma_free; 172 unsigned long local_write_available; 173 unsigned long local_read_available; 174 unsigned long remote_write_available; 175 spinlock_t tbl_list_lock; /* lock dma table */ 176 struct list_head tbl_list; 177 struct work_struct dma_trx_work; 178 wait_queue_head_t event_queue; 179 struct workqueue_struct *dma_trx_wq; 180 struct dma_table *table[PCIE_DMA_TABLE_NUM]; 181 struct dma_table *cur; 182 struct hrtimer scan_timer; 183 int busno; 184 void *priv; 185 struct completion done; 186 int ref_count; 187 struct mutex count_mutex; 188 unsigned long irq_num; 189 struct dentry *pcie_root; 190 struct pcie_misc_dev *pcie_dev; 191 void (*start_dma_func)(struct dma_trx_obj *obj); 192 void (*config_dma_func)(struct dma_table *table); 193 ktime_t begin; 194 ktime_t end; 195 u64 cache_time_total; 196 u64 cache_time_avarage; 197 u32 buffer_size; 198 u32 rd_buf_size; 199 u32 wr_buf_size; 200 u32 ack_base; 201 u32 set_data_check_pos; 202 u32 set_local_idx_pos; 203 u32 set_buf_size_pos; 204 u32 set_chk_sum_pos; 205 u32 version; 206 int addr_reverse; 207 }; 208 209 #if IS_ENABLED(CONFIG_ROCKCHIP_PCIE_DMA_OBJ) 210 struct dma_trx_obj *rk_pcie_dma_obj_probe(struct device *dev); 211 void rk_pcie_dma_obj_remove(struct dma_trx_obj *obj); 212 #else rk_pcie_dma_obj_probe(struct device * dev)213static inline struct dma_trx_obj *rk_pcie_dma_obj_probe(struct device *dev) 214 { 215 return NULL; 216 } 217 rk_pcie_dma_obj_remove(struct dma_trx_obj * obj)218static inline void rk_pcie_dma_obj_remove(struct dma_trx_obj *obj) 219 { 220 } 221 #endif 222 223 #endif 224