1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2020 Rockchip Electronics Co. Ltd. 4 * 5 * Author: Wyon Bi <bivvy.bi@rock-chips.com> 6 */ 7 8 #ifndef _RK628_H 9 #define _RK628_H 10 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/regmap.h> 14 #include <linux/irq.h> 15 #include <linux/irqdomain.h> 16 17 #include <drm/drm_crtc_helper.h> 18 19 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) 20 #define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK((h), (l)) << 16)) 21 22 #define GRF_SYSTEM_CON0 0x0000 23 #define SW_VSYNC_POL_MASK BIT(26) 24 #define SW_VSYNC_POL(x) UPDATE(x, 26, 26) 25 #define SW_HSYNC_POL_MASK BIT(25) 26 #define SW_HSYNC_POL(x) UPDATE(x, 25, 25) 27 #define SW_ADAPTER_I2CSLADR_MASK GENMASK(24, 22) 28 #define SW_ADAPTER_I2CSLADR(x) UPDATE(x, 24, 22) 29 #define SW_EDID_MODE_MASK BIT(21) 30 #define SW_EDID_MODE(x) UPDATE(x, 21, 21) 31 #define SW_I2S_DATA_OEN_MASK BIT(10) 32 #define SW_I2S_DATA_OEN(x) UPDATE(x, 10, 10) 33 #define SW_BT_DATA_OEN_MASK BIT(9) 34 #define SW_BT_DATA_OEN BIT(9) 35 #define SW_EFUSE_HDCP_EN_MASK BIT(8) 36 #define SW_EFUSE_HDCP_EN(x) UPDATE(x, 8, 8) 37 #define SW_OUTPUT_MODE_MASK GENMASK(7, 3) 38 #define SW_OUTPUT_MODE(x) UPDATE(x, 7, 3) 39 #define SW_INPUT_MODE_MASK GENMASK(2, 0) 40 #define SW_INPUT_MODE(x) UPDATE(x, 2, 0) 41 #define GRF_SYSTEM_CON1 0x0004 42 #define GRF_SYSTEM_CON2 0x0008 43 #define GRF_SYSTEM_CON3 0x000c 44 #define GRF_GPIO_RX_CEC_SEL_MASK BIT(7) 45 #define GRF_GPIO_RX_CEC_SEL(x) UPDATE(x, 7, 7) 46 #define GRF_GPIO_RXDDC_SDA_SEL_MASK BIT(6) 47 #define GRF_GPIO_RXDDC_SDA_SEL(x) UPDATE(x, 6, 6) 48 #define GRF_GPIO_RXDDC_SCL_SEL_MASK BIT(5) 49 #define GRF_GPIO_RXDDC_SCL_SEL(x) UPDATE(x, 5, 5) 50 #define GRF_SCALER_CON0 0x0010 51 #define SCL_VER_DOWN_MODE(x) HIWORD_UPDATE(x, 8, 8) 52 #define SCL_HOR_DOWN_MODE(x) HIWORD_UPDATE(x, 7, 7) 53 #define SCL_BIC_COE_SEL(x) HIWORD_UPDATE(x, 6, 5) 54 #define SCL_VER_MODE(x) HIWORD_UPDATE(x, 4, 3) 55 #define SCL_HOR_MODE(x) HIWORD_UPDATE(x, 2, 1) 56 #define SCL_EN(x) HIWORD_UPDATE(x, 0, 0) 57 #define GRF_SCALER_CON1 0x0014 58 #define SCL_V_FACTOR(x) UPDATE(x, 31, 16) 59 #define SCL_H_FACTOR(x) UPDATE(x, 15, 0) 60 #define GRF_SCALER_CON2 0x0018 61 #define DSP_FRAME_VST(x) UPDATE(x, 28, 16) 62 #define DSP_FRAME_HST(x) UPDATE(x, 12, 0) 63 #define GRF_SCALER_CON3 0x001c 64 #define DSP_HS_END(x) UPDATE(x, 23, 16) 65 #define DSP_HTOTAL(x) UPDATE(x, 12, 0) 66 #define GRF_SCALER_CON4 0x0020 67 #define DSP_HACT_ST(x) UPDATE(x, 28, 16) 68 #define DSP_HACT_END(x) UPDATE(x, 12, 0) 69 #define GRF_SCALER_CON5 0x0024 70 #define DSP_VS_END(x) UPDATE(x, 23, 16) 71 #define DSP_VTOTAL(x) UPDATE(x, 12, 0) 72 #define GRF_SCALER_CON6 0x0028 73 #define DSP_VACT_ST(x) UPDATE(x, 28, 16) 74 #define DSP_VACT_END(x) UPDATE(x, 12, 0) 75 #define GRF_SCALER_CON7 0x002c 76 #define DSP_HBOR_ST(x) UPDATE(x, 28, 16) 77 #define DSP_HBOR_END(x) UPDATE(x, 12, 0) 78 #define GRF_SCALER_CON8 0x0030 79 #define DSP_VBOR_ST(x) UPDATE(x, 28, 16) 80 #define DSP_VBOR_END(x) UPDATE(x, 12, 0) 81 #define GRF_POST_PROC_CON 0x0034 82 #define SW_DCLK_OUT_INV_EN BIT(9) 83 #define SW_DCLK_IN_INV_EN BIT(8) 84 #define SW_TXPHY_REFCLK_SEL_MASK GENMASK(6, 5) 85 #define SW_TXPHY_REFCLK_SEL(x) UPDATE(x, 6, 5) 86 #define SW_HDMITX_VCLK_PLLREF_SEL_MASK BIT(4) 87 #define SW_HDMITX_VCLK_PLLREF_SEL(x) UPDATE(x, 4, 4) 88 #define SW_HDMITX_DCLK_INV_EN BIT(3) 89 #define SW_SPLIT_MODE(x) UPDATE(x, 1, 1) 90 #define SW_SPLIT_EN BIT(0) 91 #define GRF_CSC_CTRL_CON 0x0038 92 #define SW_YUV2VYU_SWP(x) HIWORD_UPDATE(x, 8, 8) 93 #define SW_R2Y_EN(x) HIWORD_UPDATE(x, 4, 4) 94 #define SW_Y2R_EN(x) HIWORD_UPDATE(x, 0, 0) 95 #define GRF_LVDS_TX_CON 0x003c 96 #define SW_LVDS_CON_DUAL_SEL(x) HIWORD_UPDATE(x, 12, 12) 97 #define SW_LVDS_CON_DEN_POLARITY(x) HIWORD_UPDATE(x, 11, 11) 98 #define SW_LVDS_CON_HS_POLARITY(x) HIWORD_UPDATE(x, 10, 10) 99 #define SW_LVDS_CON_CLKINV(x) HIWORD_UPDATE(x, 9, 9) 100 #define SW_LVDS_STARTPHASE(x) HIWORD_UPDATE(x, 8, 8) 101 #define SW_LVDS_CON_STARTSEL(x) HIWORD_UPDATE(x, 7, 7) 102 #define SW_LVDS_CON_CHASEL(x) HIWORD_UPDATE(x, 6, 6) 103 #define SW_LVDS_TIE_VSYNC_VALUE(x) HIWORD_UPDATE(x, 5, 5) 104 #define SW_LVDS_TIE_HSYNC_VALUE(x) HIWORD_UPDATE(x, 4, 4) 105 #define SW_LVDS_TIE_DEN_ONLY(x) HIWORD_UPDATE(x, 3, 3) 106 #define SW_LVDS_CON_MSBSEL(x) HIWORD_UPDATE(x, 2, 2) 107 #define SW_LVDS_CON_SELECT(x) HIWORD_UPDATE(x, 1, 0) 108 #define GRF_RGB_DEC_CON0 0x0040 109 #define SW_HRES_MASK GENMASK(28, 16) 110 #define SW_HRES(x) UPDATE(x, 28, 16) 111 #define DUAL_DATA_SWAP BIT(6) 112 #define DEC_DUALEDGE_EN BIT(5) 113 #define SW_PROGRESS_EN BIT(4) 114 #define SW_YC_SWAP BIT(3) 115 #define SW_CAP_EN_ASYNC BIT(1) 116 #define SW_CAP_EN_PSYNC BIT(0) 117 #define GRF_RGB_DEC_CON1 0x0044 118 #define SW_SET_X_MASK GENMASK(28, 16) 119 #define SW_SET_X(x) HIWORD_UPDATE(x, 28, 16) 120 #define SW_SET_Y_MASK GENMASK(28, 16) 121 #define SW_SET_Y(x) HIWORD_UPDATE(x, 28, 16) 122 #define GRF_RGB_DEC_CON2 0x0048 123 #define GRF_RGB_ENC_CON 0x004c 124 #define BT1120_UV_SWAP(x) HIWORD_UPDATE(x, 5, 5) 125 #define ENC_DUALEDGE_EN(x) HIWORD_UPDATE(x, 3, 3) 126 #define GRF_MIPI_LANE_DELAY_CON0 0x0050 127 #define GRF_MIPI_LANE_DELAY_CON1 0x0054 128 #define GRF_BT1120_DCLK_DELAY_CON0 0x0058 129 #define GRF_BT1120_DCLK_DELAY_CON1 0x005c 130 #define GRF_MIPI_TX0_CON 0x0060 131 #define DPIUPDATECFG BIT(26) 132 #define DPICOLORM BIT(25) 133 #define DPISHUTDN BIT(24) 134 #define CSI_PHYRSTZ BIT(21) 135 #define CSI_PHYSHUTDOWNZ BIT(20) 136 #define FORCETXSTOPMODE_MASK GENMASK(19, 16) 137 #define FORCETXSTOPMODE(x) UPDATE(x, 19, 16) 138 #define FORCERXMODE_MASK GENMASK(15, 12) 139 #define FORCERXMODE(x) UPDATE(x, 15, 12) 140 #define PHY_TESTCLR BIT(10) 141 #define PHY_TESTCLK BIT(9) 142 #define PHY_TESTEN BIT(8) 143 #define PHY_TESTDIN_MASK GENMASK(7, 0) 144 #define PHY_TESTDIN(x) UPDATE(x, 7, 0) 145 #define GRF_DPHY0_STATUS 0x0064 146 #define DPHY_PHYLOCK BIT(24) 147 #define PHY_TESTDOUT_SHIFT 8 148 #define GRF_MIPI_TX1_CON 0x0068 149 #define GRF_DPHY1_STATUS 0x006c 150 #define GRF_GPIO0AB_SEL_CON 0x0070 151 #define GRF_GPIO1AB_SEL_CON 0x0074 152 #define GRF_GPIO2AB_SEL_CON 0x0078 153 #define GRF_GPIO2C_SEL_CON 0x007c 154 #define GRF_GPIO3AB_SEL_CON 0x0080 155 #define GRF_GPIO2A_SMT 0x0090 156 #define GRF_GPIO2B_SMT 0x0094 157 #define GRF_GPIO2C_SMT 0x0098 158 #define GRF_GPIO3AB_SMT 0x009c 159 #define GRF_GPIO0A_P_CON 0x00a0 160 #define GRF_GPIO1A_P_CON 0x00a4 161 #define GRF_GPIO2A_P_CON 0x00a8 162 #define GRF_GPIO2B_P_CON 0x00ac 163 #define GRF_GPIO2C_P_CON 0x00b0 164 #define GRF_GPIO3A_P_CON 0x00b4 165 #define GRF_GPIO3B_P_CON 0x00b8 166 #define GRF_GPIO0B_D_CON 0x00c0 167 #define GRF_GPIO1B_D_CON 0x00c4 168 #define GRF_GPIO2A_D0_CON 0x00c8 169 #define GRF_GPIO2A_D1_CON 0x00cc 170 #define GRF_GPIO2B_D0_CON 0x00d0 171 #define GRF_GPIO2B_D1_CON 0x00d4 172 #define GRF_GPIO2C_D0_CON 0x00d8 173 #define GRF_GPIO2C_D1_CON 0x00dc 174 #define GRF_GPIO3A_D0_CON 0x00e0 175 #define GRF_GPIO3A_D1_CON 0x00e4 176 #define GRF_GPIO3B_D_CON 0x00e8 177 #define GRF_GPIO_SR_CON 0x00ec 178 #define GRF_INTR0_EN 0x0100 179 #define GRF_INTR0_CLR_EN 0x0104 180 #define GRF_INTR0_STATUS 0x0108 181 #define GRF_INTR0_RAW_STATUS 0x010c 182 #define GRF_INTR1_EN 0x0110 183 #define GRF_INTR1_CLR_EN 0x0114 184 #define GRF_INTR1_STATUS 0x0118 185 #define GRF_INTR1_RAW_STATUS 0x011c 186 #define GRF_SYSTEM_STATUS0 0x0120 187 /* 0: i2c mode and mcu mode; 1: i2c mode only */ 188 #define I2C_ONLY_FLAG BIT(6) 189 #define GRF_SYSTEM_STATUS3 0x012c 190 #define GRF_SYSTEM_STATUS4 0x0130 191 #define GRF_OS_REG0 0x0140 192 #define GRF_OS_REG1 0x0144 193 #define GRF_OS_REG2 0x0148 194 #define GRF_OS_REG3 0x014c 195 #define GRF_SOC_VERSION 0x0150 196 #define GRF_MAX_REGISTER GRF_SOC_VERSION 197 198 enum { 199 COMBTXPHY_MODULEA_EN = BIT(0), 200 COMBTXPHY_MODULEB_EN = BIT(1), 201 }; 202 203 enum { 204 OUTPUT_MODE_GVI = 1, 205 OUTPUT_MODE_LVDS, 206 OUTPUT_MODE_HDMI, 207 OUTPUT_MODE_CSI, 208 OUTPUT_MODE_DSI, 209 OUTPUT_MODE_BT1120 = 8, 210 OUTPUT_MODE_RGB = 16, 211 OUTPUT_MODE_YUV = 24, 212 }; 213 214 enum { 215 INPUT_MODE_HDMI, 216 INPUT_MODE_BT1120 = 2, 217 INPUT_MODE_RGB, 218 INPUT_MODE_YUV, 219 }; 220 221 struct rk628_irq_chip_data { 222 const char *name; 223 unsigned int status_base; 224 unsigned int mask_base; 225 unsigned int ack_base; 226 int num_regs; 227 const struct regmap_irq *irqs; 228 int num_irqs; 229 struct mutex lock; 230 struct irq_chip irq_chip; 231 struct regmap *map; 232 struct irq_domain *domain; 233 int irq; 234 unsigned int *status_buf; 235 unsigned int *mask_buf; 236 unsigned int *mask_buf_def; 237 unsigned int irq_reg_stride; 238 unsigned int reg_stride; 239 }; 240 241 struct rk628 { 242 struct device *dev; 243 struct i2c_client *client; 244 struct regmap *grf; 245 struct gpio_desc *reset_gpio; 246 struct gpio_desc *enable_gpio; 247 struct rk628_irq_chip_data *irq_data; 248 struct drm_display_mode src_mode; 249 struct drm_display_mode dst_mode; 250 bool dst_mode_valid; 251 }; 252 253 /** 254 * rk628_scaler_add_src_mode - add source mode for scaler 255 * @rk628: parent device 256 * @connector: DRM connector 257 * If need scale, call the function at last of get_modes. 258 */ 259 int rk628_scaler_add_src_mode(struct rk628 *rk628, 260 struct drm_connector *connector); 261 262 /** 263 * rk628_mode_copy - rk628 mode copy 264 * @rk628: parent device 265 * @dst: dst mode 266 * @src: src mode 267 * Call the function at mode_set, replace drm_mode_copy. 268 */ 269 void rk628_mode_copy(struct rk628 *rk628, struct drm_display_mode *dst, 270 const struct drm_display_mode *src); 271 272 #endif 273