1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Rockchip USBDP Combo PHY with Samsung IP block driver 4 * 5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd 6 */ 7 8 #ifndef __PHY_ROCKCHIP_USBDP_H_ 9 #define __PHY_ROCKCHIP_USBDP_H_ 10 11 #include <linux/bits.h> 12 13 /* RK3588 USBDP PHY Register Definitions */ 14 15 #define UDPHY_PCS 0x4000 16 #define UDPHY_PMA 0x8000 17 18 /* VO0 GRF Registers */ 19 #define RK3588_GRF_VO0_CON0 0x0000 20 #define RK3588_GRF_VO0_CON2 0x0008 21 #define DP_SINK_HPD_CFG BIT(11) 22 #define DP_SINK_HPD_SEL BIT(10) 23 #define DP_AUX_DIN_SEL BIT(9) 24 #define DP_AUX_DOUT_SEL BIT(8) 25 #define DP_LANE_SEL_N(n) GENMASK(2 * (n) + 1, 2 * (n)) 26 #define DP_LANE_SEL_ALL GENMASK(7, 0) 27 #define PHY_AUX_DP_DATA_POL_NORMAL 0 28 #define PHY_AUX_DP_DATA_POL_INVERT 1 29 30 /* PMA CMN Registers */ 31 #define CMN_LANE_MUX_AND_EN_OFFSET 0x0288 /* cmn_reg00A2 */ 32 #define CMN_DP_LANE_MUX_N(n) BIT((n) + 4) 33 #define CMN_DP_LANE_EN_N(n) BIT(n) 34 #define CMN_DP_LANE_MUX_ALL GENMASK(7, 4) 35 #define CMN_DP_LANE_EN_ALL GENMASK(3, 0) 36 #define PHY_LANE_MUX_USB 0 37 #define PHY_LANE_MUX_DP 1 38 39 #define CMN_DP_LINK_OFFSET 0x28c /*cmn_reg00A3 */ 40 #define CMN_DP_TX_LINK_BW GENMASK(6, 5) 41 #define CMN_DP_TX_LANE_SWAP_EN BIT(2) 42 43 #define CMN_SSC_EN_OFFSET 0x2d0 /* cmn_reg00B4 */ 44 #define CMN_ROPLL_SSC_EN BIT(1) 45 #define CMN_LCPLL_SSC_EN BIT(0) 46 47 #define CMN_ANA_LCPLL_DONE_OFFSET 0x0350 /* cmn_reg00D4 */ 48 #define CMN_ANA_LCPLL_LOCK_DONE BIT(7) 49 #define CMN_ANA_LCPLL_AFC_DONE BIT(6) 50 51 #define CMN_ANA_ROPLL_DONE_OFFSET 0x0354 /* cmn_reg00D5 */ 52 #define CMN_ANA_ROPLL_LOCK_DONE BIT(1) 53 #define CMN_ANA_ROPLL_AFC_DONE BIT(0) 54 55 #define CMN_DP_RSTN_OFFSET 0x038c /* cmn_reg00E3 */ 56 #define CMN_DP_INIT_RSTN BIT(3) 57 #define CMN_DP_CMN_RSTN BIT(2) 58 #define CMN_CDR_WTCHDG_EN BIT(1) 59 #define CMN_CDR_WTCHDG_MSK_CDR_EN BIT(0) 60 61 #define TRSV_ANA_TX_CLK_OFFSET_N(n) (0x854 + (n) * 0x800) /* trsv_reg0215 */ 62 #define LN_ANA_TX_SER_TXCLK_INV BIT(1) 63 64 #define TRSV_LN0_MON_RX_CDR_DONE_OFFSET 0x0b84 /* trsv_reg02E1 */ 65 #define TRSV_LN0_MON_RX_CDR_LOCK_DONE BIT(0) 66 67 #define TRSV_LN2_MON_RX_CDR_DONE_OFFSET 0x1b84 /* trsv_reg06E1 */ 68 #define TRSV_LN2_MON_RX_CDR_LOCK_DONE BIT(0) 69 70 #endif 71