1 /* 2 * tc35874x - Toshiba HDMI to CSI-2 bridge 3 * 4 * Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights 5 * reserved. 6 * 7 * This program is free software; you may redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; version 2 of the License. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 12 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 13 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 15 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 16 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 17 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 18 * SOFTWARE. 19 * 20 */ 21 22 /* 23 * References (c = chapter, p = page): 24 * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60 25 * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls 26 * REF_03 - Toshiba, TC358749XBG (H2C+), Functional Specification, Rev 0.74 27 */ 28 29 #ifndef _TC35874X_ 30 #define _TC35874X_ 31 32 enum tc35874x_ddc5v_delays { 33 DDC5V_DELAY_0_MS, 34 DDC5V_DELAY_50_MS, 35 DDC5V_DELAY_100_MS, 36 DDC5V_DELAY_200_MS, 37 }; 38 39 enum tc35874x_hdmi_detection_delay { 40 HDMI_MODE_DELAY_0_MS, 41 HDMI_MODE_DELAY_25_MS, 42 HDMI_MODE_DELAY_50_MS, 43 HDMI_MODE_DELAY_100_MS, 44 }; 45 46 struct tc35874x_platform_data { 47 /* System clock connected to REFCLK (pin H5) */ 48 u32 refclk_hz; /* 26 MHz, 27 MHz or 42 MHz */ 49 50 /* DDC +5V debounce delay to avoid spurious interrupts when the cable 51 * is connected. 52 * Sets DDC5V_MODE in register DDC_CTL. 53 * Default: DDC5V_DELAY_0_MS 54 */ 55 enum tc35874x_ddc5v_delays ddc5v_delay; 56 57 bool enable_hdcp; 58 59 /* 60 * The FIFO size is 512x32, so Toshiba recommend to set the default FIFO 61 * level to somewhere in the middle (e.g. 300), so it can cover speed 62 * mismatches in input and output ports. 63 */ 64 u16 fifo_level; 65 66 /* Bps pr lane is (refclk_hz / pll_prd) * pll_fbd */ 67 u16 pll_prd; 68 u16 pll_fbd; 69 70 /* CSI 71 * Calculate CSI parameters with REF_02 for the highest resolution your 72 * CSI interface can handle. The driver will adjust the number of CSI 73 * lanes in use according to the pixel clock. 74 * 75 * The values in brackets are calculated with REF_02 when the number of 76 * bps pr lane is 823.5 MHz, and can serve as a starting point. 77 */ 78 u32 lineinitcnt; /* (0x00001770) */ 79 u32 lptxtimecnt; /* (0x00000005) */ 80 u32 tclk_headercnt; /* (0x00001d04) */ 81 u32 tclk_trailcnt; /* (0x00000000) */ 82 u32 ths_headercnt; /* (0x00000505) */ 83 u32 twakeup; /* (0x00004650) */ 84 u32 tclk_postcnt; /* (0x00000000) */ 85 u32 ths_trailcnt; /* (0x00000004) */ 86 u32 hstxvregcnt; /* (0x00000005) */ 87 88 /* DVI->HDMI detection delay to avoid unnecessary switching between DVI 89 * and HDMI mode. 90 * Sets HDMI_DET_V in register HDMI_DET. 91 * Default: HDMI_MODE_DELAY_0_MS 92 */ 93 enum tc35874x_hdmi_detection_delay hdmi_detection_delay; 94 95 /* Reset PHY automatically when TMDS clock goes from DC to AC. 96 * Sets PHY_AUTO_RST2 in register PHY_CTL2. 97 * Default: false 98 */ 99 bool hdmi_phy_auto_reset_tmds_detected; 100 101 /* Reset PHY automatically when TMDS clock passes 21 MHz. 102 * Sets PHY_AUTO_RST3 in register PHY_CTL2. 103 * Default: false 104 */ 105 bool hdmi_phy_auto_reset_tmds_in_range; 106 107 /* Reset PHY automatically when TMDS clock is detected. 108 * Sets PHY_AUTO_RST4 in register PHY_CTL2. 109 * Default: false 110 */ 111 bool hdmi_phy_auto_reset_tmds_valid; 112 113 /* Reset HDMI PHY automatically when hsync period is out of range. 114 * Sets H_PI_RST in register HV_RST. 115 * Default: false 116 */ 117 bool hdmi_phy_auto_reset_hsync_out_of_range; 118 119 /* Reset HDMI PHY automatically when vsync period is out of range. 120 * Sets V_PI_RST in register HV_RST. 121 * Default: false 122 */ 123 bool hdmi_phy_auto_reset_vsync_out_of_range; 124 }; 125 126 /* custom controls */ 127 /* Audio sample rate in Hz */ 128 #define TC35874X_CID_AUDIO_SAMPLING_RATE (V4L2_CID_USER_TC35874X_BASE + 0) 129 /* Audio present status */ 130 #define TC35874X_CID_AUDIO_PRESENT (V4L2_CID_USER_TC35874X_BASE + 1) 131 132 #endif