1 /******************************************************************************
2 * @file mpu_armv7.h
3 * @brief CMSIS MPU API for Armv7-M MPU
4 * @version V5.0.4
5 * @date 10. January 2018
6 ******************************************************************************/
7 /*
8 * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 #if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28 #pragma clang system_header /* treat file as system include file */
29 #endif
30
31 #ifndef ARM_MPU_ARMV7_H
32 #define ARM_MPU_ARMV7_H
33
34 #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
35 #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
36 #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
37 #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
38 #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
39 #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
40 #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
41 #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
42 #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
43 #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
44 #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
45 #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
46 #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
47 #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
48 #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
49 #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
50 #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
51 #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
52 #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
53 #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
54 #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
55 #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
56 #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
57 #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
58 #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
59 #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
60 #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
61 #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
62
63 #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
64 #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
65 #define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
66 #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
67 #define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
68 #define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
69
70 /** MPU Region Base Address Register Value
71 *
72 * \param Region The region to be configured, number 0 to 15.
73 * \param BaseAddress The base address for the region.
74 */
75 #define ARM_MPU_RBAR(Region, BaseAddress) \
76 (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
77 ((Region) & MPU_RBAR_REGION_Msk) | \
78 (MPU_RBAR_VALID_Msk))
79
80 /**
81 * MPU Memory Access Attributes
82 *
83 * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
84 * \param IsShareable Region is shareable between multiple bus masters.
85 * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
86 * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
87 */
88 #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
89 ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
90 (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
91 (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
92 (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
93
94 /**
95 * MPU Region Attribute and Size Register Value
96 *
97 * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
98 * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
99 * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
100 * \param SubRegionDisable Sub-region disable field.
101 * \param Size Region size of the region to be configured, for example 4K, 8K.
102 */
103 #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
104 ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
105 (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
106 (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
107
108 /**
109 * MPU Region Attribute and Size Register Value
110 *
111 * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
112 * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
113 * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
114 * \param IsShareable Region is shareable between multiple bus masters.
115 * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
116 * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
117 * \param SubRegionDisable Sub-region disable field.
118 * \param Size Region size of the region to be configured, for example 4K, 8K.
119 */
120 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
121 ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
122
123 /**
124 * MPU Memory Access Attribute for strongly ordered memory.
125 * - TEX: 000b
126 * - Shareable
127 * - Non-cacheable
128 * - Non-bufferable
129 */
130 #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
131
132 /**
133 * MPU Memory Access Attribute for device memory.
134 * - TEX: 000b (if non-shareable) or 010b (if shareable)
135 * - Shareable or non-shareable
136 * - Non-cacheable
137 * - Bufferable (if shareable) or non-bufferable (if non-shareable)
138 *
139 * \param IsShareable Configures the device memory as shareable or non-shareable.
140 */
141 #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
142
143 /**
144 * MPU Memory Access Attribute for normal memory.
145 * - TEX: 1BBb (reflecting outer cacheability rules)
146 * - Shareable or non-shareable
147 * - Cacheable or non-cacheable (reflecting inner cacheability rules)
148 * - Bufferable or non-bufferable (reflecting inner cacheability rules)
149 *
150 * \param OuterCp Configures the outer cache policy.
151 * \param InnerCp Configures the inner cache policy.
152 * \param IsShareable Configures the memory as shareable or non-shareable.
153 */
154 #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
155
156 /**
157 * MPU Memory Access Attribute non-cacheable policy.
158 */
159 #define ARM_MPU_CACHEP_NOCACHE 0U
160
161 /**
162 * MPU Memory Access Attribute write-back, write and read allocate policy.
163 */
164 #define ARM_MPU_CACHEP_WB_WRA 1U
165
166 /**
167 * MPU Memory Access Attribute write-through, no write allocate policy.
168 */
169 #define ARM_MPU_CACHEP_WT_NWA 2U
170
171 /**
172 * MPU Memory Access Attribute write-back, no write allocate policy.
173 */
174 #define ARM_MPU_CACHEP_WB_NWA 3U
175
176
177 /**
178 * Struct for a single MPU Region
179 */
180 typedef struct {
181 uint32_t RBAR; //!< The region base address register value (RBAR)
182 uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
183 } ARM_MPU_Region_t;
184
185 /** Enable the MPU.
186 * \param MPU_Control Default access permissions for unconfigured regions.
187 */
ARM_MPU_Enable(uint32_t MPU_Control)188 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
189 {
190 __DSB();
191 __ISB();
192 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
193 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
194 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
195 #endif
196 }
197
198 /** Disable the MPU.
199 */
ARM_MPU_Disable(void)200 __STATIC_INLINE void ARM_MPU_Disable(void)
201 {
202 __DSB();
203 __ISB();
204 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
205 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
206 #endif
207 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
208 }
209
210 /** Clear and disable the given MPU region.
211 * \param rnr Region number to be cleared.
212 */
ARM_MPU_ClrRegion(uint32_t rnr)213 __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
214 {
215 MPU->RNR = rnr;
216 MPU->RASR = 0U;
217 }
218
219 /** Configure an MPU region.
220 * \param rbar Value for RBAR register.
221 * \param rsar Value for RSAR register.
222 */
ARM_MPU_SetRegion(uint32_t rbar,uint32_t rasr)223 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
224 {
225 MPU->RBAR = rbar;
226 MPU->RASR = rasr;
227 }
228
229 /** Configure the given MPU region.
230 * \param rnr Region number to be configured.
231 * \param rbar Value for RBAR register.
232 * \param rsar Value for RSAR register.
233 */
ARM_MPU_SetRegionEx(uint32_t rnr,uint32_t rbar,uint32_t rasr)234 __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
235 {
236 MPU->RNR = rnr;
237 MPU->RBAR = rbar;
238 MPU->RASR = rasr;
239 }
240
241 /** Memcopy with strictly ordered memory access, e.g. for register targets.
242 * \param dst Destination data is copied to.
243 * \param src Source data is copied from.
244 * \param len Amount of data words to be copied.
245 */
orderedCpy(volatile uint32_t * dst,const uint32_t * __RESTRICT src,uint32_t len)246 __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
247 {
248 uint32_t i;
249 for (i = 0U; i < len; ++i)
250 {
251 dst[i] = src[i];
252 }
253 }
254
255 /** Load the given number of MPU regions from a table.
256 * \param table Pointer to the MPU configuration table.
257 * \param cnt Amount of regions to be configured.
258 */
ARM_MPU_Load(ARM_MPU_Region_t const * table,uint32_t cnt)259 __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
260 {
261 const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
262 while (cnt > MPU_TYPE_RALIASES) {
263 orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
264 table += MPU_TYPE_RALIASES;
265 cnt -= MPU_TYPE_RALIASES;
266 }
267 orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
268 }
269
270 #endif
271