1 /******************************************************************************
2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK")
3 * All rights reserved.
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************/
18 #ifndef SPI_H
19 #define SPI_H
20
21 #include "dma.h"
22 #include "gpio.h"
23 #include "reg_include/register_b91.h"
24
25 /** @page SPI
26 *
27 * Introduction
28 * ===============
29 * B91 supports two spi
30 *
31 * API Reference
32 * ===============
33 * Header File: spi.h
34 */
35
36 typedef enum {
37 SPI_RXFIFO_OR_INT_EN = BIT(0),
38 SPI_TXFIFO_UR_INT_EN = BIT(1),
39 SPI_RXFIFO_INT_EN = BIT(2),
40 SPI_TXFIFO_INT_EN = BIT(3),
41 SPI_END_INT_EN = BIT(4),
42 SPI_SLV_CMD_EN = BIT(5),
43 } spi_irq_mask;
44
45 typedef enum {
46 SPI_RXF_OR_INT = BIT(2),
47 SPI_TXF_UR_INT = BIT(3),
48 SPI_RXF_INT = BIT(4),
49 SPI_TXF_INT = BIT(5),
50 SPI_END_INT = BIT(6),
51 SPI_SLV_CMD_INT = BIT(7),
52 } spi_irq_status_e;
53
54 typedef enum {
55 PSPI_MODULE = 0,
56 HSPI_MODULE = 1,
57 } spi_sel_e;
58
59 /**
60 * @brief Define the work mode.
61 */
62 typedef enum {
63 SPI_MODE0 = 0,
64 SPI_MODE2,
65 SPI_MODE1,
66 SPI_MODE3,
67 } spi_mode_type_e;
68
69 /**
70 * @brief Define the mode for SPI io mode.
71 */
72 typedef enum { SPI_SINGLE_MODE = 0, SPI_DUAL_MODE = 1, HSPI_QUAD_MODE = 2, SPI_3_LINE_MODE = 3 } spi_io_mode_e;
73
74 typedef enum {
75 SPI_NOMAL = 0,
76 SPI_3LINE = 3,
77 } spi_nomal_3line_mode_e;
78
79 typedef enum { PSPI_SINGLE = 0, PSPI_DUAL = 1, PSPI_3LINE = 3 } pspi_single_dual_mode_e;
80
81 typedef enum { HSPI_SINGLE = 0, HSPI_DUAL = 1, HSPI_QUAD = 2, HSPI_3LINE = 3 } hspi_single_dual_quad_mode_e;
82
83 /**
84 * @brief Define the SPI command & translate mode.
85 */
86 typedef enum {
87 SPI_MODE_WRITE_AND_READ = 0, // write and read at the same.must enbale CmdEn
88 SPI_MODE_WRITE_ONLY, // write
89 SPI_MODE_READ_ONLY, // read must enbale CmdEn
90 SPI_MODE_WRITE_READ, // write_ read
91 SPI_MODE_READ_WRITE, // read_write
92 SPI_MODE_WRITE_DUMMY_READ, // write_dummy_read
93 SPI_MODE_READ_DUMMY_WRITE, // read_ dummy_write must enbale CmdEn
94 SPI_MODE_NONE_DATA, // must enbale CmdEn
95 SPI_MODE_DUMMY_WRITE, // dummy_write
96 SPI_MODE_DUMMY_READ, // dummy_read
97 SPI_MODE_RESERVED,
98 } spi_tans_mode_e;
99
100 typedef enum {
101 SPI_MODE_WR_WRITE_ONLY = 1, // write
102 SPI_MODE_WR_DUMMY_WRITE = 8, // dummy_write
103 } spi_wr_tans_mode_e;
104
105 typedef enum {
106 SPI_MODE_RD_READ_ONLY = 2, // must enbale CmdEn
107 SPI_MODE_RD_DUMMY_READ = 9, // dummy_read
108 } spi_rd_tans_mode_e;
109
110 typedef enum {
111 SPI_MODE_WR_RD = 3, // must enbale CmdEn
112 SPI_MODE_WR_DUMMY_RD = 5, // write_dummy_read
113 } spi_wr_rd_tans_mode_e;
114
115 typedef struct {
116 hspi_single_dual_quad_mode_e hspi_io_mode; // set spi interface mode
117 unsigned char hspi_dummy_cnt; // set dummy cnt if tans_mode have dummy .
118 unsigned char hspi_cmd_en; // enable cmd phase
119 unsigned char hspi_addr_en; // enable address phase
120 unsigned char hspi_addr_len; // enable address phase
121 unsigned char hspi_cmd_fmt_en; // if cmd_en enable cmd fmt will follow the interface (dual/quad)
122 unsigned char hspi_addr_fmt_en; // if addr_en enable addr fmt will follow the interface (dual/quad)
123 } hspi_config_t;
124
125 typedef struct {
126 pspi_single_dual_mode_e pspi_io_mode; // set spi interface mode
127 unsigned char pspi_dummy_cnt; // set dummy cnt if tans_mode have dummy .
128 _Bool pspi_cmd_en; // enable cmd phase
129 } pspi_config_t;
130
131 typedef enum {
132 SPI_SLAVE_WRITE_DATA_CMD = 0x00,
133 SPI_SLAVE_WRITE_DATA_DUAL_CMD = FLD_SPI_CMD_DATA_DUAL,
134 SPI_SLAVE_WRITE_ADDR_DUAL_CMD = FLD_SPI_CMD_ADDR_DUAL,
135
136 SPI_SLAVE_WRITE_DATA_DUAL_4CYC_CMD = FLD_SPI_CMD_DATA_DUAL | FLD_SPI_CMD_RD_DUMMY_4CYCLE,
137 SPI_SLAVE_WRITE_ADDR_DUAL_4CYC_CMD = FLD_SPI_CMD_ADDR_DUAL | FLD_SPI_CMD_RD_DUMMY_4CYCLE,
138 SPI_SLAVE_WRITE_DATA_AND_ADDR_DUL_4CYC_CMD =
139 FLD_SPI_CMD_ADDR_DUAL | FLD_SPI_CMD_DATA_DUAL | FLD_SPI_CMD_RD_DUMMY_4CYCLE,
140 } spi_slave_write_cmd_e;
141
142 typedef enum {
143 SPI_SLAVE_READ_DATA_CMD = FLD_SPI_CMD_RD_EN,
144 SPI_SLAVE_READ_DATA_DUAL_CMD = FLD_SPI_CMD_RD_EN | FLD_SPI_CMD_DATA_DUAL,
145 SPI_SLAVE_READ_ADDR_DUAL_CMD = FLD_SPI_CMD_RD_EN | FLD_SPI_CMD_ADDR_DUAL,
146
147 SPI_SLAVE_READ_DATA_DUAL_4CYC_CMD = FLD_SPI_CMD_RD_EN | FLD_SPI_CMD_DATA_DUAL | FLD_SPI_CMD_RD_DUMMY_4CYCLE,
148 SPI_SLAVE_READ_ADDR_DUAL_4CYC_CMD = FLD_SPI_CMD_RD_EN | FLD_SPI_CMD_ADDR_DUAL | FLD_SPI_CMD_RD_DUMMY_4CYCLE,
149
150 SPI_SLAVE_READ_DATA_AND_ADDR_DUL_4CYC_CMD =
151 FLD_SPI_CMD_RD_EN | FLD_SPI_CMD_ADDR_DUAL | FLD_SPI_CMD_DATA_DUAL | FLD_SPI_CMD_RD_DUMMY_4CYCLE,
152 } spi_slave_read_cmd_e;
153
154 typedef enum {
155 SPI_READ_STATUS_SINGLE_CMD = 0x05,
156 SPI_READ_STATUS_DUAL_CMD = 0x15,
157 HSPI_READ_STATUS_QUAD_CMD = 0x25,
158 SPI_READ_DATA_SINGLE_CMD = 0x0B,
159 SPI_READ_DATA_DUAL_CMD = 0x0C,
160 HSPI_READ_DATA_QUAD_CMD = 0x0E,
161 SPI_WRITE_DATA_SINGLE_CMD = 0x51,
162 SPI_WRITE_DATA_DUAL_CMD = 0x52,
163 HSPI_WRITE_DATA_QUAD_CMD = 0x54,
164 } pspi_hspi_cmd_e;
165 /**
166 * @brief Define APS1604M-3SQR QSPI PSRAM CMD.
167 */
168 typedef enum {
169 PSRAM_READ_CMD = 0x03,
170 PSRAM_FAST_READ_CMD = 0x0B,
171 PSRAM_FAST_READ_QUAD_CMD = 0xEB,
172
173 PSRAM_WRITE_CMD = 0x02,
174 PSRAM_QUAD_WRITE_CMD = 0x38, //
175 PSRAM_WRAPPED_READ_CMD = 0x8B,
176 PSRAM_WRAPPED_WRITE_CMD = 0x82,
177
178 PSRAM_MODE_RG_READ_CMD = 0xB5,
179 PSRAM_MODE_RG_WRITE_CMD = 0xB1,
180
181 PSRAM_ENTER_QUAD_MODE_CMD = 0x35,
182 PSRAM_EXIT_QUAD_MODE_CMD = 0xF5,
183
184 PSRAM_REST_ENABLE_CMD = 0x66,
185 PSRAM_REST_CMD = 0x99,
186 PSRAM_BURST_LENGTH_TOGGLE_CMD = 0xC0,
187 PSRAM_READ_ID_CMD = 0x95,
188 } spi_xip_cmd_e;
189
190 /**
191 * @brief Define panel 2data_lane_mode
192 */
193 typedef enum {
194 HSPI_2DATA_LANE_CLOSE = 0x00,
195 HSPI_2DATA_LANE_RGB565 = 0x01,
196 HSPI_2DATA_LANE_RGB666 = 0x03,
197 HSPI_2DATA_LANE_RGB888 = 0x07,
198 } hspi_panel_2data_lane_mode_e;
199
200 /**
201 * @brief Define the SPI io.
202 */
203 typedef enum {
204 HSPI_CLK_PB4 = GPIO_PB4,
205 HSPI_CLK_PA2 = GPIO_PA2,
206 } hspi_clk_pin_def_e;
207
208 typedef enum {
209 HSPI_CSN_PB6 = GPIO_PB6,
210 HSPI_CSN_PA1 = GPIO_PA1,
211 } hspi_csn_pin_def_e;
212
213 typedef enum {
214 HSPI_MOSI_IO0_PB3 = GPIO_PB3,
215 HSPI_MOSI_IO0_PA4 = GPIO_PA4,
216 } hspi_mosi_io0_pin_def_e;
217
218 typedef enum {
219 HSPI_MISO_IO1_PB2 = GPIO_PB2,
220 HSPI_MISO_IO1_PA3 = GPIO_PA3,
221 } hspi_miso_io1_pin_def_e;
222
223 typedef enum {
224 HSPI_WP_IO2_PB1 = GPIO_PB1,
225 } hspi_wp_io2_pin_def_e;
226
227 typedef enum {
228 HSPI_HOLD_IO3_PB0 = GPIO_PB0,
229 } hspi_hold_io3_pin_def_e;
230
231 typedef enum {
232 HSPI_CLK_PB4_PIN = GPIO_PB4,
233 HSPI_CLK_PA2_PIN = GPIO_PA2,
234
235 HSPI_CSN_PB6_PIN = GPIO_PB6,
236 HSPI_CSN_PA1_PIN = GPIO_PA1,
237
238 HSPI_MOSI_IO0_PB3_PIN = GPIO_PB3,
239 HSPI_MOSI_IO0_PA4_PIN = GPIO_PA4,
240
241 HSPI_MISO_IO1_PB2_PIN = GPIO_PB2,
242 HSPI_MISO_IO1_PA3_PIN = GPIO_PA3,
243
244 HSPI_WP_IO2_PB1_PIN = GPIO_PB1,
245 HSPI_HOLD_IO3_PB0_PIN = GPIO_PB0,
246 HSPI_NONE_PIN = 0xfff,
247 } hspi_pin_def_e;
248
249 typedef struct {
250 hspi_clk_pin_def_e hspi_clk_pin;
251 hspi_csn_pin_def_e hspi_csn_pin;
252 hspi_mosi_io0_pin_def_e hspi_mosi_io0_pin;
253 hspi_miso_io1_pin_def_e hspi_miso_io1_pin;
254 hspi_wp_io2_pin_def_e hspi_wp_io2_pin;
255 hspi_hold_io3_pin_def_e hspi_hold_io3_pin;
256 } hspi_pin_config_t;
257
258 typedef enum {
259 PSPI_CLK_PC5 = GPIO_PC5,
260 PSPI_CLK_PB5 = GPIO_PB5,
261 PSPI_CLK_PD1 = GPIO_PD1,
262 } pspi_clk_pin_def_e;
263
264 typedef enum {
265 PSPI_CSN_PC4 = GPIO_PC4,
266 PSPI_CSN_PC0 = GPIO_PC0,
267 PSPI_CSN_PD0 = GPIO_PD0,
268 } pspi_csn_pin_def_e;
269
270 typedef enum {
271 PSPI_MOSI_IO0_PC7 = GPIO_PC7,
272 PSPI_MOSI_IO0_PB7 = GPIO_PB7,
273 PSPI_MOSI_IO0_PD3 = GPIO_PD3,
274 } pspi_mosi_io0_pin_def_e;
275
276 typedef enum {
277 PSPI_MISO_IO1_PC6 = GPIO_PC6,
278 PSPI_MISO_IO1_PB6 = GPIO_PB6,
279 PSPI_MISO_IO1_PD2 = GPIO_PD2,
280 } pspi_miso_io1_pin_def_e;
281
282 typedef enum {
283 PSPI_CLK_PC5_PIN = GPIO_PC5,
284 PSPI_CLK_PB5_PIN = GPIO_PB5,
285 PSPI_CLK_PD1_PIN = GPIO_PD1,
286
287 PSPI_CSN_PC4_PIN = GPIO_PC4,
288 PSPI_CSN_PC0_PIN = GPIO_PC0,
289 PSPI_CSN_PD0_PIN = GPIO_PD0,
290
291 PSPI_MOSI_IO0_PC7_PIN = GPIO_PC7,
292 PSPI_MOSI_IO0_PB7_PIN = GPIO_PB7,
293 PSPI_MOSI_IO0_PD3_PIN = GPIO_PD3,
294
295 PSPI_MISO_IO1_PC6_PIN = GPIO_PC6,
296 PSPI_MISO_IO1_PB6_PIN = GPIO_PB6,
297 PSPI_MISO_IO1_PD2_PIN = GPIO_PD2,
298 PSPI_NONE_PIN = 0xfff,
299 } pspi_pin_def_e;
300
301 typedef struct {
302 pspi_clk_pin_def_e pspi_clk_pin;
303 pspi_csn_pin_def_e pspi_csn_pin;
304 pspi_mosi_io0_pin_def_e pspi_mosi_io0_pin;
305 pspi_miso_io1_pin_def_e pspi_miso_io1_pin;
306 } pspi_pin_config_t;
307
308 /**
309 * @brief This function reset HSPI module.
310 * @return none
311 */
hspi_reset(void)312 static inline void hspi_reset(void)
313 {
314 reg_rst0 &= (~FLD_RST0_HSPI);
315 reg_rst0 |= FLD_RST0_HSPI;
316 }
317 /**
318 * @brief This function reset PSPI module.
319 * @return none
320 */
pspi_reset(void)321 static inline void pspi_reset(void)
322 {
323 reg_rst1 &= (~FLD_RST1_PSPI);
324 reg_rst1 |= FLD_RST1_PSPI;
325 }
326
327 /**
328 * @brief This function get tx_fifo number.
329 * @param[in] spi_sel - the spi module.
330 * @return ntx_fifo - number that wait to be sent.
331 */
spi_get_txfifo_num(spi_sel_e spi_sel)332 static inline unsigned char spi_get_txfifo_num(spi_sel_e spi_sel)
333 {
334 return (reg_spi_fifo_num(spi_sel) & FLD_SPI_TXF_NUM) >> 4;
335 }
336
337 /**
338 * @brief This function get rx_fifo number.
339 * @param[in] spi_sel - the spi module.
340 * @return rx_fifo - num that have been received.
341 */
spi_get_rxfifo_num(spi_sel_e spi_sel)342 static inline unsigned char spi_get_rxfifo_num(spi_sel_e spi_sel)
343 {
344 return reg_spi_fifo_num(spi_sel) & FLD_SPI_RXF_NUM;
345 }
346
347 /**
348 * @brief This function set SPI rx_cnt.
349 * @param[in] spi_sel - the spi module.
350 * @param[in] cnt - rx amount of data.
351 * @return none
352 */
spi_rx_cnt(spi_sel_e spi_sel,unsigned int cnt)353 static inline void spi_rx_cnt(spi_sel_e spi_sel, unsigned int cnt)
354 {
355 reg_spi_rx_cnt2(spi_sel) = ((cnt - 1) >> 16) & 0xff;
356 reg_spi_rx_cnt1(spi_sel) = ((cnt - 1) >> 8) & 0xff;
357 reg_spi_rx_cnt0(spi_sel) = (cnt - 1) & 0xff;
358 }
359
360 /**
361 * @brief This function set SPI tx_cnt.
362 * @param[in] spi_sel - the spi module.
363 * @param[in] cnt - tx amount of data.
364 * @return none
365 */
spi_tx_cnt(spi_sel_e spi_sel,unsigned int cnt)366 static inline void spi_tx_cnt(spi_sel_e spi_sel, unsigned int cnt)
367 {
368 reg_spi_tx_cnt2(spi_sel) = ((cnt - 1) >> 16) & 0xff;
369 reg_spi_tx_cnt1(spi_sel) = ((cnt - 1) >> 8) & 0xff;
370 reg_spi_tx_cnt0(spi_sel) = (cnt - 1) & 0xff;
371 }
372
373 /**
374 * @brief This function clear tx_fifo.
375 * @param[in] spi_sel - the spi module.
376 * @return none
377 */
spi_tx_fifo_clr(spi_sel_e spi_sel)378 static inline void spi_tx_fifo_clr(spi_sel_e spi_sel)
379 {
380 BM_SET(reg_spi_fifo_state(spi_sel), FLD_SPI_TXF_CLR);
381 }
382
383 /**
384 * @brief This function clear rx_fifo.
385 * @param[in] spi_sel - the spi module.
386 * @return none
387 */
spi_rx_fifo_clr(spi_sel_e spi_sel)388 static inline void spi_rx_fifo_clr(spi_sel_e spi_sel)
389 {
390 BM_SET(reg_spi_fifo_state(spi_sel), FLD_SPI_RXF_CLR);
391 }
392
393 /**
394 * @brief This function set hspi command content.
395 * @param[in] spi_sel - the spi module.
396 * @param[in] cmd - command content.
397 * @return none
398 */
spi_set_cmd(spi_sel_e spi_sel,unsigned char cmd)399 static inline void spi_set_cmd(spi_sel_e spi_sel, unsigned char cmd)
400 {
401 reg_spi_trans1(spi_sel) = cmd;
402 }
403
404 /**
405 * @brief This function servers to enable cmd which will sent a byte cmd.
406 * @param[in] spi_sel - the spi module.
407 * @return none
408 */
spi_cmd_en(spi_sel_e spi_sel)409 static inline void spi_cmd_en(spi_sel_e spi_sel)
410 {
411 BM_SET(reg_spi_mode2(spi_sel), FLD_SPI_CMD_EN);
412 }
413
414 /**
415 * @brief This function servers to disable cmd which will not sent cmd.
416 * @param[in] spi_sel - the spi module.
417 * @return none
418 */
spi_cmd_dis(spi_sel_e spi_sel)419 static inline void spi_cmd_dis(spi_sel_e spi_sel)
420 {
421 BM_CLR(reg_spi_mode2(spi_sel), FLD_SPI_CMD_EN);
422 }
423
424 /**
425 * @brief This function servers enable cmd format,the format of cmd phase is the same as the data phase(Dual/Quad).
426 * @return none
427 */
hspi_cmd_fmt_en(void)428 static inline void hspi_cmd_fmt_en(void)
429 {
430 BM_SET(reg_spi_mode2(HSPI_MODULE), FLD_HSPI_CMD_FMT);
431 }
432
433 /**
434 * @brief This function servers disable cmd format.
435 * @return none
436 */
hspi_cmd_fmt_dis(void)437 static inline void hspi_cmd_fmt_dis(void)
438 {
439 BM_CLR(reg_spi_mode2(HSPI_MODULE), FLD_HSPI_CMD_FMT);
440 }
441
442 /**
443 * @brief This function servers to enable hspi quad mode.
444 * @return none
445 */
hspi_quad_mode_en(void)446 static inline void hspi_quad_mode_en(void)
447 {
448 BM_SET(reg_spi_mode2(HSPI_MODULE), FLD_HSPI_QUAD);
449 }
450
451 /**
452 * @brief This function servers to disable hspi quad mode.
453 * @param[in] spi_sel - the spi module.
454 * @return none
455 */
hspi_quad_mode_dis(spi_sel_e spi_sel)456 static inline void hspi_quad_mode_dis(spi_sel_e spi_sel)
457 {
458 BM_CLR(reg_spi_mode2(spi_sel), FLD_HSPI_QUAD);
459 }
460
461 /**
462 * @brief This function servers to enable hspi dual mode.
463 * @param[in] spi_sel - the spi module.
464 * @return none
465 */
spi_dual_mode_en(spi_sel_e spi_sel)466 static inline void spi_dual_mode_en(spi_sel_e spi_sel)
467 {
468 BM_SET(reg_spi_mode0(spi_sel), FLD_SPI_DUAL);
469 }
470
471 /**
472 * @brief This function servers to disable hspi dual mode.
473 * @param[in] spi_sel - the spi module.
474 * @return none
475 */
spi_dual_mode_dis(spi_sel_e spi_sel)476 static inline void spi_dual_mode_dis(spi_sel_e spi_sel)
477 {
478 BM_CLR(reg_spi_mode0(spi_sel), FLD_SPI_DUAL);
479 }
480
481 /**
482 * @brief This function servers to enable hspi 3line mode.
483 * @param[in] spi_sel - the spi module.
484 * @return none
485 */
spi_3line_mode_en(spi_sel_e spi_sel)486 static inline void spi_3line_mode_en(spi_sel_e spi_sel)
487 {
488 BM_SET(reg_spi_mode0(spi_sel), FLD_SPI_3LINE);
489 }
490
491 /**
492 * @brief This function servers to disable hspi 3line mode..
493 * @param[in] spi_sel - the spi module.
494 * @return none
495 */
spi_3line_mode_dis(spi_sel_e spi_sel)496 static inline void spi_3line_mode_dis(spi_sel_e spi_sel)
497 {
498 BM_CLR(reg_spi_mode0(spi_sel), FLD_SPI_3LINE);
499 }
500
501 /**
502 * @brief This function to enable address format.the format of addr phase is the same as the data phase(Dual/Quad).
503 * @return none
504 */
hspi_addr_fmt_en(void)505 static inline void hspi_addr_fmt_en(void)
506 {
507 BM_SET(reg_hspi_xip_ctrl, FLD_HSPI_ADDR_FMT);
508 }
509
510 /**
511 * @brief This function to disable address format.
512 * @return none
513 */
hspi_addr_fmt_dis(void)514 static inline void hspi_addr_fmt_dis(void)
515 {
516 BM_CLR(reg_hspi_xip_ctrl, FLD_HSPI_ADDR_FMT);
517 }
518
519 /**
520 * @brief This function to determine whether the bus is busy.
521 * @param[in] spi_sel - the spi module.
522 * @return 1:Indicates that the bus is busy. 0:Indicates that the bus is free.
523 */
spi_is_busy(spi_sel_e spi_sel)524 static inline _Bool spi_is_busy(spi_sel_e spi_sel)
525 {
526 return reg_spi_status(spi_sel) & FLD_HSPI_BUSY;
527 }
528
529 /**
530 * @brief This function enable tx dma.
531 * @param[in] spi_sel - the spi module.
532 * @return none
533 */
spi_tx_dma_en(spi_sel_e spi_sel)534 static inline void spi_tx_dma_en(spi_sel_e spi_sel)
535 {
536 BM_SET(reg_spi_trans2(spi_sel), FLD_SPI_TX_DMA_EN);
537 }
538
539 /**
540 * @brief This function disable tx dma.
541 * @param[in] spi_sel - the spi module.
542 * @return none
543 */
spi_tx_dma_dis(spi_sel_e spi_sel)544 static inline void spi_tx_dma_dis(spi_sel_e spi_sel)
545 {
546 BM_CLR(reg_spi_trans2(spi_sel), FLD_SPI_TX_DMA_EN);
547 }
548
549 /**
550 * @brief This function enable rx dma.
551 * @param[in] spi_sel - the spi module.
552 * @return none
553 */
spi_rx_dma_en(spi_sel_e spi_sel)554 static inline void spi_rx_dma_en(spi_sel_e spi_sel)
555 {
556 BM_SET(reg_spi_trans2(spi_sel), FLD_SPI_RX_DMA_EN);
557 }
558
559 /**
560 * @brief This function disable rx dma.
561 * @param[in] spi_sel - the spi module.
562 * @return none
563 */
spi_rx_dma_dis(spi_sel_e spi_sel)564 static inline void spi_rx_dma_dis(spi_sel_e spi_sel)
565 {
566 BM_CLR(reg_spi_trans2(spi_sel), FLD_SPI_RX_DMA_EN);
567 }
568
569 /**
570 * @brief This function set xip write command content.
571 * @param[in] wr_cmd - write command content.
572 * @return none
573 */
hspi_xip_set_wr_cmd(unsigned char wr_cmd)574 static inline void hspi_xip_set_wr_cmd(unsigned char wr_cmd)
575 {
576 reg_hspi_xip_wr_cmd = wr_cmd;
577 }
578
579 /**
580 * @brief This function set xip read command content.
581 * @param[in] rd_cmd - read command content.
582 * @return none
583 */
hspi_xip_set_rd_cmd(unsigned char rd_cmd)584 static inline void hspi_xip_set_rd_cmd(unsigned char rd_cmd)
585 {
586 reg_hspi_xip_rd_cmd = rd_cmd;
587 }
588
589 /**
590 * @brief This function set xip address offset.
591 * @param[in] addr_offset - the offset of data.
592 * @return none
593 */
hspi_xip_addr_offset(unsigned int addr_offset)594 static inline void hspi_xip_addr_offset(unsigned int addr_offset)
595 {
596 reg_hspi_xip_addr_offset0 = addr_offset & 0xff;
597 reg_hspi_xip_addr_offset1 = (addr_offset >> 8) & 0xff;
598 reg_hspi_xip_addr_offset2 = (addr_offset >> 16) & 0xff;
599 reg_hspi_xip_addr_offset3 = (addr_offset >> 24) & 0xff;
600 }
601
602 /**
603 * @brief This function servers to set xip read transfer mode.
604 * @param[in] rd_mode - read mode in enum hspi_tans_mode_e.
605 * @return none
606 */
hspi_xip_read_transmode(unsigned char rd_mode)607 static inline void hspi_xip_read_transmode(unsigned char rd_mode)
608 {
609 reg_hspi_xip_trans_mode &= (~FLD_HSPI_XIP_RD_TRANS_MODE);
610 reg_hspi_xip_trans_mode |= (rd_mode & 0xf) << 4;
611 }
612
613 /**
614 * @brief This function servers to set xip write transfer mode.
615 * @param[in] wr_mode - write mode in enum hspi_tans_mode_e.
616 * @return none
617 */
hspi_xip_write_transmode(unsigned char wr_mode)618 static inline void hspi_xip_write_transmode(unsigned char wr_mode)
619 {
620 reg_hspi_xip_trans_mode &= (~FLD_HSPI_XIP_WR_TRANS_MODE);
621 reg_hspi_xip_trans_mode |= wr_mode & FLD_HSPI_XIP_WR_TRANS_MODE;
622 }
623
624 /**
625 * @brief This function enable address phase.
626 * @return none
627 */
hspi_addr_en(void)628 static inline void hspi_addr_en(void)
629 {
630 BM_SET(reg_hspi_xip_ctrl, FLD_HSPI_ADDR_EN);
631 }
632
633 /**
634 * @brief This function disable address phase.
635 * @return none
636 */
hspi_addr_dis(void)637 static inline void hspi_addr_dis(void)
638 {
639 BM_CLR(reg_hspi_xip_ctrl, FLD_HSPI_ADDR_EN);
640 }
641
642 /**
643 * @brief This function servers to set hspi address length.
644 * @param[in] len - 2'b00:1bye 2'b01:2bytes 2'b10:3bytes 2'b11:4bytes
645 * @return none
646 */
hspi_set_addr_len(unsigned char len)647 static inline void hspi_set_addr_len(unsigned char len)
648 {
649 reg_hspi_xip_ctrl |= ((len - 1) & 0x3) << 2;
650 }
651
652 /**
653 * @brief This function servers to enable xip sequential mode.
654 * @return none
655 */
hspi_xip_seq_mode_en(void)656 static inline void hspi_xip_seq_mode_en(void)
657 {
658 BM_SET(reg_hspi_xip_ctrl, FLD_HSPI_XIP_MODE);
659 }
660
661 /**
662 * @brief This function servers to disable xip sequential mode.
663 * @return none
664 */
hspi_xip_seq_mode_dis(void)665 static inline void hspi_xip_seq_mode_dis(void)
666 {
667 BM_CLR(reg_hspi_xip_ctrl, FLD_HSPI_XIP_MODE);
668 }
669
670 /**
671 * @brief This function servers to enable xip.
672 * @return none
673 */
hspi_xip_en(void)674 static inline void hspi_xip_en(void)
675 {
676 BM_SET(reg_hspi_xip_ctrl, FLD_HSPI_XIP_ENABLE);
677 }
678
679 /**
680 * @brief This function servers to disable xip.
681 * @return none
682 */
hspi_xip_dis(void)683 static inline void hspi_xip_dis(void)
684 {
685 BM_CLR(reg_hspi_xip_ctrl, FLD_HSPI_XIP_ENABLE);
686 }
687
688 /**
689 * @brief This function servers to stop xip.
690 * @return none
691 */
hspi_xip_stop(void)692 static inline void hspi_xip_stop(void)
693 {
694 BM_SET(reg_hspi_xip_ctrl, FLD_HSPI_XIP_STOP);
695 }
696
697 /**
698 * @brief This function servers to enable xip timeout that set hight level.
699 * @return none
700 */
hspi_xip_timeout_mode_en(void)701 static inline void hspi_xip_timeout_mode_en(void)
702 {
703 BM_SET(reg_hspi_xip_ctrl, FLD_HSPI_XIP_TIMEOUT_MODE);
704 }
705
706 /**
707 * @brief This function servers to disable xip timeout.
708 * @return none
709 */
hspi_xip_timeout_mode_dis(void)710 static inline void hspi_xip_timeout_mode_dis(void)
711 {
712 BM_CLR(reg_hspi_xip_ctrl, FLD_HSPI_XIP_TIMEOUT_MODE);
713 }
714
715 /**
716 * @brief This function servers to set xip timeout cnt,
717 * when two data frame intervals exceed spi_clock_out_period*timeout_cnt,cs will set high level.
718 * @param[in] cnt - xip timeout cnt.
719 * @return none
720 */
hspi_xip_timeout_cnt(unsigned char cnt)721 static inline void hspi_xip_timeout_cnt(unsigned char cnt)
722 {
723 reg_hspi_xip_timeout_cnt = cnt & 0xff;
724 }
725
726 /**
727 * @brief This function servers to set page_size.
728 * @param[in] page_size_i - page boundary 2^page_size_i bytes.
729 * @return none
730 */
hspi_xip_page_size(unsigned char page_size_i)731 static inline void hspi_xip_page_size(unsigned char page_size_i)
732 {
733 reg_hspi_page_size = page_size_i;
734 }
735
736 /**
737 * @brief This function servers to reply master slave is ready. When slave is ready,
738 * slave ready reply a byte data:0x5a. Indicating that slave is ready for data transmission.
739 * @param[in] spi_sel - the spi module.
740 * @return none
741 */
spi_slave_ready_en(spi_sel_e spi_sel)742 static inline void spi_slave_ready_en(spi_sel_e spi_sel)
743 {
744 BM_SET(reg_spi_status(spi_sel), FLD_HSPI_SLAVE_READY);
745 }
746
747 /**
748 * @brief This function servers to reply master slave is not ready.
749 * Slave reply a byte data: 0x00.indicating that slave is not ready for data transmission.
750 * @param[in] spi_sel - the spi module.
751 * @return none
752 */
spi_slave_ready_dis(spi_sel_e spi_sel)753 static inline void spi_slave_ready_dis(spi_sel_e spi_sel)
754 {
755 BM_CLR(reg_spi_status(spi_sel), FLD_HSPI_SLAVE_READY);
756 }
757
758 /**
759 * @brief This function servers to read cmd from master for slave.
760 * @param[in] spi_sel - the spi module.
761 * @return cmd transferd by master.
762 */
spi_slave_get_cmd(spi_sel_e spi_sel)763 static inline unsigned char spi_slave_get_cmd(spi_sel_e spi_sel)
764 {
765 return reg_spi_trans1(spi_sel);
766 }
767
768 /**
769 * @brief The function of this API is to set the number of bytes to triggered the receive and transmit interrupt.
770 * Its default value is 4. recommend setting 4.
771 * @param[in] spi_sel - the spi module.
772 * @param[in] cnt - the interrupt trigger level.
773 * @return none
774 */
spi_rx_tx_irq_trig_cnt(spi_sel_e spi_sel,unsigned char cnt)775 static inline void spi_rx_tx_irq_trig_cnt(spi_sel_e spi_sel, unsigned char cnt)
776 {
777 BM_CLR(reg_spi_status(spi_sel), FLD_HSPI_FIFO_THRES);
778 reg_spi_status(spi_sel) |= ((cnt & 7) << 4);
779 }
780
781 /**
782 * @brief This function servers to get irq status.
783 * @param[in] spi_sel - the spi module.
784 * @param[in] status - the irq status.
785 * @return - the value of status is be set.
786 */
spi_get_irq_status(spi_sel_e spi_sel,spi_irq_status_e status)787 static inline unsigned char spi_get_irq_status(spi_sel_e spi_sel, spi_irq_status_e status)
788 {
789 return reg_spi_irq_state(spi_sel) & status;
790 }
791
792 /**
793 * @brief This function servers to clear irq status.
794 * @param[in] spi_sel - the spi module.
795 * @param[in] status - the irq status.
796 * @return none.
797 */
spi_clr_irq_status(spi_sel_e spi_sel,spi_irq_status_e status)798 static inline void spi_clr_irq_status(spi_sel_e spi_sel, spi_irq_status_e status)
799 {
800 reg_spi_irq_state(spi_sel) = status;
801 }
802
803 /**
804 * @brief This function servers to set irq mask.
805 * @param[in] spi_sel - the spi module.
806 * @param[in] mask - the irq mask.
807 * @return cmd - transferd by master.
808 */
spi_set_irq_mask(spi_sel_e spi_sel,spi_irq_mask mask)809 static inline void spi_set_irq_mask(spi_sel_e spi_sel, spi_irq_mask mask)
810 {
811 BM_SET(reg_spi_trans2(spi_sel), mask);
812 }
813
814 /**
815 * @brief This function servers to clear irq mask.
816 * @param[in] spi_sel - the spi module.
817 * @param[in] mask - the irq mask.
818 * @return cmd - transferd by master.
819 */
spi_clr_irq_mask(spi_sel_e spi_sel,spi_irq_mask mask)820 static inline void spi_clr_irq_mask(spi_sel_e spi_sel, spi_irq_mask mask)
821 {
822 BM_CLR(reg_spi_trans2(spi_sel), mask);
823 }
824
825 /**
826 * @brief This function enable 3line_dcx module which is use for panel(lcd oled..).
827 * @return none
828 */
hspi_3line_dcx_en(void)829 static inline void hspi_3line_dcx_en(void)
830 {
831 BM_SET(reg_hspi_panel_ctrl, FLD_HSPI_PANEL_3LINE_DCX_EN);
832 }
833
834 /**
835 * @brief This function disable 3line_dcx module which is use for panel(lcd oled..).
836 * @return none
837 */
hspi_3line_dcx_dis(void)838 static inline void hspi_3line_dcx_dis(void)
839 {
840 BM_CLR(reg_hspi_panel_ctrl, FLD_HSPI_PANEL_3LINE_DCX_EN);
841 }
842
843 /**
844 * @brief This function set 3line_dcx translate data.
845 * @return none
846 */
hspi_set_3line_dcx_data(void)847 static inline void hspi_set_3line_dcx_data(void)
848 {
849 BM_SET(reg_hspi_panel_ctrl, FLD_HSPI_PANEL_3LINE_DCX);
850 }
851
852 /**
853 * @brief This function set 3line_dcx translate command.
854 * @return none
855 */
hspi_set_3line_dcx_cmd(void)856 static inline void hspi_set_3line_dcx_cmd(void)
857 {
858 BM_CLR(reg_hspi_panel_ctrl, FLD_HSPI_PANEL_3LINE_DCX);
859 }
860
861 /**
862 * @brief This function set 2data_lane mode for panel.
863 * @return none
864 */
hspi_set_panel_2data_lane_mode(hspi_panel_2data_lane_mode_e mode)865 static inline void hspi_set_panel_2data_lane_mode(hspi_panel_2data_lane_mode_e mode)
866 {
867 reg_hspi_panel_ctrl &= (~FLD_HSPI_PANEL_2DATA_LANE);
868 reg_hspi_panel_ctrl |= (mode & 0xf) << 2;
869 }
870
871 /**
872 * @brief This function selects pin for hspi master or slave.
873 * @return none
874 */
875 void spi_slave_set_pin(void);
876 /**
877 * @brief This function configures hspi pin.
878 * @param[in] config - the pointer of pin config struct.
879 * @return none
880 */
881 void hspi_set_pin(hspi_pin_config_t *config);
882
883 /**
884 * @brief This function configures pspi pin.
885 * @param[in] config - the pointer of pin config struct.
886 * @return none
887 */
888 void pspi_set_pin(pspi_pin_config_t *config);
889
890 /**
891 * @brief This function enable hspi csn pin.
892 * @param[in] pin - the csn pin.
893 * @return none
894 */
895 void hspi_cs_pin_en(hspi_csn_pin_def_e pin);
896
897 /**
898 * @brief This function disable hspi csn pin.
899 * @param[in] pin - the csn pin.
900 * @return none
901 */
902 void hspi_cs_pin_dis(hspi_csn_pin_def_e pin);
903
904 /**
905 * @brief This function change hspi csn pin.
906 * @param[in] next_csn_pin - the next csn pin.
907 * @return next_csn_pin - the next csn pin.
908 */
909 hspi_csn_pin_def_e hspi_change_csn_pin(hspi_csn_pin_def_e next_csn_pin);
910 /**
911 * @brief This function enable pspi csn pin.
912 * @param[in] pin - the csn pin.
913 * @return none
914 */
915 void pspi_cs_pin_en(pspi_csn_pin_def_e pin);
916
917 /**
918 * @brief This function disable pspi csn pin.
919 * @param[in] pin - the csn pin.
920 * @return none
921 */
922 void pspi_cs_pin_dis(pspi_csn_pin_def_e pin);
923
924 /**
925 * @brief This function change pspi csn pin.
926 * @param[in] next_csn_pin - the next csn pin.
927 * @return next_csn_pin - the next csn pin.
928 */
929 pspi_csn_pin_def_e pspi_change_csn_pin(pspi_csn_pin_def_e next_csn_pin);
930 /**
931 * @brief This function configures the clock and working mode for SPI interface.
932 * @param[in] spi_sel - the spi module.
933 * @param[in] div_clock - the division factor for SPI module.
934 * spi_clock_out = ahb_clock / ((div_clock+1)*2)
935 * @param[in] mode - the selected working mode of SPI module.
936 * bit5:CPHA-Clock Polarity ; bit6:CPOL:CPHA-Clock Phase
937 * MODE0: CPHA = 0, CPOL = 0;
938 * MODE1: CPHA = 0, CPOL = 1;
939 * MODE2: CPHA = 1, CPOL = 0;
940 * MODE3: CPHA = 1, CPOL = 1;
941 * @return none
942 */
943 void spi_master_init(spi_sel_e spi_sel, unsigned char div_clock, spi_mode_type_e mode);
944
945 /**
946 * @brief This function configures the clock and working mode for SPI interface.
947 * @param[in] spi_sel - the spi module.
948 * @param[in] mode - the selected working mode of SPI module.
949 * bit5:CPHA-Clock Polarity ; bit6:CPOL:CPHA-Clock Phase
950 * MODE0: CPHA = 0, CPOL = 0;
951 * MODE1: CPHA = 0, CPOL = 1;
952 * MODE2: CPHA = 1, CPOL = 0;
953 * MODE3: CPHA = 1, CPOL = 1;
954 * @return none
955 * @note spi_clock_in (spi_slave_clock frequency)/3
956 */
957 void spi_slave_init(spi_sel_e spi_sel, spi_mode_type_e mode);
958
959 /**
960 * @brief This function servers to set dummy cycle cnt.
961 * @param[in] spi_sel - the spi module.
962 * @param[in] dummy_cnt - the cnt of dummy clock.
963 * @return none
964 */
965 void spi_set_dummy_cnt(spi_sel_e spi_sel, unsigned char dummy_cnt);
966
967 /**
968 * @brief This function servers to set slave address hspi only.
969 * @param[in] addr - address of slave.
970 * @return none
971 */
972 void hspi_set_address(unsigned int addr);
973
974 /**
975 * @brief This function servers to set spi transfer mode.
976 * @param[in] spi_sel - the spi module.
977 * @param[in] mode - transfer mode.
978 * @return none
979 */
980 void spi_set_transmode(spi_sel_e spi_sel, spi_tans_mode_e mode);
981
982 /**
983 * @brief This function servers to set normal mode.
984 * @param[in] spi_sel - the spi module.
985 * @return none
986 */
987 void spi_set_normal_mode(spi_sel_e spi_sel);
988
989 /**
990 * @brief This function servers to set dual mode.
991 * @param[in] spi_sel - the spi module.
992 * @return none
993 */
994 void spi_set_dual_mode(spi_sel_e spi_sel);
995
996 /**
997 * @brief This function servers to set quad mode.
998 * @return none
999 */
1000 void hspi_set_quad_mode(void);
1001
1002 /**
1003 * @brief This function servers to set 3line mode.
1004 * @param[in] spi_sel - the spi module.
1005 * @return none
1006 */
1007 void spi_set_3line_mode(spi_sel_e spi_sel);
1008
1009 /**
1010 * @brief This function servers to set hspi io mode.
1011 * @param[in] spi_sel - the spi module.
1012 * @param[in] mode - single/dual/quad /3line.
1013 * @return none
1014 */
1015 void spi_set_io_mode(spi_sel_e spi_sel, spi_io_mode_e mode);
1016
1017 /**
1018 * @brief This function servers to config normal mode.
1019 * @param[in] spi_sel - the spi module.
1020 * @param[in] mode - nomal ,mode 3line.
1021 * @return none
1022 */
1023 void spi_master_config(spi_sel_e spi_sel, spi_nomal_3line_mode_e mode);
1024
1025 /**
1026 * @brief This function servers to config hspi special mode.
1027 * @param[in] config - the pointer of pin special config struct.
1028 * @return none
1029 */
1030 void hspi_master_config_plus(hspi_config_t *config);
1031
1032 /**
1033 * @brief This function servers to config pspi special mode.
1034 * @param[in] config - the pointer of pin special config struct.
1035 * @return none
1036 */
1037 void pspi_master_config_plus(pspi_config_t *config);
1038
1039 /**
1040 * @brief This function servers to write hspi fifo.
1041 * @param[in] spi_sel - the spi module.
1042 * @param[in] data - the pointer to the data for write.
1043 * @param[in] len - write length.
1044 * @return none
1045 */
1046 void spi_write(spi_sel_e spi_sel, unsigned char *data, unsigned int len);
1047
1048 /**
1049 * @brief This function servers to read hspi fifo.
1050 * @param[in] spi_sel - the spi module.
1051 * @param[in] data - the pointer to the data for read.
1052 * @param[in] len - write length.
1053 * @return none
1054 */
1055 void spi_read(spi_sel_e spi_sel, unsigned char *data, unsigned int len);
1056
1057 /**
1058 * @brief This function serves to normal write data in normal.
1059 * @param[in] spi_sel - the spi module.
1060 * @param[in] data - the pointer to the data for write.
1061 * @param[in] len - write length.
1062 * @return none
1063 */
1064 void spi_master_write(spi_sel_e spi_sel, unsigned char *data, unsigned int len);
1065
1066 /**
1067 * @brief This function serves to normal write and read data.
1068 * @param[in] spi_sel - the spi module.
1069 * @param[in] wr_data - the pointer to the data for write.
1070 * @param[in] wr_len - write length.
1071 * @param[in] rd_data - the pointer to the data for read.
1072 * @param[in] rd_len - read length.
1073 * @return none
1074 */
1075 void spi_master_write_read(spi_sel_e spi_sel, unsigned char *wr_data, unsigned int wr_len, unsigned char *rd_data,
1076 unsigned int rd_len);
1077
1078 /**
1079 * @brief This function serves to single/dual/quad write to the SPI slave.
1080 * @param[in] spi_sel - the spi module.
1081 * @param[in] cmd - cmd one byte will first write.
1082 * @param[in] addr - the address of slave.
1083 * @param[in] data - pointer to the data need to write.
1084 * @param[in] data_len - length in byte of the data need to write.
1085 * @param[in] wr_mode - write mode.dummy or not dummy.
1086 * @return none
1087 */
1088 void spi_master_write_plus(spi_sel_e spi_sel, unsigned char cmd, unsigned int addr, unsigned char *data,
1089 unsigned int data_len, spi_wr_tans_mode_e wr_mode);
1090
1091 /**
1092 * @brief This function serves to single/dual/quad read from the SPI slave.
1093 * @param[in] spi_sel - the spi module.
1094 * @param[in] cmd - cmd one byte will first write.
1095 * @param[in] addr - the address of slave.
1096 * @param[in] data - pointer to the data need to read.
1097 * @param[in] data_len - the length of data.
1098 * @param[in] rd_mode - read mode.dummy or not dummy.
1099 * @return none
1100 */
1101 void spi_master_read_plus(spi_sel_e spi_sel, unsigned char cmd, unsigned int addr, unsigned char *data,
1102 unsigned int data_len, spi_rd_tans_mode_e rd_mode);
1103
1104 /**
1105 * @brief This function serves to write address, then read data from the SPI slave.
1106 * @param[in] spi_sel - the spi module.
1107 * @param[in] cmd - cmd one byte will first write.
1108 * @param[in] addrs - pointer to the address of slave.
1109 * @param[in] addr_len - the length of address.
1110 * @param[in] data - the pointer to the data for read.
1111 * @param[in] data_len - read length.
1112 * @param[in] wr_mode - write mode.dummy or not dummy.
1113 * @return none
1114 */
1115 void spi_master_write_read_plus(spi_sel_e spi_sel, unsigned char cmd, unsigned char *addrs, unsigned int addr_len,
1116 unsigned char *data, unsigned int data_len, spi_rd_tans_mode_e wr_mode);
1117
1118 /**
1119 * @brief This function serves to set tx_dam channel and config dma tx default.
1120 * @param[in] chn - dma channel.
1121 * @return none
1122 */
1123 void hspi_set_tx_dma_config(dma_chn_e chn);
1124
1125 /**
1126 * @brief This function serves to set rx_dam channel and config dma rx default.
1127 * @param[in] chn - dma channel.
1128 * @return none
1129 */
1130 void hspi_set_rx_dma_config(dma_chn_e chn);
1131
1132 /**
1133 * @brief This function serves to set tx_dam channel and config dma tx default.
1134 * @param[in] chn - dma channel.
1135 * @return none
1136 */
1137 void pspi_set_tx_dma_config(dma_chn_e chn);
1138
1139 /**
1140 * @brief This function serves to set rx_dam channel and config dma rx default.
1141 * @param[in] chn - dma channel.
1142 * @return none
1143 */
1144 void pspi_set_rx_dma_config(dma_chn_e chn);
1145
1146 /**
1147 * @brief this function set spi dma channel.
1148 * @param[in] spi_dma_chn - dma channel.
1149 * @param[in] src_addr - the address of source.
1150 * @param[in] dst_addr - the address of destination.
1151 * @param[in] len - the length of data.
1152 * */
1153 void spi_set_dma(dma_chn_e spi_dma_chn, unsigned int src_addr, unsigned int dst_addr, unsigned int len);
1154
1155 /**
1156 * @brief this function set spi tx dma channel.
1157 * @param[in] spi_sel - the spi module.
1158 * @param[in] src_addr - the address of source.
1159 * @param[in] len - the length of data.
1160 * */
1161 _attribute_ram_code_sec_ void spi_set_tx_dma(spi_sel_e spi_sel, unsigned char *src_addr, unsigned int len);
1162
1163 /**
1164 * @brief this function set spi rx dma channel.
1165 * @param[in] spi_sel - the spi module.
1166 * @param[in] dst_addr - the address of destination.
1167 * @param[in] len - the length of data.
1168 * */
1169 _attribute_ram_code_sec_ void spi_set_rx_dma(spi_sel_e spi_sel, unsigned char *dst_addr, unsigned int len);
1170 /**
1171 * @brief This function serves to normal write data by dma.
1172 * @param[in] spi_sel - the spi module.
1173 * @param[in] src_addr - the pointer to the data for write.
1174 * @param[in] len - write length.
1175 * @return none
1176 */
1177 void spi_master_write_dma(spi_sel_e spi_sel, unsigned char *src_addr, unsigned int len);
1178
1179 /**
1180 * @brief This function serves to normal write cmd and address, then read data by dma.
1181 * @param[in] spi_sel - the spi module.
1182 * @param[in] addr - the pointer to the cmd and address for write.
1183 * @param[in] addr_len - write length.
1184 * @param[in] data - the pointer to the data for read.
1185 * @param[in] data_len - read length.
1186 * @return none
1187 */
1188 void spi_master_write_read_dma(spi_sel_e spi_sel, unsigned char *addr, unsigned int addr_len, unsigned char *data,
1189 unsigned int data_len);
1190
1191 /**
1192 * @brief This function serves to single/dual/quad write to the SPI slave by dma.
1193 * @param[in] spi_sel - the spi module.
1194 * @param[in] cmd - cmd one byte will first write.
1195 * @param[in] addr - the address of slave.
1196 * @param[in] data - pointer to the data need to write.
1197 * @param[in] data_len - length in byte of the data need to write.
1198 * @param[in] wr_mode - write mode.dummy or not dummy.
1199 * @return none
1200 */
1201 void spi_master_write_dma_plus(spi_sel_e spi_sel, unsigned char cmd, unsigned int addr, unsigned char *data,
1202 unsigned int data_len, spi_wr_tans_mode_e wr_mode);
1203
1204 /**
1205 * @brief This function serves to single/dual/quad read from the SPI slave by dma.
1206 * @param[in] spi_sel - the spi module.
1207 * @param[in] cmd - cmd one byte will first write.
1208 * @param[in] addr - the address of slave.
1209 * @param[in] dst_addr - pointer to the buffer that will cache the reading out data.
1210 * @param[in] data_len - length in byte of the data need to read.
1211 * @param[in] rd_mode - read mode.dummy or not dummy.
1212 * @return none
1213 */
1214 void spi_master_read_dma_plus(spi_sel_e spi_sel, unsigned char cmd, unsigned int addr, unsigned char *dst_addr,
1215 unsigned int data_len, spi_rd_tans_mode_e rd_mode);
1216
1217 /**
1218 * @brief This function serves to single/dual/quad write address and read from the SPI slave by dma.
1219 * @param[in] spi_sel - the spi module.
1220 * @param[in] cmd - cmd one byte will first write.
1221 * @param[in] addr - the address of slave.
1222 * @param[in] addr_len - the length of address.
1223 * @param[in] rd_data - pointer to the buffer that will cache the reading out data.
1224 * @param[in] rd_len - length in byte of the data need to read.
1225 * @param[in] rd_mode - read mode.dummy or not dummy.
1226 * @return none
1227 */
1228 void spi_master_write_read_dma_plus(spi_sel_e spi_sel, unsigned char cmd, unsigned char *addr, unsigned int addr_len,
1229 unsigned char *rd_data, unsigned int rd_len, spi_rd_tans_mode_e rd_mode);
1230
1231 /**
1232 * @brief This function serves to single/dual (quad) write to the SPI slave by xip.
1233 * @param[in] cmd - cmd one byte will first write.
1234 * @param[in] addr_offset - offset of xip base address.
1235 * @param[in] data - pointer to the data need to write.
1236 * @param[in] data_len - length in byte of the data need to write.
1237 * @param[in] wr_mode - write mode dummy or not dummy.
1238 * @return none
1239 */
1240 void hspi_master_write_xip(unsigned char cmd, unsigned int addr_offset, unsigned char *data, unsigned int data_len,
1241 spi_wr_tans_mode_e wr_mode);
1242
1243 /**
1244 * @brief This function serves to single/dual (quad) read from the SPI slave by xip.
1245 * @param[in] cmd - cmd one byte will first write.
1246 * @param[in] addr_offset - offset of xip base address.
1247 * @param[in] data - pointer to the data need to read.
1248 * @param[in] data_len - length in byte of the data need to read.
1249 * @param[in] rd_mode - read mode.dummy or not dummy.
1250 * @return none
1251 */
1252 void hspi_master_read_xip(unsigned char cmd, unsigned int addr_offset, unsigned char *data, unsigned int data_len,
1253 spi_rd_tans_mode_e rd_mode);
1254
1255 /**
1256 * @brief This function serves to a cmd and one data write to the SPI slave by xip.
1257 * @param[in] cmd - cmd one byte will first write.
1258 * @param[in] addr_offset - offset of xip base address.
1259 * @param[in] data_in - data need to write.
1260 * @param[in] wr_mode - write mode dummy or not dummy.
1261 * @return none
1262 */
1263 void hspi_master_write_xip_cmd_data(unsigned char cmd, unsigned int addr_offset, unsigned char data_in,
1264 spi_wr_tans_mode_e wr_mode);
1265
1266 #endif
1267