1 /****************************************************************************** 2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK") 3 * All rights reserved. 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 *****************************************************************************/ 18 #ifndef STACK_BLE_DEBUG_H_ 19 #define STACK_BLE_DEBUG_H_ 20 21 #ifndef DEBUG_PAIRING_ENCRYPTION 22 #define DEBUG_PAIRING_ENCRYPTION 0 23 #endif 24 25 /* BLE rf irq timing && log enable */ 26 #ifndef BLE_IRQ_DBG_EN 27 #define BLE_IRQ_DBG_EN 0 28 #endif 29 30 /* BLE Tx fifo log enable */ 31 #ifndef TX_FIFO_DBG_EN 32 #define TX_FIFO_DBG_EN 0 33 #endif 34 35 /* BLE smp trans.. log enable */ 36 #ifndef SMP_DBG_EN 37 #define SMP_DBG_EN 0 38 #endif 39 40 #ifndef TX_PUSH_DATA_LOG 41 #define TX_PUSH_DATA_LOG 0 42 #endif 43 44 #ifndef RX_L2CAP_DATA_LOG 45 #define RX_L2CAP_DATA_LOG 0 46 #endif 47 48 #ifndef SCHE_DEBUG_DUMP_EN 49 #define SCHE_DEBUG_DUMP_EN 0 50 #endif 51 52 #ifndef SCHE_TIMING_DEBUG_EN 53 #define SCHE_TIMING_DEBUG_EN 0 54 #endif 55 56 #ifndef DBG_BOUNDARY_RX 57 #define DBG_BOUNDARY_RX 0 58 #endif 59 60 #ifndef DBG_LL_CTRL_LOG_EN 61 #define DBG_LL_CTRL_LOG_EN 0 62 #endif 63 64 #ifndef DBG_DLE_DUMP_EN 65 #define DBG_DLE_DUMP_EN 0 66 #endif 67 68 #ifndef DBG_SCHE_TIMING_EN 69 #define DBG_SCHE_TIMING_EN 0 70 #endif 71 72 #ifndef DBG_IAL_EN 73 #define DBG_IAL_EN 0 74 #endif 75 76 #ifndef DEB_CIG_MST_EN 77 #define DEB_CIG_MST_EN 0 78 #endif 79 80 #ifndef DEB_CIG_SLV_EN 81 #define DEB_CIG_SLV_EN 0 82 #endif 83 84 #ifndef DEB_BIG_BCST_EN 85 #define DEB_BIG_BCST_EN 0 86 #endif 87 88 #ifndef DEB_BIG_SYNC_EN 89 #define DEB_BIG_SYNC_EN 0 90 #endif 91 92 #ifndef DEB_ISO_TEST_EN 93 #define DEG_ISO_TEST_EN 1 94 #endif 95 96 #ifndef DEB_STRUCT_BUFFER_SIZE_CHECK 97 #define DEB_STRUCT_BUFFER_SIZE_CHECK 1 98 #endif 99 100 #if (DBG_SLAVE_CONN_UPDATE) 101 #define SLET_upt_cmd_1 10 102 #define SLET_upt_cmd_2 11 103 #define SLET_upt_cmd_3 12 104 #define SLET_upt_cmd_4 13 105 #define SLET_upt_sync_1 20 106 #define SLET_upt_sync_2 21 107 #define SLET_upt_sync_3 22 108 #define SLET_upt_sync_4 23 109 #endif 110 111 #endif /* STACK_BLE_DEBUG_H_ */ 112