1 /* 2 * Copyright (c) 2022 Winner Microelectronics Co., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 /** 17 * @file wm_hspi.h 18 * 19 * 20 * @brief High speed spi slave Module 21 * 22 * @author dave 23 * 24 * Copyright (c) 2015 Winner Microelectronics Co., Ltd. 25 */ 26 27 #ifndef WM_HSPI_H 28 #define WM_HSPI_H 29 30 #include "wm_type_def.h" 31 #include "wm_ram_config.h" 32 33 #define HSPI_TX_MEM_MALLOC 0 /** tx mem dynamic malloc*/ 34 35 #define HSPI_INTERFACE_SPI 2 /** spi interface*/ 36 #define HSPI_INTERFACE_SDIO 3 /** sdio interface*/ 37 38 /**rx message*/ 39 #define HSPI_RX_CMD_MSG 1 40 #define HSPI_RX_DATA_MSG 2 41 42 /**spi/sdio buffer*/ 43 #define HSPI_TXBUF_NUM 2 44 #define HSPI_TX_DESC_NUM HSPI_TXBUF_NUM 45 #define HSPI_RXBUF_NUM 3 46 #define HSPI_RX_DESC_NUM HSPI_RXBUF_NUM 47 #define HSPI_TXBUF_SIZE 1500 48 #define HSPI_RXBUF_SIZE 1500 49 50 #define HSPI_TX_DESC_SIZE sizeof(struct tls_hspi_tx_desc) 51 #define HSPI_RX_DESC_SIZE sizeof(struct tls_hspi_rx_desc) 52 53 /***************************************************************************** 54 * sdio/hspi sram partition 55 ******************************************************************************/ 56 /* HSPI txbuf zone */ 57 #define HSPI_TXBUF_BASE_ADDR ((u32)(SLAVE_HSPI_SDIO_ADDR)) 58 59 #if HSPI_TX_MEM_MALLOC 60 #define HSPI_TXBUF_TOTAL_SIZE 0 61 #else 62 #define HSPI_TXBUF_TOTAL_SIZE (HSPI_TXBUF_SIZE * HSPI_TXBUF_NUM) 63 #endif 64 /** HSPI tx desc zone */ 65 #define HSPI_TX_DESC_BASE_ADDR ((u32)(HSPI_TXBUF_BASE_ADDR + HSPI_TXBUF_TOTAL_SIZE)) 66 #define HSPI_TX_DESC_TOTAL_SIZE (HSPI_TX_DESC_SIZE * HSPI_TX_DESC_NUM) // 28*3=84 67 /** HSPI rxbuf zone */ 68 #define HSPI_RXBUF_BASE_ADDR ((u32)(HSPI_TX_DESC_BASE_ADDR + HSPI_TX_DESC_TOTAL_SIZE)) 69 #define HSPI_RXBUF_TOTAL_SIZE (HSPI_RXBUF_NUM * HSPI_RXBUF_SIZE) // 4500 70 /** HSPI rx desc zone */ 71 #define HSPI_RX_DESC_BASE_ADDR ((u32)(HSPI_RXBUF_BASE_ADDR + HSPI_RXBUF_TOTAL_SIZE)) 72 #define HSPI_RX_DESC_TOTAL_SIZE (HSPI_RX_DESC_SIZE * HSPI_RX_DESC_NUM) // 36 73 74 #define SDIO_CIS_SIZE (0x80) 75 #define SDIO_CMD_RXBUF_SIZE 256 76 77 #define SDIO_CIS0_ADDR (HSPI_RX_DESC_BASE_ADDR + HSPI_RX_DESC_TOTAL_SIZE) // 128 78 #define SDIO_CIS1_ADDR (SDIO_CIS0_ADDR + SDIO_CIS_SIZE) // 128 79 #define SDIO_CMD_RXBUF_ADDR (SDIO_CIS1_ADDR + SDIO_CIS_SIZE) 80 81 #define CIS_FUN0_ADDR ((u32)SDIO_CIS0_ADDR) 82 #define CIS_FUN1_ADDR ((u32)SDIO_CIS1_ADDR) 83 84 #define FN0_TPL_FUNCID (CIS_FUN0_ADDR + 0x00) 85 #define FN0_TPL_FUNCE (CIS_FUN0_ADDR + 0x04) 86 #define FN0_TPL_FUNCE_MAXBLK (CIS_FUN0_ADDR + 0x08) 87 #define FN0_TPL_MANFID_MID (CIS_FUN0_ADDR + 0x0C) 88 #define FN0_TPL_END (CIS_FUN0_ADDR + 0x10) 89 90 #define FN1_TPL_FUNCID (CIS_FUN1_ADDR + 0x00) 91 #define FN1_TPL_FUNCE (CIS_FUN1_ADDR + 0x04) 92 #define FN1_TPL_FUNCE_VER (CIS_FUN1_ADDR + 0x08) 93 #define FN1_TPL_FUNCE_NSN (CIS_FUN1_ADDR + 0x0C) 94 #define FN1_TPL_FUNCE_CSASIZE (CIS_FUN1_ADDR + 0x10) 95 #define FN1_TPL_FUNCE_OCR (CIS_FUN1_ADDR + 0x14) 96 #define FN1_TPL_FUNCE_MINPWR (CIS_FUN1_ADDR + 0x18) 97 #define FN1_TPL_FUNCE_STANDBY (CIS_FUN1_ADDR + 0x1C) 98 #define FN1_TPL_FUNCE_OPTBW (CIS_FUN1_ADDR + 0x20) 99 #define FN1_TPL_FUNCE_NTIMEOUT (CIS_FUN1_ADDR + 0x24) 100 #define FN1_TPL_FUNCE_AVGPWR (CIS_FUN1_ADDR + 0x28) 101 #define FN1_TPL_END (CIS_FUN1_ADDR + 0x30) 102 103 /** SDIO interrupt bit definition */ 104 #define SDIO_WP_INT_SRC_CMD_DOWN (1UL<<3) 105 #define SDIO_WP_INT_SRC_CMD_UP (1UL<<2) 106 #define SDIO_WP_INT_SRC_DATA_DOWN (1UL<<1) 107 #define SDIO_WP_INT_SRC_DATA_UP (1UL<<0) 108 109 /** Definition of send data descriptor structure */ 110 struct tls_hspi_tx_desc { 111 volatile u32 valid_ctrl; 112 u32 buf_info; 113 u32 buf_addr[3]; 114 u32 next_desc_addr; 115 #if HSPI_TX_MEM_MALLOC 116 u32 txbuf_addr; /**< txbuf addr, pbuf and buf_addr[0] are different */ 117 #endif 118 }; 119 120 /** Definition of receive data descriptor structure */ 121 struct tls_hspi_rx_desc { 122 u32 valid_ctrl; 123 u32 buf_addr; 124 u32 next_desc_addr; 125 }; 126 127 /** struct tls_slave_hspi */ 128 struct tls_slave_hspi { 129 u8 ifusermode; 130 131 s16 (*rx_cmd_callback)(char *buf); 132 133 s16 (*rx_data_callback)(char *buf); 134 135 s16 (*tx_data_callback)(char *buf); 136 137 struct tls_hspi_tx_desc *curr_tx_desc; /**< Upstream data management */ 138 139 struct tls_hspi_rx_desc *curr_rx_desc; /**< Downlink data management */ 140 141 #if HSPI_TX_MEM_MALLOC 142 u8 txdoneflag; /**< tx done falg*/ 143 #endif 144 }; 145 146 /** 147 * @defgroup Driver_APIs Driver APIs 148 * @brief Driver APIs 149 */ 150 151 /** 152 * @addtogroup Driver_APIs 153 * @{ 154 */ 155 156 /** 157 * @defgroup HSPI_Driver_APIs HSPI Driver APIs 158 * @brief HSPI driver APIs 159 */ 160 161 /** 162 * @addtogroup HSPI_Driver_APIs 163 * @{ 164 */ 165 166 /** 167 * @brief This function is used to initial HSPI register. 168 * 169 * @param[in] None 170 * 171 * @retval 0 success 172 * @retval other failed 173 * 174 * @note When the system is initialized, the function has been called, so users can not call this function. 175 */ 176 int tls_slave_spi_init(void); 177 178 /** 179 * @brief This function is used to enable or disable user mode. 180 * 181 * @param[in] ifenable TRUE or FALSE 182 * 183 * @return None 184 * 185 * @note If the user enables the user mode, RICM instruction in the system will not be used by SPI. 186 * If the user wants to use the SPI interface as other use, need to enable the user mode. 187 * This function must be called before the register function. 188 */ 189 void tls_set_hspi_user_mode(u8 ifenable); 190 191 /** 192 * @brief This function is used to set high speed interface type. 193 * 194 * @param[in] type is the interface type. HSPI_INTERFACE_SPI or HSPI_INTERFACE_SDIO 195 * 196 * @return None 197 * 198 * @note None 199 */ 200 void tls_set_high_speed_interface_type(int type); 201 202 /** 203 * @brief This function is used to register hspi rx command interrupt. 204 * 205 * @param[in] rx_cmd_callback is the hspi rx interrupt call back function. 206 * 207 * @return None 208 * 209 * @note None 210 */ 211 void tls_hspi_rx_cmd_callback_register(s16 (*rx_cmd_callback)(char *buf)); 212 213 /** 214 * @brief This function is used to register hspi rx data interrupt. 215 * 216 * @param[in] rx_data_callback is the hspi rx interrupt call back function. 217 * 218 * @return None 219 * 220 * @note None 221 */ 222 void tls_hspi_rx_data_callback_register(s16 (*rx_data_callback)(char *buf)); 223 224 /** 225 * @brief This function is used to register hspi tx data interrupt. 226 * 227 * @param[in] tx_data_callback is the hspi tx interrupt call back function. 228 * 229 * @return None 230 * 231 * @note None 232 */ 233 void tls_hspi_tx_data_callback_register(s16 (*tx_data_callback)(char *buf)); 234 235 /** 236 * @brief This function is used to transfer data. 237 * 238 * @param[in] txbuf is a buf for saving user data. 239 * @param[in] len is the data length. 240 * 241 * @retval transfer data len success 242 * @retval 0 failed 243 * 244 * @note None 245 */ 246 int tls_hspi_tx_data(char *txbuf, int len); 247 248 /** 249 * @} 250 */ 251 252 /** 253 * @} 254 */ 255 256 #endif /* WM_HSPI_H */ 257