1/* 2 * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved. 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 /****************************************************************************** 17 * @file startup.S 18 * @brief startup file for smartl. Should use with 19 * GCC for CSKY Embedded Processors 20 * @version V1.0 21 * @date 02. June 2017 22 ******************************************************************************/ 23 24#include <csi_config.h> 25 26.section .vectors 27 .align 10 28 .globl __Vectors 29 .type __Vectors, @object 30__Vectors: 31 .long Reset_Handler 32 .long Default_Handler 33 .long Default_Handler 34 .long Default_Handler 35 .long Default_Handler 36 .long Default_Handler 37 .long Default_Handler 38 .long Default_Handler 39 .long Default_Handler 40 .long Default_Handler 41 .long Default_Handler 42 .long Default_Handler 43 .long Default_Handler 44 .long Default_Handler 45 .long Default_Handler 46 .long Default_Handler 47 .long Default_Handler 48 .long Default_Handler 49 .long Default_Handler 50 .long Default_Handler 51 .long Default_Handler 52 .long Default_Handler 53 .long tspend_handler 54 .long Default_Handler 55 .long Default_Handler 56 .long Default_Handler 57 .long Default_Handler 58 .long Default_Handler 59 .long Default_Handler 60 .long Default_Handler 61 .long Default_Handler 62 .long Default_Handler 63 64 /* External interrupts */ 65 .long SDIO_IRQHandler /* 0: SDIO */ 66 .long MAC_IRQHandler /* 1: MAC */ 67 .long RF_Cfg_IRQHandler /* 2: RF Cfg */ 68 .long SEC_IRQHandler /* 3: SEC */ 69 .long DMA_Channel0_IRQHandler /* 4: DMA_Channel0 */ 70 .long DMA_Channel1_IRQHandler /* 5: DMA_Channel1 */ 71 .long DMA_Channel2_IRQHandler /* 6: DMA_Channel2 */ 72 .long DMA_Channel3_IRQHandler /* 7: DMA_Channel3 */ 73 .long DMA_Channel4_7_IRQHandler /* 8: DMA_Channel4_7 */ 74 .long DMA_BRUST_IRQHandler /* 9: DMA_BRUST */ 75 .long I2C_IRQHandler /* 10: IIC */ 76 .long ADC_IRQHandler /* 11: SD ADC */ 77 .long SPI_LS_IRQHandler /* 12: LS SPI */ 78 .long SPI_HS_IRQHandler /* 13: HS SPI */ 79 .long GPIOA_IRQHandler /* 14: GPIOA */ 80 .long GPIOB_IRQHandler /* 15: GPIOB */ 81 .long USART_IRQHandler /* 16: UART0 */ 82 .long USART1_IRQHandler /* 17: UART1 */ 83 .long USART2_IRQHandler /* 18: UART2&7816 */ 84 .long USART3_5_IRQHandler /* 19: USART3_5 */ 85 .long BLE_IRQHandler /* 20: BLE */ 86 .long BT_IRQHandler /* 21: BT */ 87 .long PWM_IRQHandler /* 22: PWM */ 88 .long I2S_IRQHandler /* 23: I2S */ 89 .long SDIO_HOST_IRQHandler /* 24: SDIO HOST */ 90 .long CORET_IRQHandler /* 25: CoreTIM */ 91 .long RSA_IRQHandler /* 26: RSA */ 92 .long GPSEC_IRQHandler /* 27: GPSEC */ 93 .long FLASH_IRQHandler /* 28: Flash */ 94 .long PMU_IRQHandler /* 29: PMU */ 95 .long TIM0_5_IRQHandler /* 30: Timer0_5 */ 96 .long WDG_IRQHandler /* 31: Watch dog */ 97 98 .size __Vectors, . - __Vectors 99 100 .text 101 .align 2 102_start: 103 .text 104 .align 2 105 .globl Reset_Handler 106 .type Reset_Handler, %function 107Reset_Handler: 108#ifdef CONFIG_KERNEL_NONE 109 lrw r0, 0xe0000200 110#else 111 lrw r0, 0x80000200 112 mtcr r0, psr 113#endif 114 mtcr r0, psr 115 116 lrw r0, g_top_irqstack 117 mov sp, r0 118 119/* 120 * move __Vectors to irq_vectors 121 */ 122 lrw r1, __Vectors 123 lrw r2, __vdata_start__ 124 lrw r3, __vdata_end__ 125 126 subu r3, r2 127 cmpnei r3, 0 128 bf .L_loopv0_done 129 130.L_loopv0: 131 ldw r0, (r1, 0) 132 stw r0, (r2, 0) 133 addi r1, 4 134 addi r2, 4 135 subi r3, 4 136 cmpnei r3, 0 137 bt .L_loopv0 138 139.L_loopv0_done: 140 141/* 142 * The ranges of copy from/to are specified by following symbols 143 * __etext: LMA of start of the section to copy from. Usually end of text 144 * __data_start__: VMA of start of the section to copy to 145 * __data_end__: VMA of end of the section to copy to 146 * 147 * All addresses must be aligned to 4 bytes boundary. 148 */ 149 lrw r1, __erodata 150 lrw r2, __data_start__ 151 lrw r3, __data_end__ 152 153 subu r3, r2 154 cmpnei r3, 0 155 bf .L_loop0_done 156 157.L_loop0: 158 ldw r0, (r1, 0) 159 stw r0, (r2, 0) 160 addi r1, 4 161 addi r2, 4 162 subi r3, 4 163 cmpnei r3, 0 164 bt .L_loop0 165 166.L_loop0_done: 167 168/* 169 * The BSS section is specified by following symbols 170 * __bss_start__: start of the BSS section. 171 * __bss_end__: end of the BSS section. 172 * 173 * Both addresses must be aligned to 4 bytes boundary. 174 */ 175 #if 1 176 lrw r1, __bss_start__ 177 lrw r2, __bss_end__ 178 179 movi r0, 0 180 181 subu r2, r1 182 cmpnei r2, 0 183 bf .L_loop1_done 184 185.L_loop1: 186 stw r0, (r1, 0) 187 addi r1, 4 188 subi r2, 4 189 cmpnei r2, 0 190 bt .L_loop1 191.L_loop1_done: 192#endif 193 194#ifndef __NO_SYSTEM_INIT 195 jbsr SystemInit 196#endif 197 198#ifndef __NO_BOARD_INIT 199 jbsr board_init 200#endif 201 202 jbsr cxx_system_init 203 204 jbsr main 205 .size Reset_Handler, . - Reset_Handler 206 207__exit: 208 br __exit 209 210.section .bss 211 212 .align 2 213 .globl g_intstackalloc 214 .global g_intstackbase 215 .global g_top_irqstack 216 .global __init_stack_s 217g_intstackalloc: 218g_intstackbase: 219 .space CONFIG_ARCH_INTERRUPTSTACK 220g_top_irqstack: 221__init_stack_s: 222 223.section .vdata 224 .align 10 225 .globl irq_vectors 226 .type irq_vectors, @object 227irq_vectors: 228 .space CONFIG_IRQ_VECTOR_SIZE 229 .size irq_vectors, . - irq_vectors 230 231 .globl irq_vectors_end 232irq_vectors_end: 233