1 /*
2 * Copyright (c) 2022 Winner Microelectronics Co., Ltd. All rights reserved.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15
16 #include <string.h>
17 #include "wm_irq.h"
18 #include "wm_i2s.h"
19
20 #define FPGA_800_I2S 0
21 #define I2S_CLK 160000000
22 #define TEST_WITH_F401 0
23 #define APPEND_NUM 4
24
25 wm_i2s_buf_t wm_i2s_buf[1] = { 0 };
26 static uint8_t tx_channel = 0, rx_channel = 0;
27 static wm_dma_desc g_dma_desc_tx[2];
28 static wm_dma_desc g_dma_desc_rx[2];
29
30 // master or slave
wm_i2s_set_mode(bool bl)31 static void wm_i2s_set_mode(bool bl)
32 {
33 tls_bitband_write(HR_I2S_CTRL, 28, bl);
34 }
35
36 // master or slave
wm_i2s_get_mode(void)37 static uint32_t wm_i2s_get_mode(void)
38 {
39 uint32_t reg;
40
41 reg = tls_reg_read32(HR_I2S_CTRL);
42 reg = reg>>28;
43
44 return (reg & 0x1);
45 }
46
47 // i2s_stardard
wm_i2s_set_format(uint32_t format)48 static void wm_i2s_set_format(uint32_t format)
49 {
50 uint32_t reg;
51 reg = tls_reg_read32(HR_I2S_CTRL);
52 reg &= ~(0x3<<24);
53 reg |= format;
54 tls_reg_write32(HR_I2S_CTRL, reg);
55 }
56
wm_i2s_left_channel_sel(bool bl)57 static void wm_i2s_left_channel_sel(bool bl)
58 {
59 tls_bitband_write(HR_I2S_CTRL, 23, bl);
60 }
61
wm_i2s_mono_select(bool bl)62 static void wm_i2s_mono_select(bool bl)
63 {
64 tls_bitband_write(HR_I2S_CTRL, 22, bl);
65 }
66
wm_i2s_rx_dma_enable(bool bl)67 static void wm_i2s_rx_dma_enable(bool bl)
68 {
69 tls_bitband_write(HR_I2S_CTRL, 21, bl);
70 }
71
wm_i2s_tx_dma_enable(bool bl)72 static void wm_i2s_tx_dma_enable(bool bl)
73 {
74 tls_bitband_write(HR_I2S_CTRL, 20, bl);
75 }
76
wm_i2s_rx_fifo_clear(void)77 static void wm_i2s_rx_fifo_clear(void)
78 {
79 tls_bitband_write(HR_I2S_CTRL, 19, 1);
80 }
81
wm_i2s_tx_fifo_clear(void)82 static void wm_i2s_tx_fifo_clear(void)
83 {
84 tls_bitband_write(HR_I2S_CTRL, 18, 1);
85 }
86
wm_i2s_set_rxth(uint8_t th)87 static void wm_i2s_set_rxth(uint8_t th)
88 {
89 uint32_t reg;
90
91 if (th > 7) {
92 th = 7;
93 }
94 reg = tls_reg_read32(HR_I2S_CTRL);
95 reg &= ~(0x7<<12);
96 reg |= (th << 12);
97 tls_reg_write32(HR_I2S_CTRL, reg);
98 }
99
wm_i2s_set_txth(uint8_t th)100 static void wm_i2s_set_txth(uint8_t th)
101 {
102 uint32_t reg;
103
104 if (th > 7) {
105 th = 7;
106 }
107 reg = tls_reg_read32(HR_I2S_CTRL);
108 reg &= ~(0x7<<9);
109 reg |= (th << 9);
110 tls_reg_write32(HR_I2S_CTRL, reg);
111 }
112
wm_i2s_set_word_len(uint8_t len)113 static void wm_i2s_set_word_len(uint8_t len)
114 {
115 uint32_t reg;
116
117 reg = tls_reg_read32(HR_I2S_CTRL);
118 reg &= ~(0x3<<4);
119 len = (len>>3) - 1;
120 reg |= (len<<4);
121 tls_reg_write32(HR_I2S_CTRL, reg);
122 }
123
wm_i2s_rx_enable(bool bl)124 void wm_i2s_rx_enable(bool bl)
125 {
126 tls_bitband_write(HR_I2S_CTRL, 2, bl);
127 }
128
wm_i2s_tx_enable(bool bl)129 void wm_i2s_tx_enable(bool bl)
130 {
131 tls_bitband_write(HR_I2S_CTRL, 1, bl);
132 }
133
wm_i2s_enable(bool bl)134 static void wm_i2s_enable(bool bl)
135 {
136 tls_bitband_write(HR_I2S_CTRL, 0, bl);
137 }
138
wm_i2s_txth_int_mask(bool bl)139 static void wm_i2s_txth_int_mask(bool bl)
140 {
141 tls_bitband_write(HR_I2S_INT_MASK, 6, bl);
142 }
143
wm_i2s_rxth_int_mask(bool bl)144 static void wm_i2s_rxth_int_mask(bool bl)
145 {
146 tls_bitband_write(HR_I2S_INT_MASK, 2, bl);
147 }
148
wm_i2s_set_freq(uint32_t lr_freq,uint32_t mclk)149 static void wm_i2s_set_freq(uint32_t lr_freq, uint32_t mclk)
150 {
151 uint32_t div, mclk_div;
152 uint32_t temp;
153 uint8_t wdwidth, stereo;
154
155 temp = I2S->CTRL;
156 wdwidth = (((temp>>4)&0x03)+1)<<3;
157 stereo = tls_bitband_read(HR_I2S_CTRL, 22) ? 1:2;
158 stereo = 2;
159 div = (I2S_CLK + lr_freq * wdwidth * stereo)/(lr_freq * wdwidth * stereo) - 1;
160
161 #if FPGA_800_I2S
162 div = div/2;
163 #endif
164 if (mclk == 0) {
165 }
166 mclk_div = I2S_CLK / mclk;
167
168 if (mclk_div > 0x3F) {
169 mclk_div = 0x3F;
170 }
171
172 *(volatile uint32_t *)HR_CLK_I2S_CTL &= ~0x3FFFF;
173 // set bclk div ,mclk div, inter clk be used, mclk enabled.
174 *(volatile uint32_t *)HR_CLK_I2S_CTL |= (uint32_t)((div<<8) | (mclk_div<<2) | 2);
175 }
176
wm_i2s_int_clear_all(void)177 static void wm_i2s_int_clear_all(void)
178 {
179 tls_reg_write32(HR_I2S_INT_SRC, 0x3FF);
180 }
181
wm_i2s_int_mask_all(void)182 static void wm_i2s_int_mask_all(void)
183 {
184 tls_reg_write32(HR_I2S_INT_MASK, 0x3FF);
185 }
186
wm_i2s_dma_start(uint8_t ch)187 static void wm_i2s_dma_start(uint8_t ch)
188 {
189 DMA_CHNLCTRL_REG(ch) = DMA_CHNL_CTRL_CHNL_ON;
190 }
191
wm_i2s_module_reset(void)192 static void wm_i2s_module_reset(void)
193 {
194 tls_bitband_write(HR_CLK_RST_CTL, 24, 0);
195 tls_bitband_write(HR_CLK_RST_CTL, 24, 1);
196 }
197
wm_i2s_dma_tx_init(uint8_t ch,uint32_t count,int16_t * buf)198 static void wm_i2s_dma_tx_init(uint8_t ch, uint32_t count, int16_t *buf)
199 {
200 DMA_INTMASK_REG &= ~(0x02<<(ch*2));
201 DMA_SRCADDR_REG(ch) = (uint32_t)buf;
202 DMA_DESTADDR_REG(ch) = HR_I2S_TX;
203
204 DMA_CTRL_REG(ch) = DMA_CTRL_SRC_ADDR_INC | DMA_CTRL_DATA_SIZE_WORD | DMA_CTRL_BURST_SIZE1;
205 DMA_MODE_REG(ch) = DMA_MODE_SEL_I2S_TX | DMA_MODE_HARD_MODE;
206 DMA_CTRL_REG(ch) &= ~0xFFFF00;
207 DMA_CTRL_REG(ch) |= (count<<8);
208 }
209
wm_i2s_dma_rx_init(uint8_t ch,uint32_t count,int16_t * buf)210 static void wm_i2s_dma_rx_init(uint8_t ch, uint32_t count, int16_t * buf)
211 {
212 DMA_INTMASK_REG &=~(0x02<<(ch*2));
213 DMA_SRCADDR_REG(ch) = HR_I2S_RX;
214 DMA_DESTADDR_REG(ch) = (uint32_t)buf;
215
216 DMA_CTRL_REG(ch) = DMA_CTRL_DEST_ADDR_INC | DMA_CTRL_DATA_SIZE_WORD | DMA_CTRL_BURST_SIZE1;
217 DMA_MODE_REG(ch) = DMA_MODE_SEL_I2S_RX | DMA_MODE_HARD_MODE;
218 DMA_CTRL_REG(ch) &= ~0xFFFF00;
219 DMA_CTRL_REG(ch) |= (count<<8);
220 }
221
i2s_I2S_IRQHandler(void)222 ATTRIBUTE_ISR void i2s_I2S_IRQHandler(void)
223 {
224 volatile uint32_t temp;
225 csi_kernel_intrpt_enter();
226 /* TxTH */
227 if ((M32(HR_I2S_INT_SRC) >> 6) & 0x1) { // 6:byte alignment
228 if (wm_i2s_buf->txtail < wm_i2s_buf->txlen) {
229 volatile uint8_t fifo_level;
230 for (fifo_level = ((I2S->INT_STATUS >> 4) & 0x0F), // 4:byte alignment
231 temp = 0; temp < 8 - fifo_level; temp++) { // 8:byte alignment
232 tls_reg_write32(HR_I2S_TX, wm_i2s_buf->txbuf[wm_i2s_buf->txtail++]);
233 if (wm_i2s_buf->txtail >= wm_i2s_buf->txlen) {
234 wm_i2s_buf->txtail = 0;
235 wm_i2s_buf->txdata_done = 1;
236 tls_bitband_write(HR_I2S_INT_MASK, 6, 1); // 6:value of bit
237 break;
238 }
239 }
240 }
241 tls_reg_write32(HR_I2S_INT_SRC, 0x40);
242 }
243 /* LZC */
244 if (tls_bitband_read(HR_I2S_INT_SRC, 9)) { // 9:value of bit
245 tls_reg_write32(HR_I2S_INT_SRC, 0x200);
246 }
247 /* RZC */
248 if (tls_bitband_read(HR_I2S_INT_SRC, 8)) { // 8:value of bit
249 tls_reg_write32(HR_I2S_INT_SRC, 0x100);
250 }
251 /* Tx Done */
252 if (tls_bitband_read(HR_I2S_INT_SRC, 7)) { // 7:value of bit
253 tls_reg_write32(HR_I2S_INT_SRC, 0x80);
254 }
255 /* TXOV */
256 if (tls_bitband_read(HR_I2S_INT_SRC, 5)) { // 5:value of bit
257 tls_reg_write32(HR_I2S_INT_SRC, 0x20);
258 }
259 /* TXUD */
260 if (tls_bitband_read(HR_I2S_INT_SRC, 4)) { // 4:value of bit
261 tls_reg_write32(HR_I2S_INT_SRC, 0x10);
262 }
263 /* Rx Done */
264 if (tls_bitband_read(HR_I2S_INT_SRC, 3)) { // 3:value of bit
265 tls_reg_write32(HR_I2S_INT_SRC, 0x08);
266 }
267 /* RxTH */
268 if (tls_bitband_read(HR_I2S_INT_SRC, 2)) { // 2:value of bit
269 volatile uint8_t cnt;
270 for (cnt = (I2S->INT_STATUS & 0x0F), temp = 0; temp < cnt; temp++) {
271 if (wm_i2s_buf->rxhead < wm_i2s_buf->rxlen) {
272 wm_i2s_buf->rxbuf[wm_i2s_buf->rxhead++] = I2S->RX;
273 if (wm_i2s_buf->rxhead >= wm_i2s_buf->rxlen) {
274 wm_i2s_buf->rxhead = 0;
275 wm_i2s_buf->rxdata_ready = 1;
276 tls_bitband_write(HR_I2S_INT_MASK, 2, 1); // 2:value of bit
277 break;
278 }
279 }
280 }
281 tls_reg_write32(HR_I2S_INT_SRC, 0x04);
282 }
283 /* RXOV */
284 if (tls_bitband_read(HR_I2S_INT_SRC, 1)) {
285 tls_reg_write32(HR_I2S_INT_SRC, 0x02);
286 }
287 /* RXUD */
288 if (tls_bitband_read(HR_I2S_INT_SRC, 0)) {
289 tls_reg_write32(HR_I2S_INT_SRC, 0x01);
290 }
291 csi_kernel_intrpt_exit();
292 }
293
i2s_DMA_TX_Channel_IRQHandler(void * p)294 void i2s_DMA_TX_Channel_IRQHandler(void *p)
295 {
296 wm_dma_handler_type *hdma = (wm_dma_handler_type *)p;
297 wm_dma_desc *dma_desc = &g_dma_desc_tx[0];
298 if (p) {
299 if (wm_i2s_buf->txdata_done) {
300 wm_i2s_buf->txdata_done = 0;
301 dma_desc[1].valid |= (1 << 31);
302 if (hdma->XferCpltCallback) {
303 hdma->XferCpltCallback(hdma);
304 }
305 } else {
306 wm_i2s_buf->txdata_done = 1;
307 dma_desc[0].valid |= (1 << 31);
308 if (hdma->XferHalfCpltCallback) {
309 hdma->XferHalfCpltCallback(hdma);
310 }
311 }
312 } else {
313 wm_i2s_buf->txdata_done = 1;
314 }
315 }
316
i2s_DMA_RX_Channel_IRQHandler(void * p)317 void i2s_DMA_RX_Channel_IRQHandler(void *p)
318 {
319 wm_dma_handler_type *hdma = (wm_dma_handler_type *)p;
320 wm_dma_desc *dma_desc = &g_dma_desc_rx[0];
321 if (p) {
322 if (wm_i2s_buf->rxdata_ready) {
323 wm_i2s_buf->rxdata_ready = 0;
324 dma_desc[1].valid |= (1 << 31);
325 if (hdma->XferCpltCallback) {
326 hdma->XferCpltCallback(hdma);
327 }
328 } else {
329 wm_i2s_buf->rxdata_ready = 1;
330 dma_desc[0].valid |= (1 << 31);
331 if (hdma->XferHalfCpltCallback) {
332 hdma->XferHalfCpltCallback(hdma);
333 }
334 }
335 } else {
336 wm_i2s_buf->rxdata_ready = 1;
337 }
338 }
339
wm_i2s_register_callback(tls_i2s_callback callback)340 void wm_i2s_register_callback(tls_i2s_callback callback)
341 {
342 wm_i2s_buf->tx_callback = callback;
343 }
344
wm_i2s_port_init(I2S_InitDef * opts)345 int wm_i2s_port_init(I2S_InitDef *opts)
346 {
347 I2S_InitDef opt = { I2S_MODE_MASTER, I2S_CTRL_STEREO, I2S_RIGHT_CHANNEL, I2S_Standard, \
348 I2S_DataFormat_16, 8000, 5000000 };
349
350 if (opts != NULL) {
351 memcpy_s(&opt, sizeof(opt), opts, sizeof(I2S_InitDef));
352 }
353
354 wm_i2s_module_reset();
355
356 tls_reg_write32(HR_I2S_CTRL, 0);
357 wm_i2s_set_mode(opt.I2S_Mode_MS);
358 wm_i2s_int_clear_all();
359 wm_i2s_int_mask_all();
360
361 wm_i2s_mono_select(opt.I2S_Mode_SS);
362 wm_i2s_left_channel_sel(opt.I2S_Mode_LR);
363 wm_i2s_set_format(opt.I2S_Trans_STD);
364 wm_i2s_set_word_len(opt.I2S_DataFormat);
365 wm_i2s_set_freq(opt.I2S_AudioFreq, opt.I2S_MclkFreq);
366 wm_i2s_set_txth(4);
367 wm_i2s_set_rxth(4);
368
369 return WM_SUCCESS;
370 }
371
wm_i2s_tx_rx_stop(void)372 void wm_i2s_tx_rx_stop(void)
373 {
374 wm_i2s_tx_enable(0);
375 wm_i2s_rx_enable(0);
376
377 tls_dma_free(tx_channel);
378 tls_dma_free(rx_channel);
379
380 wm_i2s_enable(0);
381 }
382
wm_i2s_tx_int(int16_t * data,uint16_t len,int16_t * next_data)383 int wm_i2s_tx_int(int16_t *data, uint16_t len, int16_t *next_data)
384 {
385 volatile uint32_t temp;
386 volatile uint8_t fifo_level;
387
388 if ((data == NULL) || (len == 0)) {
389 return WM_FAILED;
390 }
391 wm_i2s_buf->txlen = (uint32_t)len;
392 wm_i2s_buf->txtail = 0;
393 wm_i2s_buf->txbuf = (uint32_t *)data;
394 wm_i2s_buf->txdata_done = 0;
395
396 wm_i2s_set_mode(I2S_MODE_MASTER);
397 wm_i2s_txth_int_mask(0);
398 wm_i2s_tx_fifo_clear();
399 tls_irq_enable(I2S_IRQn);
400 wm_i2s_tx_enable(1);
401
402 for (fifo_level = ((I2S->INT_STATUS >> 4) & 0x0F), // 4:byte alignment
403 temp = 0; temp < 8 - fifo_level; temp++) { // 8:byte alignment
404 tls_reg_write32(HR_I2S_TX, wm_i2s_buf->txbuf[wm_i2s_buf->txtail++]);
405 }
406 wm_i2s_enable(1);
407
408 if ((wm_i2s_buf->tx_callback != NULL) && (next_data != NULL)) {
409 wm_i2s_buf->tx_callback((uint32_t *)next_data, &len);
410 }
411 while (wm_i2s_buf->txdata_done == 0);
412 while (tls_reg_read32(HR_I2S_STATUS)&0xF0);
413
414 return WM_SUCCESS;
415 }
416
wm_i2s_tx_dma(int16_t * data,uint16_t len,int16_t * next_data)417 int wm_i2s_tx_dma(int16_t *data, uint16_t len, int16_t *next_data)
418 {
419 if ((data == NULL) || (len == 0)) {
420 return WM_FAILED;
421 }
422 wm_i2s_buf->txdata_done = 0;
423
424 wm_i2s_set_mode(I2S_MODE_MASTER);
425 wm_i2s_dma_tx_init(tx_channel, len*4, data);
426 wm_i2s_dma_start(tx_channel);
427 wm_i2s_tx_dma_enable(1);
428 wm_i2s_tx_enable(1);
429 wm_i2s_enable(1);
430
431 if ((wm_i2s_buf->tx_callback != NULL) && (next_data != NULL)) {
432 wm_i2s_buf->tx_callback((uint32_t *)next_data, &len);
433 }
434 while (wm_i2s_buf->txdata_done == 0);
435 while (tls_reg_read32(HR_I2S_STATUS)&0xF0);
436
437 return WM_SUCCESS;
438 }
439
wm_i2s_tx_dma_link(int16_t * data,uint16_t len,int16_t * next_data)440 int wm_i2s_tx_dma_link(int16_t *data, uint16_t len, int16_t *next_data)
441 {
442 if ((data == NULL) || (next_data == NULL) || (len == 0)) {
443 return WM_FAILED;
444 }
445 uint32_t dma_ctrl;
446 wm_dma_desc dma_desc[2];
447
448 wm_i2s_buf->txdata_done = 0;
449 wm_i2s_set_mode(I2S_MODE_MASTER);
450
451 dma_ctrl = DMA_CTRL_SRC_ADDR_INC | DMA_CTRL_DATA_SIZE_WORD | DMA_CTRL_BURST_SIZE1;
452 dma_ctrl &= ~ 0xFFFF00;
453 dma_ctrl |= ((len*2)<<8);
454
455 dma_desc[0].next = &dma_desc[1];
456 dma_desc[0].dest_addr = HR_I2S_TX;
457 dma_desc[0].src_addr = (unsigned int)data;
458 dma_desc[0].dma_ctrl = dma_ctrl>>1;
459 dma_desc[0].valid = 0x80000000;
460
461 dma_desc[1].next = &dma_desc[0];
462 dma_desc[1].dest_addr = HR_I2S_TX;
463 dma_desc[1].src_addr = (unsigned int)next_data;
464 dma_desc[1].dma_ctrl = dma_ctrl>>1;
465 dma_desc[1].valid = 0x80000000;
466
467 DMA_INTMASK_REG &= ~(0x02<<(tx_channel*2));
468 DMA_MODE_REG(tx_channel) = DMA_MODE_SEL_I2S_TX | DMA_MODE_CHAIN_MODE | DMA_MODE_HARD_MODE | (1<<6);
469 tls_reg_write32(HR_DMA_CHNL0_LINK_DEST_ADDR + 0x30*tx_channel, (uint32_t)dma_desc);
470
471 wm_i2s_dma_start(tx_channel);
472 wm_i2s_tx_dma_enable(1);
473 wm_i2s_tx_enable(1);
474 wm_i2s_enable(1);
475
476 while (1) {
477 if (dma_desc[0].valid == 0) {
478 dma_desc[0].valid = 0x80000000;
479 if (wm_i2s_buf->tx_callback != NULL) {
480 wm_i2s_buf->tx_callback((uint32_t *)data, &len);
481 }
482 }
483 if (dma_desc[1].valid == 0) {
484 dma_desc[1].valid = 0x80000000;
485 if (wm_i2s_buf->tx_callback != NULL) {
486 wm_i2s_buf->tx_callback((uint32_t *)next_data, &len);
487 }
488 }
489 /* todo: a way to break this rountine */
490 if (len == 0xFFFF) {
491 break;
492 }
493 }
494
495 return WM_SUCCESS;
496 }
497
wm_i2s_rx_int(int16_t * data,uint16_t len)498 int wm_i2s_rx_int(int16_t *data, uint16_t len)
499 {
500 if ((data == NULL) || (len == 0)) {
501 return WM_FAILED;
502 }
503 wm_i2s_buf->rxbuf = (uint32_t *)data;
504 wm_i2s_buf->rxlen = (uint32_t)len;
505 wm_i2s_buf->rxhead = 0;
506 wm_i2s_buf->rxdata_ready = 0;
507
508 wm_i2s_set_mode(I2S_MODE_SLAVE);
509 wm_i2s_rxth_int_mask(0);
510 wm_i2s_rx_fifo_clear();
511 tls_irq_enable(I2S_IRQn);
512 wm_i2s_rx_enable(1);
513 wm_i2s_enable(1);
514
515 while (wm_i2s_buf->rxdata_ready == 0);
516
517 return WM_SUCCESS;
518 }
519
wm_i2s_rx_dma(int16_t * data,uint16_t len)520 int wm_i2s_rx_dma(int16_t *data, uint16_t len)
521 {
522 if ((data == NULL) || (len == 0)) {
523 return WM_FAILED;
524 }
525 wm_i2s_buf->rxdata_ready = 0;
526
527 wm_i2s_set_mode(I2S_MODE_SLAVE);
528 wm_i2s_dma_rx_init(rx_channel, len*4, data);
529 wm_i2s_dma_start(rx_channel);
530 wm_i2s_rx_dma_enable(1);
531 wm_i2s_rx_enable(1);
532 wm_i2s_enable(1);
533
534 while (wm_i2s_buf->rxdata_ready == 0);
535
536 return WM_SUCCESS;
537 }
538
wm_i2s_tx_rx_int(I2S_InitDef * opts,int16_t * data_tx,int16_t * data_rx,uint16_t len)539 int wm_i2s_tx_rx_int(I2S_InitDef *opts, int16_t *data_tx, int16_t *data_rx, uint16_t len)
540 {
541 if ((data_tx == NULL) || (data_rx == NULL) || (len == 0)) {
542 return WM_FAILED;
543 }
544 wm_i2s_buf->txbuf = (uint32_t *)data_tx;
545 wm_i2s_buf->txlen = (uint32_t)len;
546 wm_i2s_buf->txtail = 0;
547 wm_i2s_buf->txdata_done = 0;
548
549 wm_i2s_buf->rxbuf = (uint32_t *)data_rx;
550 wm_i2s_buf->rxlen = (uint32_t)len;
551 wm_i2s_buf->rxhead = 0;
552 wm_i2s_buf->rxdata_ready = 0;
553
554 wm_i2s_set_mode(opts->I2S_Mode_MS);
555 #if TEST_WITH_F401
556 (opts->I2S_Trans_STD==I2S_Standard || opts->I2S_Trans_STD==I2S_Standard_MSB)? \
557 (wm_i2s_clk_inverse(0)):(wm_i2s_clk_inverse(1));
558 #endif
559 wm_i2s_txth_int_mask(0);
560 wm_i2s_rxth_int_mask(0);
561 tls_irq_enable(I2S_IRQn);
562 wm_i2s_tx_enable(1);
563 wm_i2s_rx_enable(1);
564 wm_i2s_enable(1);
565
566 while (wm_i2s_buf->txdata_done == 0 || wm_i2s_buf->rxdata_ready == 0);
567 while (tls_reg_read32(HR_I2S_STATUS)&0xF0);
568
569 return WM_SUCCESS;
570 }
571
wm_i2s_tx_rx_dma(I2S_InitDef * opts,int16_t * data_tx,int16_t * data_rx,uint16_t len)572 int wm_i2s_tx_rx_dma(I2S_InitDef *opts, int16_t *data_tx, int16_t *data_rx, uint16_t len)
573 {
574 if ((data_tx == NULL) || (data_rx == NULL) || (len == 0)) {
575 return WM_FAILED;
576 }
577 wm_i2s_buf->txdata_done = 0;
578 wm_i2s_buf->rxdata_ready = 0;
579
580 wm_i2s_set_mode(opts->I2S_Mode_MS);
581 #if TEST_WITH_F401
582 (opts->I2S_Trans_STD==I2S_Standard || \
583 opts->I2S_Trans_STD==I2S_Standard_MSB)?(wm_i2s_clk_inverse(0)):(wm_i2s_clk_inverse(1));
584 #endif
585 wm_i2s_tx_dma_enable(1);
586 wm_i2s_rx_dma_enable(1);
587 wm_i2s_tx_enable(1);
588 wm_i2s_rx_enable(1);
589 wm_i2s_dma_tx_init(tx_channel, len*4, data_tx);
590 wm_i2s_dma_rx_init(rx_channel, len*4, data_rx);
591 wm_i2s_dma_start(tx_channel);
592 wm_i2s_dma_start(rx_channel);
593 wm_i2s_enable(1);
594
595 while (wm_i2s_buf->txdata_done == 0 || wm_i2s_buf->rxdata_ready == 0);
596 while (tls_reg_read32(HR_I2S_STATUS)&0xF0);
597
598 return WM_SUCCESS;
599 }
wm_i2s_receive_dma(wm_dma_handler_type * hdma,uint16_t * data,uint16_t len)600 int wm_i2s_receive_dma(wm_dma_handler_type *hdma, uint16_t *data, uint16_t len)
601 {
602 uint32_t dma_ctrl;
603 wm_dma_desc *dma_desc = &g_dma_desc_rx[0];
604 uint16_t *next_data = &data[(len/2)];
605 if ((data == NULL) || (len == 0)) {
606 return WM_FAILED;
607 }
608
609 wm_i2s_buf->rxdata_ready = 0;
610
611 if (rx_channel) {
612 tls_dma_free(rx_channel);
613 }
614
615 rx_channel = tls_dma_request(WM_I2S_RX_DMA_CHANNEL, TLS_DMA_FLAGS_CHANNEL_SEL(TLS_DMA_SEL_I2S_RX) |
616 TLS_DMA_FLAGS_HARD_MODE);
617 if (rx_channel == 0xFF) {
618 return WM_FAILED;
619 }
620 hdma->channel = rx_channel;
621 if (tls_dma_stop(rx_channel)) {
622 return WM_FAILED;
623 }
624
625 tls_dma_irq_register(rx_channel, i2s_DMA_RX_Channel_IRQHandler, hdma, TLS_DMA_IRQ_TRANSFER_DONE);
626
627 dma_ctrl = DMA_CTRL_DEST_ADDR_INC | DMA_CTRL_DATA_SIZE_WORD | DMA_CTRL_BURST_SIZE1;
628 dma_ctrl &= ~ 0xFFFF00;
629 dma_ctrl |= ((len)<<8); // half length of data
630
631 dma_desc[0].next = &dma_desc[1];
632 dma_desc[0].dest_addr = (unsigned int)data;
633 dma_desc[0].src_addr = HR_I2S_RX;
634 dma_desc[0].dma_ctrl = dma_ctrl>>1;
635 dma_desc[0].valid = 0x80000000;
636
637 dma_desc[1].next = &dma_desc[0];
638 dma_desc[1].dest_addr = (unsigned int)next_data;
639 dma_desc[1].src_addr = HR_I2S_RX;
640 dma_desc[1].dma_ctrl = dma_ctrl>>1;
641 dma_desc[1].valid = 0x80000000;
642
643 DMA_INTMASK_REG &= ~(0x02<<(rx_channel*2));
644 DMA_MODE_REG(rx_channel) = DMA_MODE_SEL_I2S_RX | DMA_MODE_CHAIN_MODE | DMA_MODE_HARD_MODE | DMA_MODE_CHAIN_LINK_EN;
645 tls_reg_write32(HR_DMA_CHNL0_LINK_DEST_ADDR + 0x30*rx_channel, (uint32_t)dma_desc);
646
647 wm_i2s_dma_start(rx_channel);
648 wm_i2s_rx_dma_enable(1);
649 wm_i2s_rx_enable(1);
650 wm_i2s_enable(1);
651 return WM_SUCCESS;
652 }
wm_i2s_transmit_dma(wm_dma_handler_type * hdma,uint16_t * data,uint16_t len)653 int wm_i2s_transmit_dma(wm_dma_handler_type *hdma, uint16_t *data, uint16_t len)
654 {
655 uint32_t dma_ctrl;
656 wm_dma_desc *dma_desc = &g_dma_desc_tx[0];
657 uint16_t *next_data = &data[(len/2)];
658 if ((data == NULL) || (len == 0)) {
659 return WM_FAILED;
660 }
661
662 wm_i2s_buf->txdata_done = 0;
663
664 if (tx_channel) {
665 tls_dma_free(tx_channel);
666 }
667
668 tx_channel = tls_dma_request(WM_I2S_TX_DMA_CHANNEL, TLS_DMA_FLAGS_CHANNEL_SEL(TLS_DMA_SEL_I2S_TX) |
669 TLS_DMA_FLAGS_HARD_MODE);
670 if (tx_channel == 0xFF) {
671 return WM_FAILED;
672 }
673 hdma->channel = tx_channel;
674 if (tls_dma_stop(tx_channel)) {
675 return WM_FAILED;
676 }
677
678 tls_dma_irq_register(tx_channel, i2s_DMA_TX_Channel_IRQHandler, hdma, TLS_DMA_IRQ_TRANSFER_DONE);
679
680 dma_ctrl = DMA_CTRL_SRC_ADDR_INC | DMA_CTRL_DATA_SIZE_WORD | DMA_CTRL_BURST_SIZE1;
681 dma_ctrl &= ~ 0xFFFF00;
682 dma_ctrl |= ((len)<<8); // half length of data
683
684 dma_desc[0].next = &dma_desc[1];
685 dma_desc[0].dest_addr = HR_I2S_TX;
686 dma_desc[0].src_addr = (unsigned int)data;
687 dma_desc[0].dma_ctrl = dma_ctrl>>1;
688 dma_desc[0].valid = 0x80000000;
689
690 dma_desc[1].next = &dma_desc[0];
691 dma_desc[1].dest_addr = HR_I2S_TX;
692 dma_desc[1].src_addr = (unsigned int)next_data;
693 dma_desc[1].dma_ctrl = dma_ctrl>>1;
694 dma_desc[1].valid = 0x80000000;
695
696 DMA_INTMASK_REG &= ~(0x02<<(tx_channel*2));
697 DMA_MODE_REG(tx_channel) = DMA_MODE_SEL_I2S_TX | DMA_MODE_CHAIN_MODE | DMA_MODE_HARD_MODE | DMA_MODE_CHAIN_LINK_EN;
698 tls_reg_write32(HR_DMA_CHNL0_LINK_DEST_ADDR + 0x30*tx_channel, (uint32_t)dma_desc);
699
700 wm_i2s_dma_start(tx_channel);
701 wm_i2s_tx_dma_enable(1);
702 wm_i2s_tx_enable(1);
703 wm_i2s_enable(1);
704 return WM_SUCCESS;
705 }
706
wm_i2s_tranceive_dma(uint32_t i2s_mode,wm_dma_handler_type * hdma_tx,wm_dma_handler_type * hdma_rx,uint16_t * data_tx,uint16_t * data_rx,uint16_t len)707 int wm_i2s_tranceive_dma(uint32_t i2s_mode, wm_dma_handler_type *hdma_tx, wm_dma_handler_type *hdma_rx,
708 uint16_t *data_tx, uint16_t *data_rx, uint16_t len)
709 {
710 uint32_t dma_ctrl;
711 wm_dma_desc *dma_desc_tx = &g_dma_desc_tx[0];
712 wm_dma_desc *dma_desc_rx = &g_dma_desc_rx[0];
713 uint16_t *next_data_tx = &data_tx[(len/2)];
714 uint16_t *next_data_rx = &data_rx[(len/2)];
715 if ((data_tx == NULL) || (data_rx == NULL) || (len == 0)) {
716 return WM_FAILED;
717 }
718
719 wm_i2s_buf->txdata_done = 0;
720 wm_i2s_buf->rxdata_ready = 0;
721 wm_i2s_set_mode(i2s_mode);
722
723 if (tx_channel) {
724 tls_dma_free(tx_channel);
725 }
726
727 tx_channel = tls_dma_request(WM_I2S_TX_DMA_CHANNEL, TLS_DMA_FLAGS_CHANNEL_SEL(TLS_DMA_SEL_I2S_TX) |
728 TLS_DMA_FLAGS_HARD_MODE);
729 if (tx_channel == 0xFF) {
730 return WM_FAILED;
731 }
732 hdma_tx->channel = tx_channel;
733 if (tls_dma_stop(tx_channel)) {
734 return WM_FAILED;
735 }
736
737 tls_dma_irq_register(tx_channel, i2s_DMA_TX_Channel_IRQHandler, hdma_tx, TLS_DMA_IRQ_TRANSFER_DONE);
738
739 dma_ctrl = DMA_CTRL_SRC_ADDR_INC | DMA_CTRL_DATA_SIZE_WORD | DMA_CTRL_BURST_SIZE1;
740 dma_ctrl &= ~ 0xFFFF00;
741 dma_ctrl |= ((len)<<8); // half length of data
742
743 dma_desc_tx[0].next = &dma_desc_tx[1];
744 dma_desc_tx[0].dest_addr = HR_I2S_TX;
745 dma_desc_tx[0].src_addr = (unsigned int)data_tx;
746 dma_desc_tx[0].dma_ctrl = dma_ctrl>>1;
747 dma_desc_tx[0].valid = 0x80000000;
748
749 dma_desc_tx[1].next = &dma_desc_tx[0];
750 dma_desc_tx[1].dest_addr = HR_I2S_TX;
751 dma_desc_tx[1].src_addr = (unsigned int)next_data_tx;
752 dma_desc_tx[1].dma_ctrl = dma_ctrl>>1;
753 dma_desc_tx[1].valid = 0x80000000;
754 DMA_MODE_REG(tx_channel) = DMA_MODE_SEL_I2S_TX | DMA_MODE_CHAIN_MODE | DMA_MODE_HARD_MODE | DMA_MODE_CHAIN_LINK_EN;
755 tls_reg_write32(HR_DMA_CHNL0_LINK_DEST_ADDR + 0x30*tx_channel, (uint32_t)dma_desc_tx);
756
757 if (rx_channel) {
758 tls_dma_free(rx_channel);
759 }
760
761 rx_channel = tls_dma_request(WM_I2S_RX_DMA_CHANNEL,
762 TLS_DMA_FLAGS_CHANNEL_SEL(TLS_DMA_SEL_I2S_RX) | TLS_DMA_FLAGS_HARD_MODE);
763 if (rx_channel == 0xFF) {
764 return WM_FAILED;
765 }
766 hdma_rx->channel = rx_channel;
767 if (tls_dma_stop(rx_channel)) {
768 return WM_FAILED;
769 }
770
771 tls_dma_irq_register(rx_channel, i2s_DMA_RX_Channel_IRQHandler, hdma_rx, TLS_DMA_IRQ_TRANSFER_DONE);
772
773 dma_ctrl = DMA_CTRL_DEST_ADDR_INC | DMA_CTRL_DATA_SIZE_WORD | DMA_CTRL_BURST_SIZE1;
774 dma_ctrl &= ~ 0xFFFF00;
775 dma_ctrl |= ((len)<<8); // half length of data
776
777 dma_desc_rx[0].next = &dma_desc_rx[1];
778 dma_desc_rx[0].dest_addr = (unsigned int)data_rx;
779 dma_desc_rx[0].src_addr = HR_I2S_RX;
780 dma_desc_rx[0].dma_ctrl = dma_ctrl>>1;
781 dma_desc_rx[0].valid = 0x80000000;
782
783 dma_desc_rx[1].next = &dma_desc_rx[0];
784 dma_desc_rx[1].dest_addr = (unsigned int)next_data_rx;
785 dma_desc_rx[1].src_addr = HR_I2S_RX;
786 dma_desc_rx[1].dma_ctrl = dma_ctrl>>1;
787 dma_desc_rx[1].valid = 0x80000000;
788 DMA_MODE_REG(rx_channel) = DMA_MODE_SEL_I2S_RX | DMA_MODE_CHAIN_MODE | DMA_MODE_HARD_MODE | DMA_MODE_CHAIN_LINK_EN;
789 tls_reg_write32(HR_DMA_CHNL0_LINK_DEST_ADDR + 0x30*rx_channel, (uint32_t)dma_desc_rx);
790
791 wm_i2s_dma_start(rx_channel);
792 wm_i2s_rx_dma_enable(1);
793 wm_i2s_rx_enable(1);
794
795 wm_i2s_dma_start(tx_channel);
796 wm_i2s_tx_dma_enable(1);
797 wm_i2s_tx_enable(1);
798 wm_i2s_enable(1);
799 return WM_SUCCESS;
800 }