1NVIDIA Tegra host1x 2 3Required properties: 4- compatible: "nvidia,tegra<chip>-host1x" 5- reg: Physical base address and length of the controller's registers. 6 For pre-Tegra186, one entry describing the whole register area. 7 For Tegra186, one entry for each entry in reg-names: 8 "vm" - VM region assigned to Linux 9 "hypervisor" - Hypervisor region (only if Linux acts as hypervisor) 10- interrupts: The interrupt outputs from the controller. 11- #address-cells: The number of cells used to represent physical base addresses 12 in the host1x address space. Should be 1. 13- #size-cells: The number of cells used to represent the size of an address 14 range in the host1x address space. Should be 1. 15- ranges: The mapping of the host1x address space to the CPU address space. 16- clocks: Must contain one entry, for the module clock. 17 See ../clocks/clock-bindings.txt for details. 18- resets: Must contain an entry for each entry in reset-names. 19 See ../reset/reset.txt for details. 20- reset-names: Must include the following entries: 21 - host1x 22 23The host1x top-level node defines a number of children, each representing one 24of the following host1x client modules: 25 26- mpe: video encoder 27 28 Required properties: 29 - compatible: "nvidia,tegra<chip>-mpe" 30 - reg: Physical base address and length of the controller's registers. 31 - interrupts: The interrupt outputs from the controller. 32 - clocks: Must contain one entry, for the module clock. 33 See ../clocks/clock-bindings.txt for details. 34 - resets: Must contain an entry for each entry in reset-names. 35 See ../reset/reset.txt for details. 36 - reset-names: Must include the following entries: 37 - mpe 38 39- vi: video input 40 41 Required properties: 42 - compatible: "nvidia,tegra<chip>-vi" 43 - reg: Physical base address and length of the controller registers. 44 - interrupts: The interrupt outputs from the controller. 45 - clocks: clocks: Must contain one entry, for the module clock. 46 See ../clocks/clock-bindings.txt for details. 47 - Tegra20/Tegra30/Tegra114/Tegra124: 48 - resets: Must contain an entry for each entry in reset-names. 49 See ../reset/reset.txt for details. 50 - reset-names: Must include the following entries: 51 - vi 52 - Tegra210: 53 - power-domains: Must include venc powergate node as vi is in VE partition. 54 55 ports (optional node) 56 vi can have optional ports node and max 6 ports are supported. Each port 57 should have single 'endpoint' child node. All port nodes are grouped under 58 ports node. Please refer to the bindings defined in 59 Documentation/devicetree/bindings/media/video-interfaces.txt 60 61 csi (required node) 62 Tegra210 has CSI part of VI sharing same host interface and register space. 63 So, VI device node should have CSI child node. 64 65 - csi: mipi csi interface to vi 66 67 Required properties: 68 - compatible: "nvidia,tegra210-csi" 69 - reg: Physical base address offset to parent and length of the controller 70 registers. 71 - clocks: Must contain entries csi, cilab, cilcd, cile, csi_tpg clocks. 72 See ../clocks/clock-bindings.txt for details. 73 - power-domains: Must include sor powergate node as csicil is in 74 SOR partition. 75 76 channel (optional nodes) 77 Maximum 6 channels are supported with each csi brick as either x4 or x2 78 based on hw connectivity to sensor. 79 80 Required properties: 81 - reg: csi port number. Valid port numbers are 0 through 5. 82 - nvidia,mipi-calibrate: Should contain a phandle and a specifier 83 specifying which pads are used by this CSI port and need to be 84 calibrated. See also ../display/tegra/nvidia,tegra114-mipi.txt. 85 86 Each channel node must contain 2 port nodes which can be grouped 87 under 'ports' node and each port should have a single child 'endpoint' 88 node. 89 90 ports node 91 Please refer to the bindings defined in 92 Documentation/devicetree/bindings/media/video-interfaces.txt 93 94 ports node must contain below 2 port nodes. 95 port@0 with single child 'endpoint' node always a sink. 96 port@1 with single child 'endpoint' node always a source. 97 98 port@0 (required node) 99 Required properties: 100 - reg: 0 101 102 endpoint (required node) 103 Required properties: 104 - data-lanes: an array of data lane from 1 to 4. Valid array 105 lengths are 1/2/4. 106 - remote-endpoint: phandle to sensor 'endpoint' node. 107 108 port@1 (required node) 109 Required properties: 110 - reg: 1 111 112 endpoint (required node) 113 Required properties: 114 - remote-endpoint: phandle to vi port 'endpoint' node. 115 116- epp: encoder pre-processor 117 118 Required properties: 119 - compatible: "nvidia,tegra<chip>-epp" 120 - reg: Physical base address and length of the controller's registers. 121 - interrupts: The interrupt outputs from the controller. 122 - clocks: Must contain one entry, for the module clock. 123 See ../clocks/clock-bindings.txt for details. 124 - resets: Must contain an entry for each entry in reset-names. 125 See ../reset/reset.txt for details. 126 - reset-names: Must include the following entries: 127 - epp 128 129- isp: image signal processor 130 131 Required properties: 132 - compatible: "nvidia,tegra<chip>-isp" 133 - reg: Physical base address and length of the controller's registers. 134 - interrupts: The interrupt outputs from the controller. 135 - clocks: Must contain one entry, for the module clock. 136 See ../clocks/clock-bindings.txt for details. 137 - resets: Must contain an entry for each entry in reset-names. 138 See ../reset/reset.txt for details. 139 - reset-names: Must include the following entries: 140 - isp 141 142- gr2d: 2D graphics engine 143 144 Required properties: 145 - compatible: "nvidia,tegra<chip>-gr2d" 146 - reg: Physical base address and length of the controller's registers. 147 - interrupts: The interrupt outputs from the controller. 148 - clocks: Must contain one entry, for the module clock. 149 See ../clocks/clock-bindings.txt for details. 150 - resets: Must contain an entry for each entry in reset-names. 151 See ../reset/reset.txt for details. 152 - reset-names: Must include the following entries: 153 - 2d 154 155- gr3d: 3D graphics engine 156 157 Required properties: 158 - compatible: "nvidia,tegra<chip>-gr3d" 159 - reg: Physical base address and length of the controller's registers. 160 - clocks: Must contain an entry for each entry in clock-names. 161 See ../clocks/clock-bindings.txt for details. 162 - clock-names: Must include the following entries: 163 (This property may be omitted if the only clock in the list is "3d") 164 - 3d 165 This MUST be the first entry. 166 - 3d2 (Only required on SoCs with two 3D clocks) 167 - resets: Must contain an entry for each entry in reset-names. 168 See ../reset/reset.txt for details. 169 - reset-names: Must include the following entries: 170 - 3d 171 - 3d2 (Only required on SoCs with two 3D clocks) 172 173- dc: display controller 174 175 Required properties: 176 - compatible: "nvidia,tegra<chip>-dc" 177 - reg: Physical base address and length of the controller's registers. 178 - interrupts: The interrupt outputs from the controller. 179 - clocks: Must contain an entry for each entry in clock-names. 180 See ../clocks/clock-bindings.txt for details. 181 - clock-names: Must include the following entries: 182 - dc 183 This MUST be the first entry. 184 - parent 185 - resets: Must contain an entry for each entry in reset-names. 186 See ../reset/reset.txt for details. 187 - reset-names: Must include the following entries: 188 - dc 189 - nvidia,head: The number of the display controller head. This is used to 190 setup the various types of output to receive video data from the given 191 head. 192 193 Each display controller node has a child node, named "rgb", that represents 194 the RGB output associated with the controller. It can take the following 195 optional properties: 196 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing 197 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection 198 - nvidia,edid: supplies a binary EDID blob 199 - nvidia,panel: phandle of a display panel 200 201- hdmi: High Definition Multimedia Interface 202 203 Required properties: 204 - compatible: "nvidia,tegra<chip>-hdmi" 205 - reg: Physical base address and length of the controller's registers. 206 - interrupts: The interrupt outputs from the controller. 207 - hdmi-supply: supply for the +5V HDMI connector pin 208 - vdd-supply: regulator for supply voltage 209 - pll-supply: regulator for PLL 210 - clocks: Must contain an entry for each entry in clock-names. 211 See ../clocks/clock-bindings.txt for details. 212 - clock-names: Must include the following entries: 213 - hdmi 214 This MUST be the first entry. 215 - parent 216 - resets: Must contain an entry for each entry in reset-names. 217 See ../reset/reset.txt for details. 218 - reset-names: Must include the following entries: 219 - hdmi 220 221 Optional properties: 222 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing 223 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection 224 - nvidia,edid: supplies a binary EDID blob 225 - nvidia,panel: phandle of a display panel 226 227- tvo: TV encoder output 228 229 Required properties: 230 - compatible: "nvidia,tegra<chip>-tvo" 231 - reg: Physical base address and length of the controller's registers. 232 - interrupts: The interrupt outputs from the controller. 233 - clocks: Must contain one entry, for the module clock. 234 See ../clocks/clock-bindings.txt for details. 235 236- dsi: display serial interface 237 238 Required properties: 239 - compatible: "nvidia,tegra<chip>-dsi" 240 - reg: Physical base address and length of the controller's registers. 241 - clocks: Must contain an entry for each entry in clock-names. 242 See ../clocks/clock-bindings.txt for details. 243 - clock-names: Must include the following entries: 244 - dsi 245 This MUST be the first entry. 246 - lp 247 - parent 248 - resets: Must contain an entry for each entry in reset-names. 249 See ../reset/reset.txt for details. 250 - reset-names: Must include the following entries: 251 - dsi 252 - avdd-dsi-supply: phandle of a supply that powers the DSI controller 253 - nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying 254 which pads are used by this DSI output and need to be calibrated. See also 255 ../display/tegra/nvidia,tegra114-mipi.txt. 256 257 Optional properties: 258 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing 259 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection 260 - nvidia,edid: supplies a binary EDID blob 261 - nvidia,panel: phandle of a display panel 262 - nvidia,ganged-mode: contains a phandle to a second DSI controller to gang 263 up with in order to support up to 8 data lanes 264 265- sor: serial output resource 266 267 Required properties: 268 - compatible: Should be: 269 - "nvidia,tegra124-sor": for Tegra124 and Tegra132 270 - "nvidia,tegra132-sor": for Tegra132 271 - "nvidia,tegra210-sor": for Tegra210 272 - "nvidia,tegra210-sor1": for Tegra210 273 - "nvidia,tegra186-sor": for Tegra186 274 - "nvidia,tegra186-sor1": for Tegra186 275 - reg: Physical base address and length of the controller's registers. 276 - interrupts: The interrupt outputs from the controller. 277 - clocks: Must contain an entry for each entry in clock-names. 278 See ../clocks/clock-bindings.txt for details. 279 - clock-names: Must include the following entries: 280 - sor: clock input for the SOR hardware 281 - out: SOR output clock 282 - parent: input for the pixel clock 283 - dp: reference clock for the SOR clock 284 - safe: safe reference for the SOR clock during power up 285 286 For Tegra186 and later: 287 - pad: SOR pad output clock (on Tegra186 and later) 288 289 Obsolete: 290 - source: source clock for the SOR clock (obsolete, use "out" instead) 291 292 - resets: Must contain an entry for each entry in reset-names. 293 See ../reset/reset.txt for details. 294 - reset-names: Must include the following entries: 295 - sor 296 297 Required properties on Tegra186 and later: 298 - nvidia,interface: index of the SOR interface 299 300 Optional properties: 301 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing 302 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection 303 - nvidia,edid: supplies a binary EDID blob 304 - nvidia,panel: phandle of a display panel 305 - nvidia,xbar-cfg: 5 cells containing the crossbar configuration. Each lane 306 of the SOR, identified by the cell's index, is mapped via the crossbar to 307 the pad specified by the cell's value. 308 309 Optional properties when driving an eDP output: 310 - nvidia,dpaux: phandle to a DispayPort AUX interface 311 312- dpaux: DisplayPort AUX interface 313 - compatible : Should contain one of the following: 314 - "nvidia,tegra124-dpaux": for Tegra124 and Tegra132 315 - "nvidia,tegra210-dpaux": for Tegra210 316 - reg: Physical base address and length of the controller's registers. 317 - interrupts: The interrupt outputs from the controller. 318 - clocks: Must contain an entry for each entry in clock-names. 319 See ../clocks/clock-bindings.txt for details. 320 - clock-names: Must include the following entries: 321 - dpaux: clock input for the DPAUX hardware 322 - parent: reference clock 323 - resets: Must contain an entry for each entry in reset-names. 324 See ../reset/reset.txt for details. 325 - reset-names: Must include the following entries: 326 - dpaux 327 - vdd-supply: phandle of a supply that powers the DisplayPort link 328 - i2c-bus: Subnode where I2C slave devices are listed. This subnode 329 must be always present. If there are no I2C slave devices, an empty 330 node should be added. See ../../i2c/i2c.txt for more information. 331 332 See ../pinctrl/nvidia,tegra124-dpaux-padctl.txt for information 333 regarding the DPAUX pad controller bindings. 334 335- vic: Video Image Compositor 336 - compatible : "nvidia,tegra<chip>-vic" 337 - reg: Physical base address and length of the controller's registers. 338 - interrupts: The interrupt outputs from the controller. 339 - clocks: Must contain an entry for each entry in clock-names. 340 See ../clocks/clock-bindings.txt for details. 341 - clock-names: Must include the following entries: 342 - vic: clock input for the VIC hardware 343 - resets: Must contain an entry for each entry in reset-names. 344 See ../reset/reset.txt for details. 345 - reset-names: Must include the following entries: 346 - vic 347 348Example: 349 350/ { 351 ... 352 353 host1x { 354 compatible = "nvidia,tegra20-host1x", "simple-bus"; 355 reg = <0x50000000 0x00024000>; 356 interrupts = <0 65 0x04 /* mpcore syncpt */ 357 0 67 0x04>; /* mpcore general */ 358 clocks = <&tegra_car TEGRA20_CLK_HOST1X>; 359 resets = <&tegra_car 28>; 360 reset-names = "host1x"; 361 362 #address-cells = <1>; 363 #size-cells = <1>; 364 365 ranges = <0x54000000 0x54000000 0x04000000>; 366 367 mpe { 368 compatible = "nvidia,tegra20-mpe"; 369 reg = <0x54040000 0x00040000>; 370 interrupts = <0 68 0x04>; 371 clocks = <&tegra_car TEGRA20_CLK_MPE>; 372 resets = <&tegra_car 60>; 373 reset-names = "mpe"; 374 }; 375 376 vi@54080000 { 377 compatible = "nvidia,tegra210-vi"; 378 reg = <0x0 0x54080000 0x0 0x700>; 379 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 380 assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; 381 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 382 383 clocks = <&tegra_car TEGRA210_CLK_VI>; 384 power-domains = <&pd_venc>; 385 386 #address-cells = <1>; 387 #size-cells = <1>; 388 389 ranges = <0x0 0x0 0x54080000 0x2000>; 390 391 ports { 392 #address-cells = <1>; 393 #size-cells = <0>; 394 395 port@0 { 396 reg = <0>; 397 imx219_vi_in0: endpoint { 398 remote-endpoint = <&imx219_csi_out0>; 399 }; 400 }; 401 }; 402 403 csi@838 { 404 compatible = "nvidia,tegra210-csi"; 405 reg = <0x838 0x1300>; 406 assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, 407 <&tegra_car TEGRA210_CLK_CILCD>, 408 <&tegra_car TEGRA210_CLK_CILE>, 409 <&tegra_car TEGRA210_CLK_CSI_TPG>; 410 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, 411 <&tegra_car TEGRA210_CLK_PLL_P>, 412 <&tegra_car TEGRA210_CLK_PLL_P>; 413 assigned-clock-rates = <102000000>, 414 <102000000>, 415 <102000000>, 416 <972000000>; 417 418 clocks = <&tegra_car TEGRA210_CLK_CSI>, 419 <&tegra_car TEGRA210_CLK_CILAB>, 420 <&tegra_car TEGRA210_CLK_CILCD>, 421 <&tegra_car TEGRA210_CLK_CILE>, 422 <&tegra_car TEGRA210_CLK_CSI_TPG>; 423 clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; 424 power-domains = <&pd_sor>; 425 426 #address-cells = <1>; 427 #size-cells = <0>; 428 429 channel@0 { 430 reg = <0>; 431 nvidia,mipi-calibrate = <&mipi 0x001>; 432 433 ports { 434 #address-cells = <1>; 435 #size-cells = <0>; 436 437 port@0 { 438 reg = <0>; 439 imx219_csi_in0: endpoint { 440 data-lanes = <1 2>; 441 remote-endpoint = <&imx219_out0>; 442 }; 443 }; 444 445 port@1 { 446 reg = <1>; 447 imx219_csi_out0: endpoint { 448 remote-endpoint = <&imx219_vi_in0>; 449 }; 450 }; 451 }; 452 }; 453 }; 454 }; 455 456 epp { 457 compatible = "nvidia,tegra20-epp"; 458 reg = <0x540c0000 0x00040000>; 459 interrupts = <0 70 0x04>; 460 clocks = <&tegra_car TEGRA20_CLK_EPP>; 461 resets = <&tegra_car 19>; 462 reset-names = "epp"; 463 }; 464 465 isp { 466 compatible = "nvidia,tegra20-isp"; 467 reg = <0x54100000 0x00040000>; 468 interrupts = <0 71 0x04>; 469 clocks = <&tegra_car TEGRA20_CLK_ISP>; 470 resets = <&tegra_car 23>; 471 reset-names = "isp"; 472 }; 473 474 gr2d { 475 compatible = "nvidia,tegra20-gr2d"; 476 reg = <0x54140000 0x00040000>; 477 interrupts = <0 72 0x04>; 478 clocks = <&tegra_car TEGRA20_CLK_GR2D>; 479 resets = <&tegra_car 21>; 480 reset-names = "2d"; 481 }; 482 483 gr3d { 484 compatible = "nvidia,tegra20-gr3d"; 485 reg = <0x54180000 0x00040000>; 486 clocks = <&tegra_car TEGRA20_CLK_GR3D>; 487 resets = <&tegra_car 24>; 488 reset-names = "3d"; 489 }; 490 491 dc@54200000 { 492 compatible = "nvidia,tegra20-dc"; 493 reg = <0x54200000 0x00040000>; 494 interrupts = <0 73 0x04>; 495 clocks = <&tegra_car TEGRA20_CLK_DISP1>, 496 <&tegra_car TEGRA20_CLK_PLL_P>; 497 clock-names = "dc", "parent"; 498 resets = <&tegra_car 27>; 499 reset-names = "dc"; 500 501 rgb { 502 status = "disabled"; 503 }; 504 }; 505 506 dc@54240000 { 507 compatible = "nvidia,tegra20-dc"; 508 reg = <0x54240000 0x00040000>; 509 interrupts = <0 74 0x04>; 510 clocks = <&tegra_car TEGRA20_CLK_DISP2>, 511 <&tegra_car TEGRA20_CLK_PLL_P>; 512 clock-names = "dc", "parent"; 513 resets = <&tegra_car 26>; 514 reset-names = "dc"; 515 516 rgb { 517 status = "disabled"; 518 }; 519 }; 520 521 hdmi { 522 compatible = "nvidia,tegra20-hdmi"; 523 reg = <0x54280000 0x00040000>; 524 interrupts = <0 75 0x04>; 525 clocks = <&tegra_car TEGRA20_CLK_HDMI>, 526 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; 527 clock-names = "hdmi", "parent"; 528 resets = <&tegra_car 51>; 529 reset-names = "hdmi"; 530 status = "disabled"; 531 }; 532 533 tvo { 534 compatible = "nvidia,tegra20-tvo"; 535 reg = <0x542c0000 0x00040000>; 536 interrupts = <0 76 0x04>; 537 clocks = <&tegra_car TEGRA20_CLK_TVO>; 538 status = "disabled"; 539 }; 540 541 dsi { 542 compatible = "nvidia,tegra20-dsi"; 543 reg = <0x54300000 0x00040000>; 544 clocks = <&tegra_car TEGRA20_CLK_DSI>, 545 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; 546 clock-names = "dsi", "parent"; 547 resets = <&tegra_car 48>; 548 reset-names = "dsi"; 549 status = "disabled"; 550 }; 551 }; 552 553 ... 554}; 555